Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T23,T24
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T23,T24
1	0	Covered	T7,T23,T24
1	1	Covered	T7,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T46,T48,T66
1	0	Covered	T66,T70,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
1	0	Covered	T81,T235,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T23,T24
1	-	Covered	T7,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T23,T24
DetectSt	168	Covered	T7,T23,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T23,T24
DebounceSt->IdleSt	163	Covered	T183,T53,T54
DetectSt->IdleSt	186	Covered	T46,T48,T66
DetectSt->StableSt	191	Covered	T7,T23,T24
IdleSt->DebounceSt	148	Covered	T7,T23,T24
StableSt->IdleSt	206	Covered	T7,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T23,T24
0	1	Covered	T7,T23,T24
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T23,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T7,T23,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T53,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T46,T48,T66
DetectSt	-	-	-	-	0	1	-	Covered	T7,T23,T24
DetectSt	-	-	-	-	0	0	-	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	1	Covered	T7,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T7,T23,T24
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	3358	0	0
CntIncr_A	8343984	118036	0	0
CntNoWrap_A	8343984	7669160	0	0
DetectStDropOut_A	8343984	522	0	0
DetectedOut_A	8343984	79563	0	0
DetectedPulseOut_A	8343984	842	0	0
DisabledIdleSt_A	8343984	7176399	0	0
DisabledNoDetection_A	8343984	7178659	0	0
EnterDebounceSt_A	8343984	1687	0	0
EnterDetectSt_A	8343984	1671	0	0
EnterStableSt_A	8343984	842	0	0
PulseIsPulse_A	8343984	842	0	0
StayInStableSt	8343984	78630	0	0
gen_high_event_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	744	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	3358	0	0
T7	23528	42	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	50	0	0
T24	20075	4	0	0
T30	0	44	0	0
T45	12897	0	0	0
T46	0	28	0	0
T48	0	24	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	54	0	0
T68	0	58	0	0
T69	0	26	0	0
T70	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	118036	0	0
T7	23528	3822	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	2325	0	0
T24	20075	122	0	0
T30	0	1386	0	0
T45	12897	0	0	0
T46	0	818	0	0
T48	0	641	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	1376	0	0
T68	0	2291	0	0
T69	0	923	0	0
T70	0	382	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7669160	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	522	0	0
T11	2230	0	0	0
T12	10358	0	0	0
T46	5599	14	0	0
T47	50219	0	0	0
T48	5317	12	0	0
T55	741	0	0	0
T63	2260	0	0	0
T64	528	0	0	0
T66	0	21	0	0
T70	0	3	0	0
T95	0	12	0	0
T97	0	10	0	0
T101	0	3	0	0
T128	0	2	0	0
T190	449	0	0	0
T215	424	0	0	0
T217	0	11	0	0
T219	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	79563	0	0
T7	23528	5843	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	2239	0	0
T24	20075	129	0	0
T30	0	2077	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	1861	0	0
T69	0	398	0	0
T80	0	595	0	0
T183	0	5	0	0
T196	0	1310	0	0
T236	0	1723	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	842	0	0
T7	23528	21	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	2	0	0
T30	0	22	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	29	0	0
T69	0	13	0	0
T80	0	5	0	0
T183	0	2	0	0
T196	0	27	0	0
T236	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7176399	0	0
T1	7746	7336	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69707	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7178659	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1687	0	0
T7	23528	21	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	2	0	0
T30	0	22	0	0
T45	12897	0	0	0
T46	0	14	0	0
T48	0	12	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	27	0	0
T68	0	29	0	0
T69	0	13	0	0
T70	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	1671	0	0
T7	23528	21	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	2	0	0
T30	0	22	0	0
T45	12897	0	0	0
T46	0	14	0	0
T48	0	12	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T66	0	27	0	0
T68	0	29	0	0
T69	0	13	0	0
T70	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	842	0	0
T7	23528	21	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	2	0	0
T30	0	22	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	29	0	0
T69	0	13	0	0
T80	0	5	0	0
T183	0	2	0	0
T196	0	27	0	0
T236	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	842	0	0
T7	23528	21	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	2	0	0
T30	0	22	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	29	0	0
T69	0	13	0	0
T80	0	5	0	0
T183	0	2	0	0
T196	0	27	0	0
T236	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	78630	0	0
T7	23528	5821	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	2214	0	0
T24	20075	126	0	0
T30	0	2055	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	1832	0	0
T69	0	385	0	0
T80	0	588	0	0
T183	0	3	0	0
T196	0	1283	0	0
T236	0	1716	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	744	0	0
T7	23528	20	0	0
T8	1925	0	0	0
T9	1884	0	0	0
T10	575	0	0	0
T23	12392	25	0	0
T24	20075	1	0	0
T30	0	22	0	0
T45	12897	0	0	0
T50	672	0	0	0
T51	406	0	0	0
T52	525	0	0	0
T68	0	29	0	0
T69	0	13	0	0
T80	0	3	0	0
T183	0	2	0	0
T196	0	27	0	0
T236	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T32,T163
1	0	Covered	T53,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T23
0	1	Covered	T1,T7,T23
1	0	Covered	T237

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T23
1	-	Covered	T1,T7,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T7
DetectSt	168	Covered	T1,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T7,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T7
DebounceSt->IdleSt	163	Covered	T6,T31,T68
DetectSt->IdleSt	186	Covered	T6,T32,T163
DetectSt->StableSt	191	Covered	T1,T7,T23
IdleSt->DebounceSt	148	Covered	T1,T6,T7
StableSt->IdleSt	206	Covered	T1,T7,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T31,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T6,T32,T163
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T23
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8343984	789	0	0
CntIncr_A	8343984	44704	0	0
CntNoWrap_A	8343984	7671729	0	0
DetectStDropOut_A	8343984	26	0	0
DetectedOut_A	8343984	14465	0	0
DetectedPulseOut_A	8343984	346	0	0
DisabledIdleSt_A	8343984	7261812	0	0
DisabledNoDetection_A	8343984	7263539	0	0
EnterDebounceSt_A	8343984	415	0	0
EnterDetectSt_A	8343984	375	0	0
EnterStableSt_A	8343984	346	0	0
PulseIsPulse_A	8343984	346	0	0
StayInStableSt	8343984	14097	0	0
gen_high_level_sva.HighLevelEvent_A	8343984	7674965	0	0
gen_not_sticky_sva.StableStDropOut_A	8343984	322	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	789	0	0
T1	7746	4	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	3	0	0
T7	0	10	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	6	0	0
T24	0	2	0	0
T29	0	8	0	0
T30	0	8	0	0
T31	0	33	0	0
T45	0	4	0	0
T68	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	44704	0	0
T1	7746	210	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	161	0	0
T7	0	865	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	258	0	0
T24	0	66	0	0
T29	0	620	0	0
T30	0	364	0	0
T31	0	1915	0	0
T45	0	120	0	0
T68	0	225	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7671729	0	0
T1	7746	7332	0	0
T2	191888	186462	0	0
T3	11238	5886	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	69704	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	26	0	0
T6	76975	1	0	0
T7	23528	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T32	0	4	0	0
T42	722	0	0	0
T43	695	0	0	0
T44	5814	0	0	0
T50	672	0	0	0
T53	0	1	0	0
T59	495	0	0	0
T74	454	0	0	0
T98	0	2	0	0
T163	0	1	0	0
T238	0	1	0	0
T239	0	7	0	0
T240	0	1	0	0
T241	0	1	0	0
T242	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14465	0	0
T1	7746	59	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T7	0	440	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	800	0	0
T24	0	38	0	0
T29	0	54	0	0
T30	0	189	0	0
T31	0	481	0	0
T38	0	15	0	0
T45	0	13	0	0
T68	0	223	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	346	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T7	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	14	0	0
T38	0	1	0	0
T45	0	2	0	0
T68	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7261812	0	0
T1	7746	4030	0	0
T2	191888	186462	0	0
T3	11238	5697	0	0
T4	491	90	0	0
T5	582	181	0	0
T6	76975	64625	0	0
T13	637	236	0	0
T14	422	21	0	0
T15	405	4	0	0
T16	5222	1011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7263539	0	0
T1	7746	4030	0	0
T2	191888	186477	0	0
T3	11238	5709	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	64642	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	415	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	2	0	0
T7	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	19	0	0
T45	0	2	0	0
T68	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	375	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	1	0	0
T7	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	14	0	0
T45	0	2	0	0
T68	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	346	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T7	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	14	0	0
T38	0	1	0	0
T45	0	2	0	0
T68	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	346	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T7	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	14	0	0
T38	0	1	0	0
T45	0	2	0	0
T68	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	14097	0	0
T1	7746	57	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T7	0	435	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	797	0	0
T24	0	36	0	0
T29	0	50	0	0
T30	0	185	0	0
T31	0	467	0	0
T38	0	14	0	0
T45	0	11	0	0
T68	0	220	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	7674965	0	0
T1	7746	7338	0	0
T2	191888	186477	0	0
T3	11238	5899	0	0
T4	491	91	0	0
T5	582	182	0	0
T6	76975	69733	0	0
T13	637	237	0	0
T14	422	22	0	0
T15	405	5	0	0
T16	5222	1024	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8343984	322	0	0
T1	7746	2	0	0
T2	191888	0	0	0
T3	11238	0	0	0
T6	76975	0	0	0
T7	0	5	0	0
T13	637	0	0	0
T14	422	0	0	0
T15	405	0	0	0
T16	5222	0	0	0
T17	1411	0	0	0
T18	691	0	0	0
T23	0	3	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	14	0	0
T38	0	1	0	0
T45	0	2	0	0
T68	0	3	0	0
T224	0	5	0	0