Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1353810099	11430	0	0
auto_block_debounce_ctl_rd_A	1353810099	2177	0	0
auto_block_out_ctl_rd_A	1353810099	3138	0	0
com_det_ctl_0_rd_A	1353810099	4714	0	0
com_det_ctl_1_rd_A	1353810099	4706	0	0
com_det_ctl_2_rd_A	1353810099	4794	0	0
com_det_ctl_3_rd_A	1353810099	4539	0	0
com_out_ctl_0_rd_A	1353810099	5483	0	0
com_out_ctl_1_rd_A	1353810099	5399	0	0
com_out_ctl_2_rd_A	1353810099	5500	0	0
com_out_ctl_3_rd_A	1353810099	5452	0	0
com_pre_det_ctl_0_rd_A	1353810099	1625	0	0
com_pre_det_ctl_1_rd_A	1353810099	1659	0	0
com_pre_det_ctl_2_rd_A	1353810099	1564	0	0
com_pre_det_ctl_3_rd_A	1353810099	1836	0	0
com_pre_sel_ctl_0_rd_A	1353810099	5681	0	0
com_pre_sel_ctl_1_rd_A	1353810099	5465	0	0
com_pre_sel_ctl_2_rd_A	1353810099	5515	0	0
com_pre_sel_ctl_3_rd_A	1353810099	5508	0	0
com_sel_ctl_0_rd_A	1353810099	5603	0	0
com_sel_ctl_1_rd_A	1353810099	5772	0	0
com_sel_ctl_2_rd_A	1353810099	5525	0	0
com_sel_ctl_3_rd_A	1353810099	5627	0	0
ec_rst_ctl_rd_A	1353810099	2875	0	0
intr_enable_rd_A	1353810099	2203	0	0
key_intr_ctl_rd_A	1353810099	4550	0	0
key_intr_debounce_ctl_rd_A	1353810099	1735	0	0
key_invert_ctl_rd_A	1353810099	6500	0	0
pin_allowed_ctl_rd_A	1353810099	7023	0	0
pin_out_ctl_rd_A	1353810099	4710	0	0
pin_out_value_rd_A	1353810099	4861	0	0
regwen_rd_A	1353810099	1719	0	0
ulp_ac_debounce_ctl_rd_A	1353810099	1861	0	0
ulp_ctl_rd_A	1353810099	1780	0	0
ulp_lid_debounce_ctl_rd_A	1353810099	1832	0	0
ulp_pwrb_debounce_ctl_rd_A	1353810099	1888	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	11430	0	0
T2	113646	9	0	0
T3	533177	18	0	0
T6	118546	3	0	0
T12	0	19	0	0
T16	253613	5	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	8	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	12	0	0
T57	0	1	0	0
T59	118921	0	0	0
T65	0	14	0	0
T113	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	2177	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	21	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	72	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	18	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	18	0	0
T90	0	11	0	0
T239	0	5	0	0
T265	0	12	0	0
T266	0	15	0	0
T267	0	2	0	0
T268	0	16	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	3138	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	23	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	40	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	20	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	21	0	0
T90	0	7	0	0
T113	0	18	0	0
T239	0	10	0	0
T265	0	20	0	0
T266	0	15	0	0
T268	0	19	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4714	0	0
T6	118546	0	0	0
T7	116463	12	0	0
T16	253613	35	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	30	0	0
T30	0	51	0	0
T31	0	116	0	0
T32	0	59	0	0
T38	0	44	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	4	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	16	0	0
T224	0	43	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4706	0	0
T6	118546	0	0	0
T7	116463	21	0	0
T16	253613	11	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	42	0	0
T30	0	50	0	0
T31	0	174	0	0
T32	0	42	0	0
T38	0	50	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	7	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	20	0	0
T224	0	43	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4794	0	0
T6	118546	0	0	0
T7	116463	26	0	0
T16	253613	19	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	53	0	0
T30	0	49	0	0
T31	0	124	0	0
T32	0	45	0	0
T38	0	63	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	12	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	5	0	0
T224	0	47	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4539	0	0
T6	118546	0	0	0
T7	116463	14	0	0
T16	253613	16	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	42	0	0
T30	0	55	0	0
T31	0	147	0	0
T32	0	25	0	0
T38	0	48	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	13	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	9	0	0
T224	0	53	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5483	0	0
T6	118546	0	0	0
T7	116463	14	0	0
T16	253613	16	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	44	0	0
T30	0	52	0	0
T31	0	141	0	0
T32	0	59	0	0
T38	0	41	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	12	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	1	0	0
T224	0	47	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5399	0	0
T6	118546	0	0	0
T7	116463	24	0	0
T16	253613	9	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	24	0	0
T30	0	45	0	0
T31	0	135	0	0
T32	0	29	0	0
T38	0	34	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	11	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	8	0	0
T224	0	37	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5500	0	0
T6	118546	0	0	0
T7	116463	43	0	0
T16	253613	12	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	39	0	0
T30	0	49	0	0
T31	0	128	0	0
T32	0	43	0	0
T38	0	54	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	16	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	10	0	0
T224	0	48	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5452	0	0
T6	118546	0	0	0
T7	116463	30	0	0
T16	253613	23	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	40	0	0
T30	0	66	0	0
T31	0	131	0	0
T32	0	38	0	0
T38	0	47	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	14	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	14	0	0
T224	0	25	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1625	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	11	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	14	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	9	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	10	0	0
T113	0	20	0	0
T127	0	26	0	0
T133	0	15	0	0
T268	0	20	0	0
T269	0	13	0	0
T270	0	16	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1659	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	12	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	16	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	11	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	9	0	0
T113	0	12	0	0
T127	0	38	0	0
T133	0	2	0	0
T268	0	12	0	0
T269	0	11	0	0
T270	0	17	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1564	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	10	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	31	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	10	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	10	0	0
T127	0	23	0	0
T133	0	14	0	0
T165	0	4	0	0
T268	0	16	0	0
T269	0	11	0	0
T270	0	27	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1836	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	18	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	35	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	11	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	14	0	0
T113	0	5	0	0
T127	0	24	0	0
T133	0	15	0	0
T268	0	26	0	0
T269	0	19	0	0
T270	0	27	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5681	0	0
T6	118546	0	0	0
T7	116463	24	0	0
T16	253613	29	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	39	0	0
T30	0	40	0	0
T31	0	131	0	0
T32	0	55	0	0
T38	0	61	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	6	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	10	0	0
T224	0	63	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5465	0	0
T6	118546	0	0	0
T7	116463	11	0	0
T16	253613	18	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	37	0	0
T30	0	45	0	0
T31	0	135	0	0
T32	0	55	0	0
T38	0	52	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	3	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	4	0	0
T224	0	39	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5515	0	0
T6	118546	0	0	0
T7	116463	17	0	0
T16	253613	9	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	38	0	0
T30	0	46	0	0
T31	0	126	0	0
T32	0	27	0	0
T38	0	40	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	13	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	11	0	0
T224	0	41	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5508	0	0
T6	118546	0	0	0
T7	116463	26	0	0
T16	253613	11	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	57	0	0
T30	0	55	0	0
T31	0	139	0	0
T32	0	45	0	0
T38	0	27	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	4	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	14	0	0
T224	0	50	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5603	0	0
T6	118546	0	0	0
T7	116463	26	0	0
T16	253613	28	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	42	0	0
T30	0	50	0	0
T31	0	110	0	0
T32	0	47	0	0
T38	0	42	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	12	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	11	0	0
T224	0	46	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5772	0	0
T6	118546	0	0	0
T7	116463	32	0	0
T16	253613	13	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	53	0	0
T30	0	49	0	0
T31	0	156	0	0
T32	0	47	0	0
T38	0	45	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	10	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	16	0	0
T224	0	45	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5525	0	0
T6	118546	0	0	0
T7	116463	28	0	0
T16	253613	30	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	70	0	0
T30	0	46	0	0
T31	0	128	0	0
T32	0	45	0	0
T38	0	61	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	10	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	1	0	0
T224	0	48	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	5627	0	0
T6	118546	0	0	0
T7	116463	11	0	0
T16	253613	12	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	43	0	0
T30	0	34	0	0
T31	0	141	0	0
T32	0	53	0	0
T38	0	34	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	5	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T163	0	63	0	0
T224	0	8	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	2875	0	0
T6	118546	0	0	0
T7	116463	5	0	0
T16	253613	26	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T23	0	9	0	0
T30	0	9	0	0
T31	0	66	0	0
T32	0	2	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T46	0	6	0	0
T48	0	3	0	0
T57	0	17	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T113	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	2203	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	22	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	39	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	19	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	16	0	0
T113	0	12	0	0
T127	0	72	0	0
T133	0	33	0	0
T268	0	12	0	0
T271	0	9	0	0
T272	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4550	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	29	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T34	0	3	0	0
T38	0	44	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	8	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	15	0	0
T108	0	8	0	0
T113	0	7	0	0
T142	0	7	0	0
T172	0	4	0	0
T268	0	18	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1735	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	24	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	13	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	17	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	6	0	0
T113	0	1	0	0
T127	0	18	0	0
T133	0	18	0	0
T268	0	15	0	0
T269	0	5	0	0
T270	0	15	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	6500	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	10	0	0
T17	670309	33	0	0
T18	335826	0	0	0
T31	0	60	0	0
T38	0	82	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	70	0	0
T59	118921	65	0	0
T60	0	73	0	0
T74	56873	0	0	0
T113	0	54	0	0
T158	0	51	0	0
T273	0	69	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	7023	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	167	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	227	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	84	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	190	0	0
T113	0	4	0	0
T274	0	29	0	0
T275	0	89	0	0
T276	0	91	0	0
T277	0	76	0	0
T278	0	67	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4710	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	164	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	238	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	80	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	153	0	0
T113	0	1	0	0
T274	0	41	0	0
T275	0	53	0	0
T276	0	58	0	0
T277	0	90	0	0
T278	0	95	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	4861	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	169	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	211	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	87	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	184	0	0
T113	0	2	0	0
T274	0	50	0	0
T275	0	82	0	0
T276	0	67	0	0
T277	0	67	0	0
T278	0	68	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1719	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	17	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	21	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	10	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	15	0	0
T113	0	23	0	0
T127	0	26	0	0
T133	0	2	0	0
T268	0	12	0	0
T269	0	6	0	0
T270	0	19	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1861	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	24	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	29	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	14	0	0
T58	0	9	0	0
T59	118921	0	0	0
T71	0	8	0	0
T74	56873	0	0	0
T78	0	20	0	0
T113	0	18	0	0
T163	0	5	0	0
T239	0	6	0	0
T279	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1780	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	20	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	40	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	13	0	0
T59	118921	0	0	0
T71	0	4	0	0
T74	56873	0	0	0
T78	0	28	0	0
T117	0	4	0	0
T163	0	5	0	0
T268	0	14	0	0
T279	0	8	0	0
T280	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1832	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	16	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	36	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	4	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	11	0	0
T113	0	22	0	0
T117	0	7	0	0
T163	0	3	0	0
T239	0	1	0	0
T279	0	9	0	0
T281	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1353810099	1888	0	0
T6	118546	0	0	0
T7	116463	0	0	0
T16	253613	21	0	0
T17	670309	0	0	0
T18	335826	0	0	0
T38	0	27	0	0
T42	347052	0	0	0
T43	309754	0	0	0
T44	639610	0	0	0
T57	0	22	0	0
T58	0	2	0	0
T59	118921	0	0	0
T74	56873	0	0	0
T78	0	9	0	0
T113	0	15	0	0
T117	0	7	0	0
T163	0	9	0	0
T239	0	1	0	0
T280	0	5	0	0