Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	1	30	96.77	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872

1

T2

40

T13

8

T6

4

auto[1]

519

1

T2

4

T6

3

T21

13

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1824

1

T2

38

T13

8

T6

6

auto[1]

567

1

T2

6

T6

1

T21

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T2

39

T13

5

T6

1

auto[1]

597

1

T2

5

T13

3

T6

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1798

1

T2

39

T13

6

T6

1

auto[1]

593

1

T2

5

T13

2

T6

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2163

1

T2

44

T13

6

T6

7

auto[1]

228

1

T13

2

T21

7

T41

19

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2184

1

T2

39

T13

5

T6

7

auto[1]

207

1

T2

5

T13

3

T21

10

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2201

1

T2

38

T13

8

T6

7

auto[1]

190

1

T2

6

T21

6

T41

16

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2208

1

T2

44

T13

7

T6

7

auto[1]

183

1

T13

1

T21

9

T25

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125

1

T2

40

T13

8

T6

7

auto[1]

266

1

T2

4

T41

8

T201

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1799

1

T2

38

T13

7

T21

23

auto[1]

592

1

T2

6

T13

1

T6

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	771	1			T6	5		T8	11		T10	20
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	62	1			T21	6		T41	19		T336	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	90	1			T2	4		T238	8		T337	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	21	1			T323	12		T338	6		T339	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	34	1			T25	2		T166	2		T239	12
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	28	1			T239	6		T323	10		T340	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	25	1			T239	7		T341	6		T130	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T201	2		T342	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	50	1			T2	6		T41	16		T340	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T323	11		T130	3		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	28	1			T238	4		T336	3		T343	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	13	1			T323	8		T344	3		T322	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	16	1			T21	4		T239	5		T345	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T339	1		T331	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T334	2		T346	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	80	1			T2	5		T21	7		T201	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T322	9		T345	1		T347	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	22	1			T41	8		T201	3		T348	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T329	1		T349	1		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	16	1			T21	3		T166	1		T85	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	17	1			T322	7		T332	10		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T341	6		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	8	1			T166	1		T335	2		T350	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T351	5		T352	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T353	3		T342	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T354	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	1	30	96.77	1
Automatically Generated Cross Bins	31	1	30	96.77	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

79

1

T2

4

T201

3

T216

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T21

6

T8

7

T320

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

59

1

T41

16

T26

4

T28

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

91

1

T320

7

T238

12

T323

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

64

1

T10

8

T41

8

T203

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

65

1

T41

19

T27

8

T30

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T26

2

T82

3

T106

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

90

1

T66

1

T69

3

T341

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T28

4

T166

1

T167

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T21

3

T10

6

T26

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T21

7

T28

1

T167

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T2

5

T30

2

T337

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T27

5

T201

4

T321

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T6

4

T174

3

T355

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T81

1

T321

1

T241

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

119

1

T66

1

T201

2

T319

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T21

4

T30

1

T166

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T2

6

T25

2

T38

14

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T6

1

T10

3

T239

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T8

4

T167

5

T81

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T10

3

T26

2

T356

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T174

6

T252

4

T89

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T81

1

T319

3

T68

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T38

8

T320

10

T355

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T319

1

T239

7

T357

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T68

2

T336

1

T241

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T241

1

T318

1

T327

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T28

2

T68

3

T340

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T38

2

T199

1

T337

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T253

1

T358

1

T359

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded