Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T5

22

T54

9

T20

21

auto[1]

1043

1

T5

18

T54

11

T20

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

509

1

T5

9

T54

5

T20

8

from_0to1

499

1

T5

9

T54

5

T20

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T5

24

T54

14

T20

24

auto[1]

1084

1

T5

16

T54

6

T20

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T5

19

T54

11

T20

18

auto[1]

1039

1

T5

21

T54

9

T20

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T5

3

T54

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T54

1

T20

2

T56

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T5

3

T56

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T5

1

T54

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T56

1

T57

1

T376

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T5

1

T54

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T5

3

T54

1

T20

2

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T5

1

T20

3

T36

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T20

2

T57

2

T287

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T5

1

T56

2

T30

2

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T5

1

T54

2

T20

2

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T20

1

T56

2

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T5

2

T54

2

T56

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T5

1

T20

2

T56

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T56

1

T36

1

T287

2

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T5

1

T54

1

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T5

19

T54

12

T20

21

auto[1]

1006

1

T5

21

T54

8

T20

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T5

8

T54

3

T20

13

from_0to1

499

1

T5

9

T54

4

T20

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T5

25

T54

5

T20

23

auto[1]

1073

1

T5

15

T54

15

T20

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T5

20

T54

8

T20

17

auto[1]

1049

1

T5

20

T54

12

T20

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T5

3

T20

1

T56

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T5

3

T20

2

T56

2

auto[0]

from_1to0

auto[1]

auto[0]

81

1

T5

1

T20

1

T57

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T54

1

T20

2

T287

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T5

2

T20

2

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T20

2

T57

2

T287

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T5

2

T54

1

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T54

2

T20

1

T56

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T57

1

T36

2

T376

2

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T5

1

T54

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T54

1

T20

3

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T20

3

T57

2

T36

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T5

1

T54

1

T287

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T5

1

T20

3

T102

2

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T5

1

T20

4

T57

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T5

2

T57

1

T36

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T5

21

T54

7

T20

23

auto[1]

1089

1

T5

19

T54

13

T20

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T5

10

T54

4

T20

9

from_0to1

478

1

T5

9

T54

4

T20

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T5

27

T54

14

T20

16

auto[1]

1052

1

T5

13

T54

6

T20

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T5

19

T54

11

T20

16

auto[1]

1083

1

T5

21

T54

9

T20

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T5

3

T54

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T20

1

T287

2

T376

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T5

1

T20

1

T56

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T5

1

T20

2

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T54

1

T20

1

T36

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T54

1

T20

3

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T5

1

T20

3

T56

2

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T5

1

T20

1

T56

2

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T5

2

T376

2

T30

3

auto[1]

from_1to0

auto[0]

auto[1]

84

1

T5

1

T54

3

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T20

1

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T5

1

T20

4

T56

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T5

1

T54

1

T30

3

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T5

3

T20

1

T36

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T5

1

T36

2

T287

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T5

2

T54

1

T20

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T5

20

T54

7

T20

21

auto[1]

1036

1

T5

20

T54

13

T20

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

513

1

T5

13

T54

7

T20

11

from_0to1

503

1

T5

12

T54

6

T20

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T5

20

T54

10

T20

26

auto[1]

1080

1

T5

20

T54

10

T20

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T5

21

T54

7

T20

16

auto[1]

1024

1

T5

19

T54

13

T20

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T5

1

T54

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T5

1

T54

1

T20

7

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T5

4

T20

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T5

1

T54

1

T376

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T5

1

T20

1

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T54

1

T57

1

T287

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T5

2

T54

1

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T5

2

T20

1

T30

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T5

4

T20

1

T56

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T5

1

T54

2

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T54

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T54

1

T20

1

T56

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T20

2

T56

2

T36

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T5

4

T54

2

T20

3

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T5

1

T54

1

T20

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T5

2

T54

1

T20

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T5

18

T54

9

T20

20

auto[1]

1057

1

T5

22

T54

11

T20

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

494

1

T5

8

T54

7

T20

9

from_0to1

491

1

T5

7

T54

6

T20

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T5

19

T54

12

T20

14

auto[1]

1056

1

T5

21

T54

8

T20

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T5

26

T54

11

T20

22

auto[1]

1091

1

T5

14

T54

9

T20

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T20

1

T56

1

T36

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T5

1

T54

1

T287

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T5

2

T54

2

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T5

1

T54

1

T20

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T5

1

T54

3

T20

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T54

1

T20

1

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T5

2

T20

2

T56

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T20

1

T57

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T5

2

T54

1

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T5

2

T54

1

T20

2

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T20

2

T36

1

T376

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T54

1

T57

1

T287

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T54

2

T20

1

T287

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T5

1

T20

1

T287

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T5

1

T20

2

T56

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T5

1

T20

1

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T5

21

T54

11

T20

17

auto[1]

1042

1

T5

19

T54

9

T20

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T5

12

T54

6

T20

11

from_0to1

517

1

T5

11

T54

7

T20

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T5

27

T54

9

T20

22

auto[1]

1044

1

T5

13

T54

11

T20

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1046

1

T5

22

T54

7

T20

21

auto[1]

1064

1

T5

18

T54

13

T20

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

1

T54

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T5

3

T54

1

T20

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T5

2

T20

3

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T5

1

T54

3

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T5

1

T20

2

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T5

1

T54

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T5

1

T57

1

T376

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T5

2

T54

2

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T5

3

T20

2

T56

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T5

1

T287

2

T30

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T20

1

T287

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T54

1

T20

3

T56

3

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T5

3

T54

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T5

2

T54

2

T20

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T5

1

T54

1

T20

3

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T20

1

T56

1

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T5

24

T54

8

T20

18

auto[1]

1043

1

T5

16

T54

12

T20

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T5

9

T54

5

T20

11

from_0to1

512

1

T5

9

T54

5

T20

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T5

17

T54

11

T20

23

auto[1]

1043

1

T5

23

T54

9

T20

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T5

21

T54

14

T20

23

auto[1]

1110

1

T5

19

T54

6

T20

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T5

1

T56

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T20

1

T56

1

T36

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T5

2

T54

2

T20

3

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T5

1

T20

1

T36

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T5

3

T54

2

T376

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T5

1

T54

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T5

1

T56

1

T36

2

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T5

1

T20

2

T56

4

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T5

1

T54

2

T20

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T5

1

T20

1

T56

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T5

3

T54

1

T20

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T20

1

T56

1

T376

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T5

1

T20

2

T36

2

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T5

1

T54

1

T20

2

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T20

3

T287

1

T30

2

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T54

1

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T5

19

T54

13

T20

21

auto[1]

1060

1

T5

21

T54

7

T20

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T5

10

T54

4

T20

9

from_0to1

499

1

T5

9

T54

3

T20

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T5

25

T54

11

T20

20

auto[1]

1060

1

T5

15

T54

9

T20

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T5

21

T54

10

T20

16

auto[1]

1051

1

T5

19

T54

10

T20

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T5

1

T20

1

T56

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T5

3

T20

3

T56

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T5

2

T54

3

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T5

1

T20

1

T56

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T5

2

T54

1

T20

2

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T5

1

T54

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T5

1

T56

1

T30

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T20

1

T36

1

T376

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T57

1

T30

3

T377

4

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T5

1

T20

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T5

2

T54

1

T20

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T20

1

T56

2

T287

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T5

1

T20

1

T56

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T5

3

T54

1

T20

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T20

1

T36

1

T287

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T5

1

T20

2

T56

1