Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 152671 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 118772 1 T1 387 T2 558 T4 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 140039 1 T1 546 T2 461 T4 8
values[0x0] 65360 1 T1 164 T2 472 T4 4
values[0x1] 66044 1 T1 149 T2 446 T4 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 123741 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 147702 1 T1 469 T2 672 T4 11



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 949 1 T2 6 T5 1 T15 1
valid_sources[0x01] 819 1 T1 16 T2 2 T8 3
valid_sources[0x02] 1266 1 T1 6 T2 4 T5 7
valid_sources[0x03] 1136 1 T2 9 T8 3 T20 2
valid_sources[0x04] 1052 1 T2 9 T5 3 T8 2
valid_sources[0x05] 1175 1 T2 6 T8 3 T25 7
valid_sources[0x06] 1279 1 T2 2 T25 8 T251 1
valid_sources[0x07] 977 1 T2 4 T5 2 T20 1
valid_sources[0x08] 1029 1 T1 2 T2 3 T8 5
valid_sources[0x09] 1013 1 T2 9 T8 4 T20 2
valid_sources[0x0a] 850 1 T2 8 T5 2 T8 1
valid_sources[0x0b] 809 1 T1 2 T2 7 T12 1
valid_sources[0x0c] 1876 1 T1 7 T2 4 T5 2
valid_sources[0x0d] 1094 1 T1 2 T2 5 T4 3
valid_sources[0x0e] 1111 1 T1 3 T2 2 T7 1
valid_sources[0x0f] 1050 1 T2 3 T25 4 T143 1
valid_sources[0x10] 814 1 T2 5 T12 2 T5 2
valid_sources[0x11] 846 1 T2 4 T14 3 T46 1
valid_sources[0x12] 907 1 T2 6 T5 10 T8 1
valid_sources[0x13] 882 1 T2 4 T9 1 T60 1
valid_sources[0x14] 855 1 T2 6 T8 13 T20 1
valid_sources[0x15] 991 1 T1 4 T2 9 T5 11
valid_sources[0x16] 864 1 T2 7 T8 1 T20 1
valid_sources[0x17] 747 1 T2 3 T5 4 T46 1
valid_sources[0x18] 747 1 T1 1 T2 3 T15 1
valid_sources[0x19] 1248 1 T2 3 T5 2 T8 5
valid_sources[0x1a] 942 1 T2 2 T5 5 T46 1
valid_sources[0x1b] 1102 1 T1 5 T2 5 T5 1
valid_sources[0x1c] 938 1 T2 5 T8 1 T57 3
valid_sources[0x1d] 873 1 T2 6 T5 1 T8 3
valid_sources[0x1e] 1025 1 T2 6 T8 5 T20 1
valid_sources[0x1f] 997 1 T1 4 T2 7 T14 1
valid_sources[0x20] 973 1 T2 3 T5 2 T8 3
valid_sources[0x21] 882 1 T1 18 T2 2 T8 7
valid_sources[0x22] 1084 1 T1 5 T2 4 T5 5
valid_sources[0x23] 1202 1 T2 6 T5 9 T15 1
valid_sources[0x24] 907 1 T1 10 T2 6 T5 2
valid_sources[0x25] 775 1 T2 5 T8 4 T25 1
valid_sources[0x26] 1019 1 T2 6 T8 1 T20 1
valid_sources[0x27] 1187 1 T2 12 T8 9 T20 3
valid_sources[0x28] 796 1 T2 7 T15 1 T9 2
valid_sources[0x29] 875 1 T1 27 T2 4 T7 1
valid_sources[0x2a] 1290 1 T2 4 T5 9 T20 5
valid_sources[0x2b] 1166 1 T2 3 T8 1 T20 2
valid_sources[0x2c] 1019 1 T1 8 T2 4 T20 1
valid_sources[0x2d] 759 1 T2 7 T14 4 T8 3
valid_sources[0x2e] 1159 1 T1 7 T2 7 T5 25
valid_sources[0x2f] 1022 1 T2 4 T8 2 T20 1
valid_sources[0x30] 785 1 T2 11 T8 1 T25 3
valid_sources[0x31] 859 1 T2 1 T8 4 T20 2
valid_sources[0x32] 1065 1 T2 4 T12 1 T8 4
valid_sources[0x33] 834 1 T1 7 T2 5 T8 1
valid_sources[0x34] 885 1 T2 7 T8 2 T9 1
valid_sources[0x35] 831 1 T2 4 T8 3 T58 1
valid_sources[0x36] 1222 1 T2 13 T12 1 T5 1
valid_sources[0x37] 1166 1 T1 9 T2 4 T12 2
valid_sources[0x38] 842 1 T1 7 T2 4 T3 6
valid_sources[0x39] 1062 1 T2 5 T4 6 T5 1
valid_sources[0x3a] 781 1 T1 6 T2 6 T15 1
valid_sources[0x3b] 809 1 T1 6 T2 3 T8 7
valid_sources[0x3c] 772 1 T2 9 T5 3 T14 1
valid_sources[0x3d] 1091 1 T1 5 T2 2 T5 15
valid_sources[0x3e] 1016 1 T1 2 T2 5 T14 1
valid_sources[0x3f] 789 1 T1 9 T2 6 T15 1
valid_sources[0x40] 977 1 T1 4 T2 5 T8 8
valid_sources[0x41] 954 1 T1 18 T2 8 T5 2
valid_sources[0x42] 948 1 T2 4 T3 4 T12 1
valid_sources[0x43] 809 1 T1 1 T2 4 T8 3
valid_sources[0x44] 1335 1 T1 5 T2 5 T8 1
valid_sources[0x45] 917 1 T1 4 T2 5 T15 1
valid_sources[0x46] 1094 1 T1 5 T2 6 T15 1
valid_sources[0x47] 991 1 T2 2 T5 2 T14 1
valid_sources[0x48] 1080 1 T1 1 T2 4 T5 7
valid_sources[0x49] 1025 1 T1 13 T2 9 T5 1
valid_sources[0x4a] 1058 1 T2 7 T5 1 T20 1
valid_sources[0x4b] 1095 1 T1 9 T2 5 T3 7
valid_sources[0x4c] 844 1 T2 4 T15 1 T8 13
valid_sources[0x4d] 838 1 T1 8 T2 5 T15 1
valid_sources[0x4e] 1409 1 T2 11 T12 2 T5 2
valid_sources[0x4f] 856 1 T1 1 T2 3 T55 2
valid_sources[0x50] 1096 1 T1 2 T2 2 T5 1
valid_sources[0x51] 1298 1 T2 4 T20 1 T47 1
valid_sources[0x52] 1431 1 T1 10 T2 2 T5 3
valid_sources[0x53] 1042 1 T2 5 T8 3 T47 1
valid_sources[0x54] 1720 1 T1 3 T2 3 T12 1
valid_sources[0x55] 1855 1 T2 2 T8 1 T20 1
valid_sources[0x56] 1030 1 T1 5 T2 5 T3 6
valid_sources[0x57] 1266 1 T2 2 T8 4 T20 1
valid_sources[0x58] 928 1 T1 5 T2 4 T5 5
valid_sources[0x59] 1830 1 T2 5 T8 2 T25 4
valid_sources[0x5a] 823 1 T2 14 T5 3 T14 1
valid_sources[0x5b] 845 1 T2 2 T20 2 T25 4
valid_sources[0x5c] 1019 1 T1 4 T2 1 T20 2
valid_sources[0x5d] 912 1 T1 11 T2 1 T20 3
valid_sources[0x5e] 1062 1 T2 10 T11 28 T58 1
valid_sources[0x5f] 808 1 T2 6 T58 1 T25 2
valid_sources[0x60] 1501 1 T1 4 T2 4 T5 13
valid_sources[0x61] 858 1 T2 3 T8 1 T20 2
valid_sources[0x62] 734 1 T1 3 T2 6 T7 2
valid_sources[0x63] 1175 1 T1 24 T2 6 T7 1
valid_sources[0x64] 1240 1 T1 31 T2 7 T14 2
valid_sources[0x65] 1206 1 T1 4 T2 7 T5 2
valid_sources[0x66] 1013 1 T1 2 T2 8 T5 6
valid_sources[0x67] 897 1 T1 5 T2 7 T5 6
valid_sources[0x68] 935 1 T1 2 T2 5 T5 1
valid_sources[0x69] 1126 1 T1 7 T2 4 T5 3
valid_sources[0x6a] 1017 1 T2 5 T5 14 T15 1
valid_sources[0x6b] 931 1 T1 5 T2 3 T8 1
valid_sources[0x6c] 1156 1 T1 20 T2 4 T15 1
valid_sources[0x6d] 870 1 T2 10 T14 3 T15 1
valid_sources[0x6e] 1495 1 T2 5 T7 1 T8 3
valid_sources[0x6f] 959 1 T2 3 T7 1 T8 4
valid_sources[0x70] 1738 1 T1 3 T2 7 T5 6
valid_sources[0x71] 1033 1 T1 13 T2 7 T12 2
valid_sources[0x72] 1093 1 T2 4 T5 1 T8 6
valid_sources[0x73] 1293 1 T2 10 T5 1 T8 1
valid_sources[0x74] 1002 1 T2 1 T8 8 T57 1
valid_sources[0x75] 1041 1 T2 2 T15 1 T8 1
valid_sources[0x76] 1576 1 T2 5 T5 14 T15 1
valid_sources[0x77] 722 1 T1 4 T2 7 T7 1
valid_sources[0x78] 1019 1 T2 7 T8 5 T20 1
valid_sources[0x79] 1001 1 T1 3 T2 6 T55 1
valid_sources[0x7a] 991 1 T2 5 T5 5 T58 1
valid_sources[0x7b] 1232 1 T1 5 T2 5 T5 20
valid_sources[0x7c] 2052 1 T2 3 T12 1 T5 11
valid_sources[0x7d] 1240 1 T1 5 T2 5 T15 2
valid_sources[0x7e] 861 1 T2 3 T14 2 T8 3
valid_sources[0x7f] 913 1 T2 5 T5 2 T15 1
valid_sources[0x80] 2222 1 T2 2 T5 5 T14 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 63933 1 T1 280 T2 241 T4 5
values[0x0] all_enables biggest_size 31982 1 T1 68 T2 199 T4 2
values[0x1] all_enables biggest_size 22857 1 T1 39 T2 118 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%