Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1292548164	11411	0	0
auto_block_debounce_ctl_rd_A	1292548164	1716	0	0
auto_block_out_ctl_rd_A	1292548164	2297	0	0
com_det_ctl_0_rd_A	1292548164	2948	0	0
com_det_ctl_1_rd_A	1292548164	3167	0	0
com_det_ctl_2_rd_A	1292548164	3069	0	0
com_det_ctl_3_rd_A	1292548164	3043	0	0
com_out_ctl_0_rd_A	1292548164	3600	0	0
com_out_ctl_1_rd_A	1292548164	3759	0	0
com_out_ctl_2_rd_A	1292548164	3818	0	0
com_out_ctl_3_rd_A	1292548164	3538	0	0
com_pre_det_ctl_0_rd_A	1292548164	1271	0	0
com_pre_det_ctl_1_rd_A	1292548164	1286	0	0
com_pre_det_ctl_2_rd_A	1292548164	1256	0	0
com_pre_det_ctl_3_rd_A	1292548164	1326	0	0
com_pre_sel_ctl_0_rd_A	1292548164	3801	0	0
com_pre_sel_ctl_1_rd_A	1292548164	3712	0	0
com_pre_sel_ctl_2_rd_A	1292548164	3896	0	0
com_pre_sel_ctl_3_rd_A	1292548164	3842	0	0
com_sel_ctl_0_rd_A	1292548164	3879	0	0
com_sel_ctl_1_rd_A	1292548164	3984	0	0
com_sel_ctl_2_rd_A	1292548164	3886	0	0
com_sel_ctl_3_rd_A	1292548164	3966	0	0
ec_rst_ctl_rd_A	1292548164	2036	0	0
intr_enable_rd_A	1292548164	1759	0	0
key_intr_ctl_rd_A	1292548164	3440	0	0
key_intr_debounce_ctl_rd_A	1292548164	1295	0	0
key_invert_ctl_rd_A	1292548164	5708	0	0
pin_allowed_ctl_rd_A	1292548164	5063	0	0
pin_out_ctl_rd_A	1292548164	3319	0	0
pin_out_value_rd_A	1292548164	3751	0	0
regwen_rd_A	1292548164	1354	0	0
ulp_ac_debounce_ctl_rd_A	1292548164	1402	0	0
ulp_ctl_rd_A	1292548164	1461	0	0
ulp_lid_debounce_ctl_rd_A	1292548164	1548	0	0
ulp_pwrb_debounce_ctl_rd_A	1292548164	1414	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	11411	0	0
T1	506685	8	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	12	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	5	0	0
T30	0	9	0	0
T31	0	1	0	0
T32	0	8	0	0
T66	0	20	0	0
T76	0	3	0	0
T102	0	12	0	0
T216	0	23	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1716	0	0
T1	506685	46	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	4	0	0
T31	0	8	0	0
T40	0	9	0	0
T71	0	64	0	0
T78	0	4	0	0
T102	0	43	0	0
T134	0	10	0	0
T204	0	10	0	0
T277	0	11	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	2297	0	0
T1	506685	33	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	10	0	0
T31	0	9	0	0
T40	0	16	0	0
T71	0	63	0	0
T73	0	50	0	0
T102	0	32	0	0
T134	0	7	0	0
T204	0	5	0	0
T277	0	12	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	2948	0	0
T1	506685	9	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	38	0	0
T10	0	48	0	0
T12	657420	0	0	0
T13	330135	47	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	73	0	0
T28	0	93	0	0
T31	0	22	0	0
T81	0	72	0	0
T102	0	24	0	0
T203	0	63	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3167	0	0
T1	506685	29	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	75	0	0
T10	0	42	0	0
T12	657420	0	0	0
T13	330135	39	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	88	0	0
T28	0	77	0	0
T31	0	10	0	0
T81	0	65	0	0
T102	0	38	0	0
T203	0	40	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3069	0	0
T1	506685	19	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	80	0	0
T10	0	34	0	0
T12	657420	0	0	0
T13	330135	36	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	41	0	0
T28	0	122	0	0
T31	0	1	0	0
T81	0	100	0	0
T102	0	35	0	0
T203	0	25	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3043	0	0
T1	506685	24	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	76	0	0
T10	0	26	0	0
T12	657420	0	0	0
T13	330135	48	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	60	0	0
T28	0	90	0	0
T31	0	26	0	0
T81	0	68	0	0
T102	0	36	0	0
T203	0	49	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3600	0	0
T1	506685	35	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	69	0	0
T10	0	23	0	0
T12	657420	0	0	0
T13	330135	30	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	54	0	0
T28	0	109	0	0
T31	0	1	0	0
T81	0	78	0	0
T102	0	45	0	0
T203	0	44	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3759	0	0
T1	506685	21	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	72	0	0
T10	0	41	0	0
T12	657420	0	0	0
T13	330135	46	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	64	0	0
T28	0	80	0	0
T31	0	10	0	0
T81	0	84	0	0
T102	0	50	0	0
T203	0	41	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3818	0	0
T1	506685	18	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	87	0	0
T10	0	36	0	0
T12	657420	0	0	0
T13	330135	36	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	65	0	0
T28	0	105	0	0
T31	0	19	0	0
T81	0	51	0	0
T102	0	43	0	0
T203	0	58	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3538	0	0
T1	506685	7	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	48	0	0
T10	0	37	0	0
T12	657420	0	0	0
T13	330135	29	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	64	0	0
T28	0	85	0	0
T31	0	22	0	0
T81	0	87	0	0
T102	0	32	0	0
T203	0	27	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1271	0	0
T1	506685	11	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	4	0	0
T31	0	10	0	0
T71	0	36	0	0
T73	0	21	0	0
T102	0	34	0	0
T134	0	6	0	0
T179	0	29	0	0
T278	0	39	0	0
T279	0	8	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1286	0	0
T1	506685	16	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	10	0	0
T31	0	7	0	0
T71	0	56	0	0
T73	0	34	0	0
T102	0	43	0	0
T134	0	1	0	0
T179	0	12	0	0
T278	0	38	0	0
T279	0	18	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1256	0	0
T1	506685	14	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	15	0	0
T31	0	9	0	0
T71	0	41	0	0
T73	0	33	0	0
T102	0	48	0	0
T134	0	8	0	0
T179	0	23	0	0
T278	0	39	0	0
T279	0	23	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1326	0	0
T1	506685	36	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	4	0	0
T31	0	10	0	0
T71	0	50	0	0
T73	0	18	0	0
T102	0	55	0	0
T134	0	6	0	0
T179	0	16	0	0
T278	0	16	0	0
T279	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3801	0	0
T1	506685	8	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	69	0	0
T10	0	19	0	0
T12	657420	0	0	0
T13	330135	42	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	54	0	0
T28	0	67	0	0
T31	0	11	0	0
T81	0	62	0	0
T102	0	38	0	0
T203	0	33	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3712	0	0
T1	506685	3	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	55	0	0
T10	0	46	0	0
T12	657420	0	0	0
T13	330135	30	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	61	0	0
T28	0	85	0	0
T31	0	4	0	0
T81	0	81	0	0
T102	0	40	0	0
T203	0	27	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3896	0	0
T1	506685	11	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	64	0	0
T10	0	43	0	0
T12	657420	0	0	0
T13	330135	31	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	64	0	0
T28	0	74	0	0
T31	0	5	0	0
T81	0	82	0	0
T102	0	50	0	0
T203	0	39	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3842	0	0
T1	506685	14	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	77	0	0
T10	0	48	0	0
T12	657420	0	0	0
T13	330135	56	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	67	0	0
T28	0	68	0	0
T31	0	13	0	0
T81	0	55	0	0
T102	0	54	0	0
T203	0	33	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3879	0	0
T1	506685	16	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	64	0	0
T10	0	39	0	0
T12	657420	0	0	0
T13	330135	32	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	61	0	0
T28	0	24	0	0
T31	0	16	0	0
T81	0	67	0	0
T102	0	46	0	0
T203	0	24	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3984	0	0
T1	506685	21	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	64	0	0
T10	0	22	0	0
T12	657420	0	0	0
T13	330135	25	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	83	0	0
T28	0	70	0	0
T31	0	16	0	0
T81	0	70	0	0
T102	0	36	0	0
T203	0	68	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3886	0	0
T1	506685	14	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	76	0	0
T10	0	55	0	0
T12	657420	0	0	0
T13	330135	29	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	48	0	0
T28	0	93	0	0
T31	0	8	0	0
T81	0	72	0	0
T102	0	30	0	0
T203	0	28	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3966	0	0
T1	506685	31	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	74	0	0
T10	0	50	0	0
T12	657420	0	0	0
T13	330135	33	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	86	0	0
T28	0	113	0	0
T31	0	4	0	0
T81	0	74	0	0
T102	0	31	0	0
T203	0	41	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	2036	0	0
T1	506685	32	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	8	0	0
T10	0	24	0	0
T12	657420	1	0	0
T13	330135	2	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T21	0	15	0	0
T28	0	36	0	0
T46	0	3	0	0
T280	0	7	0	0
T281	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1759	0	0
T1	506685	25	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	4	0	0
T29	0	23	0	0
T31	0	11	0	0
T71	0	58	0	0
T73	0	54	0	0
T102	0	41	0	0
T134	0	52	0	0
T282	0	3	0	0
T283	0	14	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3440	0	0
T1	506685	22	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	12	0	0
T29	0	1	0	0
T31	0	13	0	0
T60	0	4	0	0
T71	0	33	0	0
T102	0	40	0	0
T149	0	6	0	0
T161	0	4	0	0
T165	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1295	0	0
T1	506685	17	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	1	0	0
T71	0	44	0	0
T73	0	31	0	0
T102	0	41	0	0
T134	0	6	0	0
T179	0	17	0	0
T278	0	19	0	0
T279	0	10	0	0
T284	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	5708	0	0
T1	506685	110	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	83	0	0
T28	0	58	0	0
T31	0	9	0	0
T71	0	103	0	0
T97	0	37	0	0
T102	0	44	0	0
T134	0	137	0	0
T285	0	86	0	0
T286	0	66	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	5063	0	0
T1	506685	23	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T31	0	63	0	0
T57	0	57	0	0
T71	0	32	0	0
T102	0	115	0	0
T113	0	32	0	0
T172	0	43	0	0
T287	0	29	0	0
T288	0	54	0	0
T289	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3319	0	0
T1	506685	21	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	2	0	0
T31	0	66	0	0
T57	0	72	0	0
T102	0	119	0	0
T113	0	37	0	0
T172	0	34	0	0
T287	0	34	0	0
T288	0	45	0	0
T289	0	64	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	3751	0	0
T1	506685	20	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	2	0	0
T31	0	29	0	0
T57	0	64	0	0
T102	0	137	0	0
T113	0	45	0	0
T172	0	44	0	0
T287	0	35	0	0
T288	0	39	0	0
T289	0	40	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1354	0	0
T1	506685	17	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	17	0	0
T31	0	6	0	0
T71	0	52	0	0
T73	0	41	0	0
T102	0	47	0	0
T134	0	4	0	0
T179	0	27	0	0
T278	0	38	0	0
T279	0	18	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1402	0	0
T1	506685	28	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	3	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	8	0	0
T31	0	18	0	0
T47	0	10	0	0
T48	0	9	0	0
T49	0	4	0	0
T65	0	10	0	0
T102	0	49	0	0
T173	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1461	0	0
T1	506685	32	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	4	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	13	0	0
T31	0	9	0	0
T47	0	4	0	0
T48	0	13	0	0
T49	0	12	0	0
T65	0	6	0	0
T102	0	55	0	0
T173	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1548	0	0
T1	506685	14	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	19	0	0
T31	0	7	0	0
T47	0	1	0	0
T48	0	11	0	0
T65	0	10	0	0
T102	0	45	0	0
T114	0	5	0	0
T173	0	3	0	0
T290	0	3	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292548164	1414	0	0
T1	506685	30	0	0
T2	279197	0	0	0
T3	63911	0	0	0
T4	88697	0	0	0
T5	250903	0	0	0
T6	468401	0	0	0
T12	657420	0	0	0
T13	330135	0	0	0
T14	52064	0	0	0
T15	29919	0	0	0
T28	0	12	0	0
T31	0	14	0	0
T47	0	4	0	0
T48	0	11	0	0
T49	0	7	0	0
T65	0	3	0	0
T102	0	31	0	0
T114	0	6	0	0
T173	0	10	0	0