Module Definition
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Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.91 96.00 93.02 82.61 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_wkup_status_cdc.u_arb 90.16 92.00 86.05 82.61 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
83.33 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
283 1 1
284 1 1
299 unreachable


Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
90.16 92.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL504692.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS1396583.33
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 0 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 0 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 0 1
211 0 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
83.33 66.67
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.16 86.05
tb.dut.u_reg.u_wkup_status_cdc.u_arb

TotalCoveredPercent
Conditions433786.05
Logical433786.05
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT16,T17,T18

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T3
10CoveredT16,T17,T18

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T17,T18
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T4
001Not Covered
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 19 82.61
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 3 75.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T4
0 1 - Covered T16,T17,T18
0 0 1 Covered T16,T17,T18
0 0 0 Covered T1,T2,T4


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T4
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T4


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T4
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T4


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 6722269 727 0 915
gen_wr_req.HwIdSelCheck_A 6722269 727 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6722269 727 0 915
T1 13100 3 0 1
T2 34899 8 0 1
T3 2173 2 0 1
T4 739 0 0 1
T5 5381 1 0 1
T6 9368 5 0 1
T7 0 1 0 0
T8 0 11 0 0
T9 0 1 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 1551 0 0 1
T13 6878 0 0 1
T14 495 0 0 1
T15 498 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6722269 727 0 0
T1 13100 3 0 0
T2 34899 8 0 0
T3 2173 2 0 0
T4 739 0 0 0
T5 5381 1 0 0
T6 9368 5 0 0
T7 0 1 0 0
T8 0 11 0 0
T9 0 1 0 0
T10 0 6 0 0
T11 0 1 0 0
T12 1551 0 0 0
T13 6878 0 0 0
T14 495 0 0 0
T15 498 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%