| T88 |
/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1349313845 |
|
|
Apr 30 12:37:41 PM PDT 24 |
Apr 30 12:38:21 PM PDT 24 |
82765998811 ps |
| T434 |
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2954085377 |
|
|
Apr 30 12:38:07 PM PDT 24 |
Apr 30 12:38:18 PM PDT 24 |
3694760143 ps |
| T435 |
/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.915456352 |
|
|
Apr 30 12:36:34 PM PDT 24 |
Apr 30 12:36:36 PM PDT 24 |
4156198148 ps |
| T436 |
/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.897120740 |
|
|
Apr 30 12:37:08 PM PDT 24 |
Apr 30 12:37:10 PM PDT 24 |
7379833472 ps |
| T437 |
/workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2531515919 |
|
|
Apr 30 12:37:35 PM PDT 24 |
Apr 30 12:37:42 PM PDT 24 |
5830814044 ps |
| T438 |
/workspace/coverage/default/12.sysrst_ctrl_pin_override_test.4208256888 |
|
|
Apr 30 12:36:34 PM PDT 24 |
Apr 30 12:36:42 PM PDT 24 |
2511397649 ps |
| T439 |
/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.191955462 |
|
|
Apr 30 12:37:56 PM PDT 24 |
Apr 30 12:37:59 PM PDT 24 |
2477149787 ps |
| T440 |
/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2389760028 |
|
|
Apr 30 12:36:43 PM PDT 24 |
Apr 30 12:36:52 PM PDT 24 |
2613135869 ps |
| T441 |
/workspace/coverage/default/28.sysrst_ctrl_stress_all.3262924101 |
|
|
Apr 30 12:37:25 PM PDT 24 |
Apr 30 12:37:28 PM PDT 24 |
11042216353 ps |
| T442 |
/workspace/coverage/default/30.sysrst_ctrl_alert_test.3598860680 |
|
|
Apr 30 12:37:29 PM PDT 24 |
Apr 30 12:37:33 PM PDT 24 |
2020630442 ps |
| T443 |
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2217500531 |
|
|
Apr 30 12:38:24 PM PDT 24 |
Apr 30 12:38:27 PM PDT 24 |
2536973040 ps |
| T444 |
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2642624100 |
|
|
Apr 30 12:36:29 PM PDT 24 |
Apr 30 12:36:38 PM PDT 24 |
6230213110 ps |
| T445 |
/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2528112440 |
|
|
Apr 30 12:36:19 PM PDT 24 |
Apr 30 12:36:28 PM PDT 24 |
2614358391 ps |
| T289 |
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3256764298 |
|
|
Apr 30 12:36:25 PM PDT 24 |
Apr 30 12:36:32 PM PDT 24 |
2515609358 ps |
| T446 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3359412006 |
|
|
Apr 30 12:36:16 PM PDT 24 |
Apr 30 12:36:19 PM PDT 24 |
2518994229 ps |
| T447 |
/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.460911708 |
|
|
Apr 30 12:37:15 PM PDT 24 |
Apr 30 12:37:20 PM PDT 24 |
2620892838 ps |
| T448 |
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.136361930 |
|
|
Apr 30 12:36:32 PM PDT 24 |
Apr 30 12:36:36 PM PDT 24 |
2520813771 ps |
| T89 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect.4248760787 |
|
|
Apr 30 12:37:15 PM PDT 24 |
Apr 30 12:38:21 PM PDT 24 |
25085146740 ps |
| T449 |
/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1059261139 |
|
|
Apr 30 12:37:24 PM PDT 24 |
Apr 30 12:37:34 PM PDT 24 |
3195906903 ps |
| T450 |
/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.85450396 |
|
|
Apr 30 12:36:17 PM PDT 24 |
Apr 30 12:36:25 PM PDT 24 |
2224920528 ps |
| T191 |
/workspace/coverage/default/17.sysrst_ctrl_edge_detect.2412925870 |
|
|
Apr 30 12:36:55 PM PDT 24 |
Apr 30 12:36:59 PM PDT 24 |
4089405779 ps |
| T341 |
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3786358938 |
|
|
Apr 30 12:38:31 PM PDT 24 |
Apr 30 12:40:26 PM PDT 24 |
79833075732 ps |
| T451 |
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1645217513 |
|
|
Apr 30 12:38:03 PM PDT 24 |
Apr 30 12:38:07 PM PDT 24 |
3139721319 ps |
| T452 |
/workspace/coverage/default/31.sysrst_ctrl_alert_test.2389226555 |
|
|
Apr 30 12:37:29 PM PDT 24 |
Apr 30 12:37:35 PM PDT 24 |
2010792780 ps |
| T453 |
/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2389056553 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:37:02 PM PDT 24 |
2471659064 ps |
| T454 |
/workspace/coverage/default/44.sysrst_ctrl_alert_test.4220096451 |
|
|
Apr 30 12:38:10 PM PDT 24 |
Apr 30 12:38:14 PM PDT 24 |
2021767299 ps |
| T455 |
/workspace/coverage/default/16.sysrst_ctrl_smoke.3344086193 |
|
|
Apr 30 12:36:52 PM PDT 24 |
Apr 30 12:36:54 PM PDT 24 |
2129998640 ps |
| T71 |
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.988616332 |
|
|
Apr 30 12:38:21 PM PDT 24 |
Apr 30 12:40:34 PM PDT 24 |
51737746460 ps |
| T126 |
/workspace/coverage/default/2.sysrst_ctrl_edge_detect.1754439557 |
|
|
Apr 30 12:36:20 PM PDT 24 |
Apr 30 12:36:30 PM PDT 24 |
3184844494 ps |
| T127 |
/workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3870511880 |
|
|
Apr 30 12:36:33 PM PDT 24 |
Apr 30 12:36:41 PM PDT 24 |
2843055101 ps |
| T128 |
/workspace/coverage/default/25.sysrst_ctrl_smoke.2627594161 |
|
|
Apr 30 12:37:15 PM PDT 24 |
Apr 30 12:37:21 PM PDT 24 |
2112657467 ps |
| T129 |
/workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2065324983 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:36:57 PM PDT 24 |
4382908689 ps |
| T130 |
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2564707164 |
|
|
Apr 30 12:38:42 PM PDT 24 |
Apr 30 12:40:47 PM PDT 24 |
88951735887 ps |
| T131 |
/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.833525502 |
|
|
Apr 30 12:38:05 PM PDT 24 |
Apr 30 12:38:09 PM PDT 24 |
2130049174 ps |
| T132 |
/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3868545316 |
|
|
Apr 30 12:37:41 PM PDT 24 |
Apr 30 12:37:43 PM PDT 24 |
2495150048 ps |
| T133 |
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1324119571 |
|
|
Apr 30 12:38:43 PM PDT 24 |
Apr 30 12:39:54 PM PDT 24 |
26583534008 ps |
| T134 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.993104853 |
|
|
Apr 30 12:37:02 PM PDT 24 |
Apr 30 12:37:37 PM PDT 24 |
629920570335 ps |
| T72 |
/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1047813791 |
|
|
Apr 30 12:37:31 PM PDT 24 |
Apr 30 12:37:34 PM PDT 24 |
3338950801 ps |
| T456 |
/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.588306615 |
|
|
Apr 30 12:37:24 PM PDT 24 |
Apr 30 12:37:30 PM PDT 24 |
2233829682 ps |
| T457 |
/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3478702551 |
|
|
Apr 30 12:36:42 PM PDT 24 |
Apr 30 12:36:45 PM PDT 24 |
2257387856 ps |
| T458 |
/workspace/coverage/default/29.sysrst_ctrl_edge_detect.1731533520 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:31 PM PDT 24 |
2391823207 ps |
| T459 |
/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.816691941 |
|
|
Apr 30 12:36:43 PM PDT 24 |
Apr 30 12:36:46 PM PDT 24 |
2234402189 ps |
| T353 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1942275452 |
|
|
Apr 30 12:36:10 PM PDT 24 |
Apr 30 12:36:39 PM PDT 24 |
64605080477 ps |
| T460 |
/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2784868940 |
|
|
Apr 30 12:37:01 PM PDT 24 |
Apr 30 12:37:03 PM PDT 24 |
2542678358 ps |
| T461 |
/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1254254865 |
|
|
Apr 30 12:37:56 PM PDT 24 |
Apr 30 12:37:59 PM PDT 24 |
2485628642 ps |
| T235 |
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1957441952 |
|
|
Apr 30 12:38:45 PM PDT 24 |
Apr 30 12:38:55 PM PDT 24 |
19616610975 ps |
| T338 |
/workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1972854019 |
|
|
Apr 30 12:37:06 PM PDT 24 |
Apr 30 12:38:19 PM PDT 24 |
105253484136 ps |
| T462 |
/workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2497222658 |
|
|
Apr 30 12:37:47 PM PDT 24 |
Apr 30 12:37:51 PM PDT 24 |
2490048737 ps |
| T463 |
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4073437752 |
|
|
Apr 30 12:38:19 PM PDT 24 |
Apr 30 12:38:24 PM PDT 24 |
2514793871 ps |
| T357 |
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2561236236 |
|
|
Apr 30 12:38:45 PM PDT 24 |
Apr 30 12:39:50 PM PDT 24 |
46647560063 ps |
| T464 |
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1978912794 |
|
|
Apr 30 12:37:56 PM PDT 24 |
Apr 30 12:38:04 PM PDT 24 |
2514523193 ps |
| T465 |
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4223855311 |
|
|
Apr 30 12:38:07 PM PDT 24 |
Apr 30 12:38:11 PM PDT 24 |
3333702949 ps |
| T466 |
/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1811095615 |
|
|
Apr 30 12:37:30 PM PDT 24 |
Apr 30 12:37:36 PM PDT 24 |
2120121167 ps |
| T467 |
/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3553480032 |
|
|
Apr 30 12:37:33 PM PDT 24 |
Apr 30 12:37:48 PM PDT 24 |
11041749905 ps |
| T468 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2793492554 |
|
|
Apr 30 12:36:23 PM PDT 24 |
Apr 30 12:36:31 PM PDT 24 |
2521911050 ps |
| T469 |
/workspace/coverage/default/3.sysrst_ctrl_alert_test.180845085 |
|
|
Apr 30 12:36:25 PM PDT 24 |
Apr 30 12:36:29 PM PDT 24 |
2014719374 ps |
| T470 |
/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2731360656 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:37:42 PM PDT 24 |
2530563513 ps |
| T471 |
/workspace/coverage/default/38.sysrst_ctrl_alert_test.590153472 |
|
|
Apr 30 12:37:56 PM PDT 24 |
Apr 30 12:37:59 PM PDT 24 |
2044250693 ps |
| T74 |
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2411220375 |
|
|
Apr 30 12:38:21 PM PDT 24 |
Apr 30 12:38:53 PM PDT 24 |
22064229716 ps |
| T343 |
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2125871778 |
|
|
Apr 30 12:38:46 PM PDT 24 |
Apr 30 12:40:26 PM PDT 24 |
76254266034 ps |
| T472 |
/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.50674950 |
|
|
Apr 30 12:37:16 PM PDT 24 |
Apr 30 12:37:52 PM PDT 24 |
24839316413 ps |
| T473 |
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3185749600 |
|
|
Apr 30 12:36:20 PM PDT 24 |
Apr 30 12:36:29 PM PDT 24 |
2475859735 ps |
| T474 |
/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1736376009 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:37:44 PM PDT 24 |
2058156083 ps |
| T277 |
/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.565236625 |
|
|
Apr 30 12:37:14 PM PDT 24 |
Apr 30 12:37:20 PM PDT 24 |
3715409489 ps |
| T475 |
/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.917913937 |
|
|
Apr 30 12:36:42 PM PDT 24 |
Apr 30 12:36:50 PM PDT 24 |
2511981682 ps |
| T371 |
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2482221266 |
|
|
Apr 30 12:38:44 PM PDT 24 |
Apr 30 12:40:20 PM PDT 24 |
73219622290 ps |
| T476 |
/workspace/coverage/default/22.sysrst_ctrl_stress_all.3474525436 |
|
|
Apr 30 12:37:08 PM PDT 24 |
Apr 30 12:37:28 PM PDT 24 |
14518236539 ps |
| T477 |
/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2011058884 |
|
|
Apr 30 12:37:31 PM PDT 24 |
Apr 30 12:37:34 PM PDT 24 |
2640790813 ps |
| T478 |
/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3034199131 |
|
|
Apr 30 12:37:37 PM PDT 24 |
Apr 30 12:37:39 PM PDT 24 |
3443412656 ps |
| T479 |
/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1935807782 |
|
|
Apr 30 12:37:46 PM PDT 24 |
Apr 30 12:37:54 PM PDT 24 |
2511212265 ps |
| T123 |
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3984399516 |
|
|
Apr 30 12:38:11 PM PDT 24 |
Apr 30 12:41:05 PM PDT 24 |
574932501463 ps |
| T480 |
/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3496160333 |
|
|
Apr 30 12:37:39 PM PDT 24 |
Apr 30 12:37:47 PM PDT 24 |
2612923214 ps |
| T481 |
/workspace/coverage/default/15.sysrst_ctrl_alert_test.2663695515 |
|
|
Apr 30 12:36:59 PM PDT 24 |
Apr 30 12:37:03 PM PDT 24 |
2029452252 ps |
| T482 |
/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1727115196 |
|
|
Apr 30 12:36:34 PM PDT 24 |
Apr 30 12:36:37 PM PDT 24 |
2535375525 ps |
| T299 |
/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1975658373 |
|
|
Apr 30 12:37:17 PM PDT 24 |
Apr 30 12:39:49 PM PDT 24 |
54874320173 ps |
| T117 |
/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.185988574 |
|
|
Apr 30 12:36:43 PM PDT 24 |
Apr 30 12:38:11 PM PDT 24 |
124895560655 ps |
| T483 |
/workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3488814001 |
|
|
Apr 30 12:38:00 PM PDT 24 |
Apr 30 12:38:03 PM PDT 24 |
2495601030 ps |
| T73 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.582812113 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:38:59 PM PDT 24 |
51675691915 ps |
| T344 |
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3953561268 |
|
|
Apr 30 12:38:43 PM PDT 24 |
Apr 30 12:41:22 PM PDT 24 |
132944226495 ps |
| T484 |
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.647185448 |
|
|
Apr 30 12:38:11 PM PDT 24 |
Apr 30 12:38:18 PM PDT 24 |
2451528873 ps |
| T485 |
/workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.2362731527 |
|
|
Apr 30 12:37:35 PM PDT 24 |
Apr 30 12:37:43 PM PDT 24 |
2612344058 ps |
| T486 |
/workspace/coverage/default/17.sysrst_ctrl_stress_all.993914656 |
|
|
Apr 30 12:36:56 PM PDT 24 |
Apr 30 12:37:22 PM PDT 24 |
13269982908 ps |
| T487 |
/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.521934723 |
|
|
Apr 30 12:37:05 PM PDT 24 |
Apr 30 12:37:14 PM PDT 24 |
3138338079 ps |
| T488 |
/workspace/coverage/default/11.sysrst_ctrl_alert_test.3016933598 |
|
|
Apr 30 12:36:36 PM PDT 24 |
Apr 30 12:36:39 PM PDT 24 |
2028894450 ps |
| T282 |
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2240913267 |
|
|
Apr 30 12:38:03 PM PDT 24 |
Apr 30 12:38:16 PM PDT 24 |
8397274714 ps |
| T489 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all.3646960594 |
|
|
Apr 30 12:37:39 PM PDT 24 |
Apr 30 12:41:56 PM PDT 24 |
131730004058 ps |
| T169 |
/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3523081177 |
|
|
Apr 30 12:36:19 PM PDT 24 |
Apr 30 12:39:14 PM PDT 24 |
65168070202 ps |
| T490 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3299934910 |
|
|
Apr 30 12:36:13 PM PDT 24 |
Apr 30 12:36:16 PM PDT 24 |
2523322722 ps |
| T491 |
/workspace/coverage/default/34.sysrst_ctrl_combo_detect.3192428184 |
|
|
Apr 30 12:37:46 PM PDT 24 |
Apr 30 12:42:26 PM PDT 24 |
104383127756 ps |
| T356 |
/workspace/coverage/default/16.sysrst_ctrl_stress_all.814924632 |
|
|
Apr 30 12:36:55 PM PDT 24 |
Apr 30 12:40:29 PM PDT 24 |
85880161449 ps |
| T339 |
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.328883777 |
|
|
Apr 30 12:38:32 PM PDT 24 |
Apr 30 12:44:05 PM PDT 24 |
122542346183 ps |
| T492 |
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1171555505 |
|
|
Apr 30 12:36:20 PM PDT 24 |
Apr 30 12:36:23 PM PDT 24 |
2166096473 ps |
| T493 |
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2896372709 |
|
|
Apr 30 12:38:13 PM PDT 24 |
Apr 30 12:39:02 PM PDT 24 |
34881559847 ps |
| T283 |
/workspace/coverage/default/12.sysrst_ctrl_stress_all.3631984325 |
|
|
Apr 30 12:36:44 PM PDT 24 |
Apr 30 12:37:07 PM PDT 24 |
8185442252 ps |
| T494 |
/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.11243397 |
|
|
Apr 30 12:36:55 PM PDT 24 |
Apr 30 12:37:12 PM PDT 24 |
22609662437 ps |
| T354 |
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3742411889 |
|
|
Apr 30 12:38:36 PM PDT 24 |
Apr 30 12:40:18 PM PDT 24 |
41473900777 ps |
| T495 |
/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1932610431 |
|
|
Apr 30 12:36:20 PM PDT 24 |
Apr 30 12:36:26 PM PDT 24 |
3369024108 ps |
| T496 |
/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1299930045 |
|
|
Apr 30 12:37:55 PM PDT 24 |
Apr 30 12:40:34 PM PDT 24 |
129029450485 ps |
| T497 |
/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2562932859 |
|
|
Apr 30 12:38:03 PM PDT 24 |
Apr 30 12:38:05 PM PDT 24 |
3540533822 ps |
| T240 |
/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3921989249 |
|
|
Apr 30 12:37:05 PM PDT 24 |
Apr 30 12:37:51 PM PDT 24 |
65396205781 ps |
| T498 |
/workspace/coverage/default/32.sysrst_ctrl_edge_detect.2733922810 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:37:45 PM PDT 24 |
3867665595 ps |
| T211 |
/workspace/coverage/default/10.sysrst_ctrl_stress_all.2451526901 |
|
|
Apr 30 12:36:32 PM PDT 24 |
Apr 30 12:37:18 PM PDT 24 |
18598759000 ps |
| T499 |
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2868754992 |
|
|
Apr 30 12:38:02 PM PDT 24 |
Apr 30 12:38:08 PM PDT 24 |
9556930079 ps |
| T372 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.4043373056 |
|
|
Apr 30 12:36:35 PM PDT 24 |
Apr 30 12:37:45 PM PDT 24 |
72428808275 ps |
| T500 |
/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1994194929 |
|
|
Apr 30 12:36:58 PM PDT 24 |
Apr 30 12:37:06 PM PDT 24 |
2613306372 ps |
| T501 |
/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.317589031 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:37:52 PM PDT 24 |
4011590272 ps |
| T502 |
/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.519503418 |
|
|
Apr 30 12:37:22 PM PDT 24 |
Apr 30 12:39:46 PM PDT 24 |
55771111035 ps |
| T503 |
/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2133652533 |
|
|
Apr 30 12:37:13 PM PDT 24 |
Apr 30 12:37:21 PM PDT 24 |
2514458929 ps |
| T504 |
/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1053397630 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:27 PM PDT 24 |
2531517603 ps |
| T505 |
/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3887181412 |
|
|
Apr 30 12:36:58 PM PDT 24 |
Apr 30 12:37:02 PM PDT 24 |
2514073935 ps |
| T506 |
/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2152119174 |
|
|
Apr 30 12:36:17 PM PDT 24 |
Apr 30 12:36:25 PM PDT 24 |
2613002088 ps |
| T507 |
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3950806233 |
|
|
Apr 30 12:36:54 PM PDT 24 |
Apr 30 12:37:00 PM PDT 24 |
3614846496 ps |
| T508 |
/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1517739268 |
|
|
Apr 30 12:37:14 PM PDT 24 |
Apr 30 12:37:22 PM PDT 24 |
2511186072 ps |
| T278 |
/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1821594081 |
|
|
Apr 30 12:38:05 PM PDT 24 |
Apr 30 12:41:21 PM PDT 24 |
79483993987 ps |
| T162 |
/workspace/coverage/default/25.sysrst_ctrl_edge_detect.1546312519 |
|
|
Apr 30 12:37:14 PM PDT 24 |
Apr 30 12:37:20 PM PDT 24 |
3599403434 ps |
| T509 |
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4153730946 |
|
|
Apr 30 12:38:17 PM PDT 24 |
Apr 30 12:48:51 PM PDT 24 |
245202306355 ps |
| T510 |
/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2344620727 |
|
|
Apr 30 12:36:43 PM PDT 24 |
Apr 30 12:36:55 PM PDT 24 |
3815266344 ps |
| T511 |
/workspace/coverage/default/18.sysrst_ctrl_edge_detect.1950781412 |
|
|
Apr 30 12:36:52 PM PDT 24 |
Apr 30 12:36:57 PM PDT 24 |
2676305971 ps |
| T512 |
/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1811413116 |
|
|
Apr 30 12:37:29 PM PDT 24 |
Apr 30 12:37:32 PM PDT 24 |
2482057298 ps |
| T179 |
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.530609923 |
|
|
Apr 30 12:38:05 PM PDT 24 |
Apr 30 12:39:23 PM PDT 24 |
60108661108 ps |
| T513 |
/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2236175064 |
|
|
Apr 30 12:37:22 PM PDT 24 |
Apr 30 12:37:24 PM PDT 24 |
2520985182 ps |
| T514 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3098777626 |
|
|
Apr 30 12:36:25 PM PDT 24 |
Apr 30 12:36:28 PM PDT 24 |
2217443552 ps |
| T515 |
/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2404651095 |
|
|
Apr 30 12:36:46 PM PDT 24 |
Apr 30 12:36:49 PM PDT 24 |
4845300264 ps |
| T516 |
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2183506729 |
|
|
Apr 30 12:38:30 PM PDT 24 |
Apr 30 12:38:32 PM PDT 24 |
2262062082 ps |
| T366 |
/workspace/coverage/default/3.sysrst_ctrl_stress_all.213183561 |
|
|
Apr 30 12:36:28 PM PDT 24 |
Apr 30 12:42:05 PM PDT 24 |
138760780162 ps |
| T517 |
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3065677747 |
|
|
Apr 30 12:38:15 PM PDT 24 |
Apr 30 12:38:23 PM PDT 24 |
2466179754 ps |
| T518 |
/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.270914907 |
|
|
Apr 30 12:37:30 PM PDT 24 |
Apr 30 12:37:35 PM PDT 24 |
4216001308 ps |
| T329 |
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2279080208 |
|
|
Apr 30 12:38:46 PM PDT 24 |
Apr 30 12:40:09 PM PDT 24 |
62404758324 ps |
| T519 |
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.4263562211 |
|
|
Apr 30 12:38:32 PM PDT 24 |
Apr 30 12:38:40 PM PDT 24 |
2507432763 ps |
| T520 |
/workspace/coverage/default/0.sysrst_ctrl_edge_detect.330187933 |
|
|
Apr 30 12:36:11 PM PDT 24 |
Apr 30 12:36:17 PM PDT 24 |
2958727587 ps |
| T521 |
/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3774637690 |
|
|
Apr 30 12:37:55 PM PDT 24 |
Apr 30 12:46:35 PM PDT 24 |
208250876001 ps |
| T522 |
/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1912252302 |
|
|
Apr 30 12:36:34 PM PDT 24 |
Apr 30 12:36:39 PM PDT 24 |
2469177482 ps |
| T218 |
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.3402957583 |
|
|
Apr 30 12:36:31 PM PDT 24 |
Apr 30 12:43:02 PM PDT 24 |
145050538381 ps |
| T206 |
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1121125923 |
|
|
Apr 30 12:36:33 PM PDT 24 |
Apr 30 12:36:40 PM PDT 24 |
2781774866 ps |
| T523 |
/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2784173050 |
|
|
Apr 30 12:37:17 PM PDT 24 |
Apr 30 12:37:22 PM PDT 24 |
2108170437 ps |
| T524 |
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3157608171 |
|
|
Apr 30 12:36:29 PM PDT 24 |
Apr 30 12:36:35 PM PDT 24 |
14457127735 ps |
| T525 |
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2211422829 |
|
|
Apr 30 12:36:27 PM PDT 24 |
Apr 30 12:36:32 PM PDT 24 |
3512272474 ps |
| T526 |
/workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1260448692 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:36:55 PM PDT 24 |
2036380702 ps |
| T241 |
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4122227406 |
|
|
Apr 30 12:38:03 PM PDT 24 |
Apr 30 12:39:05 PM PDT 24 |
232842673974 ps |
| T527 |
/workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.669920356 |
|
|
Apr 30 12:37:14 PM PDT 24 |
Apr 30 12:37:18 PM PDT 24 |
2618507777 ps |
| T219 |
/workspace/coverage/default/13.sysrst_ctrl_stress_all.884321051 |
|
|
Apr 30 12:36:52 PM PDT 24 |
Apr 30 12:37:26 PM PDT 24 |
14441633212 ps |
| T331 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2919187177 |
|
|
Apr 30 12:38:02 PM PDT 24 |
Apr 30 12:40:15 PM PDT 24 |
88165174525 ps |
| T528 |
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2866508838 |
|
|
Apr 30 12:38:42 PM PDT 24 |
Apr 30 12:39:11 PM PDT 24 |
22591730993 ps |
| T180 |
/workspace/coverage/default/27.sysrst_ctrl_edge_detect.1099137619 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:28 PM PDT 24 |
2948109508 ps |
| T182 |
/workspace/coverage/default/0.sysrst_ctrl_stress_all.2281726209 |
|
|
Apr 30 12:36:11 PM PDT 24 |
Apr 30 12:36:29 PM PDT 24 |
20487839205 ps |
| T183 |
/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.46673585 |
|
|
Apr 30 12:37:02 PM PDT 24 |
Apr 30 12:37:05 PM PDT 24 |
2503024069 ps |
| T184 |
/workspace/coverage/default/35.sysrst_ctrl_alert_test.3872584292 |
|
|
Apr 30 12:37:48 PM PDT 24 |
Apr 30 12:37:54 PM PDT 24 |
2017398598 ps |
| T185 |
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2182617910 |
|
|
Apr 30 12:38:22 PM PDT 24 |
Apr 30 12:38:25 PM PDT 24 |
3433299680 ps |
| T186 |
/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.966190600 |
|
|
Apr 30 12:37:45 PM PDT 24 |
Apr 30 12:37:48 PM PDT 24 |
2185878967 ps |
| T187 |
/workspace/coverage/default/30.sysrst_ctrl_smoke.106274075 |
|
|
Apr 30 12:37:27 PM PDT 24 |
Apr 30 12:37:29 PM PDT 24 |
2137550846 ps |
| T188 |
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3696479356 |
|
|
Apr 30 12:38:21 PM PDT 24 |
Apr 30 12:51:11 PM PDT 24 |
310544523460 ps |
| T189 |
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.4172295456 |
|
|
Apr 30 12:38:32 PM PDT 24 |
Apr 30 12:38:37 PM PDT 24 |
3520568850 ps |
| T190 |
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1070759205 |
|
|
Apr 30 12:38:42 PM PDT 24 |
Apr 30 12:39:01 PM PDT 24 |
26359420634 ps |
| T234 |
/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.4039751362 |
|
|
Apr 30 12:37:01 PM PDT 24 |
Apr 30 12:37:08 PM PDT 24 |
2036545154 ps |
| T529 |
/workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.111708031 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:35 PM PDT 24 |
4238306659 ps |
| T244 |
/workspace/coverage/default/12.sysrst_ctrl_combo_detect.1615223180 |
|
|
Apr 30 12:36:45 PM PDT 24 |
Apr 30 12:41:36 PM PDT 24 |
123392096766 ps |
| T195 |
/workspace/coverage/default/30.sysrst_ctrl_edge_detect.2850627601 |
|
|
Apr 30 12:37:31 PM PDT 24 |
Apr 30 12:37:42 PM PDT 24 |
4746626235 ps |
| T530 |
/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3157864403 |
|
|
Apr 30 12:38:01 PM PDT 24 |
Apr 30 12:38:11 PM PDT 24 |
3491495619 ps |
| T531 |
/workspace/coverage/default/45.sysrst_ctrl_alert_test.1711625292 |
|
|
Apr 30 12:38:20 PM PDT 24 |
Apr 30 12:38:22 PM PDT 24 |
2039250864 ps |
| T348 |
/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3743800744 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:38:26 PM PDT 24 |
95923139688 ps |
| T532 |
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.915854071 |
|
|
Apr 30 12:38:31 PM PDT 24 |
Apr 30 12:39:07 PM PDT 24 |
25087195391 ps |
| T533 |
/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.850029327 |
|
|
Apr 30 12:36:58 PM PDT 24 |
Apr 30 12:37:04 PM PDT 24 |
2618376034 ps |
| T534 |
/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.609014053 |
|
|
Apr 30 12:37:04 PM PDT 24 |
Apr 30 12:37:07 PM PDT 24 |
3815822519 ps |
| T124 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all.1740252730 |
|
|
Apr 30 12:37:05 PM PDT 24 |
Apr 30 12:38:07 PM PDT 24 |
1242499238976 ps |
| T535 |
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2440838795 |
|
|
Apr 30 12:36:25 PM PDT 24 |
Apr 30 12:36:37 PM PDT 24 |
3694627640 ps |
| T536 |
/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.4246353718 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:25 PM PDT 24 |
2493270723 ps |
| T242 |
/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.793267547 |
|
|
Apr 30 12:36:09 PM PDT 24 |
Apr 30 12:36:48 PM PDT 24 |
84756269258 ps |
| T322 |
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2244194179 |
|
|
Apr 30 12:38:49 PM PDT 24 |
Apr 30 12:40:13 PM PDT 24 |
113242734851 ps |
| T90 |
/workspace/coverage/default/32.sysrst_ctrl_combo_detect.2946053643 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:38:43 PM PDT 24 |
113638693153 ps |
| T537 |
/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1792943205 |
|
|
Apr 30 12:37:36 PM PDT 24 |
Apr 30 12:37:43 PM PDT 24 |
2765717735 ps |
| T538 |
/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.62100744 |
|
|
Apr 30 12:37:24 PM PDT 24 |
Apr 30 12:37:29 PM PDT 24 |
2520044229 ps |
| T539 |
/workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2175603922 |
|
|
Apr 30 12:37:38 PM PDT 24 |
Apr 30 12:37:41 PM PDT 24 |
2482452185 ps |
| T540 |
/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1103613146 |
|
|
Apr 30 12:37:14 PM PDT 24 |
Apr 30 12:37:55 PM PDT 24 |
31212691922 ps |
| T541 |
/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.243550519 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:37:04 PM PDT 24 |
3401838424 ps |
| T542 |
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2130011988 |
|
|
Apr 30 12:38:03 PM PDT 24 |
Apr 30 12:38:06 PM PDT 24 |
3373400068 ps |
| T543 |
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1299737103 |
|
|
Apr 30 12:36:26 PM PDT 24 |
Apr 30 12:36:35 PM PDT 24 |
2610275612 ps |
| T544 |
/workspace/coverage/default/10.sysrst_ctrl_alert_test.956149385 |
|
|
Apr 30 12:36:33 PM PDT 24 |
Apr 30 12:36:37 PM PDT 24 |
2014921392 ps |
| T545 |
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2872331147 |
|
|
Apr 30 12:38:20 PM PDT 24 |
Apr 30 12:38:27 PM PDT 24 |
3990493409 ps |
| T546 |
/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.260732382 |
|
|
Apr 30 12:37:55 PM PDT 24 |
Apr 30 12:38:03 PM PDT 24 |
2260472113 ps |
| T547 |
/workspace/coverage/default/33.sysrst_ctrl_stress_all.1397942679 |
|
|
Apr 30 12:37:38 PM PDT 24 |
Apr 30 12:37:46 PM PDT 24 |
11033148979 ps |
| T548 |
/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.852563147 |
|
|
Apr 30 12:36:14 PM PDT 24 |
Apr 30 12:36:16 PM PDT 24 |
2635697221 ps |
| T151 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1647618836 |
|
|
Apr 30 12:36:58 PM PDT 24 |
Apr 30 12:38:03 PM PDT 24 |
161782669214 ps |
| T549 |
/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.5240133 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:31 PM PDT 24 |
2613521147 ps |
| T550 |
/workspace/coverage/default/24.sysrst_ctrl_smoke.3773546751 |
|
|
Apr 30 12:37:17 PM PDT 24 |
Apr 30 12:37:19 PM PDT 24 |
2125816399 ps |
| T551 |
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1474160165 |
|
|
Apr 30 12:38:36 PM PDT 24 |
Apr 30 12:38:38 PM PDT 24 |
2049731549 ps |
| T552 |
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3683497278 |
|
|
Apr 30 12:38:05 PM PDT 24 |
Apr 30 12:38:08 PM PDT 24 |
2120601199 ps |
| T553 |
/workspace/coverage/default/2.sysrst_ctrl_pin_access_test.859810309 |
|
|
Apr 30 12:36:22 PM PDT 24 |
Apr 30 12:36:28 PM PDT 24 |
2223887758 ps |
| T91 |
/workspace/coverage/default/36.sysrst_ctrl_combo_detect.3226862959 |
|
|
Apr 30 12:37:47 PM PDT 24 |
Apr 30 12:40:06 PM PDT 24 |
52129318492 ps |
| T554 |
/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1731286431 |
|
|
Apr 30 12:37:00 PM PDT 24 |
Apr 30 12:37:58 PM PDT 24 |
20818389087 ps |
| T555 |
/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3862535678 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:38:37 PM PDT 24 |
42262882983 ps |
| T556 |
/workspace/coverage/default/29.sysrst_ctrl_smoke.604522998 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:25 PM PDT 24 |
2173179343 ps |
| T557 |
/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.2591033972 |
|
|
Apr 30 12:37:23 PM PDT 24 |
Apr 30 12:37:25 PM PDT 24 |
2581933519 ps |
| T558 |
/workspace/coverage/default/15.sysrst_ctrl_smoke.2934644118 |
|
|
Apr 30 12:36:41 PM PDT 24 |
Apr 30 12:36:44 PM PDT 24 |
2129612905 ps |
| T559 |
/workspace/coverage/default/22.sysrst_ctrl_alert_test.3139692842 |
|
|
Apr 30 12:37:12 PM PDT 24 |
Apr 30 12:37:14 PM PDT 24 |
2051063271 ps |
| T560 |
/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1024357122 |
|
|
Apr 30 12:37:28 PM PDT 24 |
Apr 30 12:37:39 PM PDT 24 |
3611708627 ps |
| T561 |
/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.998724995 |
|
|
Apr 30 12:37:39 PM PDT 24 |
Apr 30 12:37:46 PM PDT 24 |
2510664546 ps |
| T562 |
/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.4155215111 |
|
|
Apr 30 12:37:39 PM PDT 24 |
Apr 30 12:37:45 PM PDT 24 |
2179836972 ps |
| T212 |
/workspace/coverage/default/13.sysrst_ctrl_edge_detect.3441656811 |
|
|
Apr 30 12:36:41 PM PDT 24 |
Apr 30 12:36:57 PM PDT 24 |
5532990659 ps |
| T563 |
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1881946418 |
|
|
Apr 30 12:38:06 PM PDT 24 |
Apr 30 12:38:12 PM PDT 24 |
3016315864 ps |
| T564 |
/workspace/coverage/default/23.sysrst_ctrl_alert_test.916621174 |
|
|
Apr 30 12:37:15 PM PDT 24 |
Apr 30 12:37:22 PM PDT 24 |
2010206808 ps |
| T152 |
/workspace/coverage/default/20.sysrst_ctrl_edge_detect.2036138395 |
|
|
Apr 30 12:37:03 PM PDT 24 |
Apr 30 12:37:21 PM PDT 24 |
1053385889451 ps |
| T565 |
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1182204117 |
|
|
Apr 30 12:38:05 PM PDT 24 |
Apr 30 12:38:10 PM PDT 24 |
2617062805 ps |
| T365 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect.1533232711 |
|
|
Apr 30 12:38:03 PM PDT 24 |
Apr 30 12:40:48 PM PDT 24 |
125544666806 ps |
| T566 |
/workspace/coverage/default/12.sysrst_ctrl_alert_test.125034751 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:36:55 PM PDT 24 |
2033334623 ps |
| T567 |
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2497473060 |
|
|
Apr 30 12:36:27 PM PDT 24 |
Apr 30 12:37:18 PM PDT 24 |
69873688387 ps |
| T568 |
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.448644449 |
|
|
Apr 30 12:38:36 PM PDT 24 |
Apr 30 12:38:44 PM PDT 24 |
3192547645 ps |
| T569 |
/workspace/coverage/default/0.sysrst_ctrl_smoke.2383363844 |
|
|
Apr 30 12:36:13 PM PDT 24 |
Apr 30 12:36:20 PM PDT 24 |
2111315648 ps |
| T125 |
/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.261347808 |
|
|
Apr 30 12:37:17 PM PDT 24 |
Apr 30 12:37:23 PM PDT 24 |
9655232122 ps |
| T345 |
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1646701449 |
|
|
Apr 30 12:38:44 PM PDT 24 |
Apr 30 12:40:51 PM PDT 24 |
99943741573 ps |
| T570 |
/workspace/coverage/default/30.sysrst_ctrl_stress_all.2568744126 |
|
|
Apr 30 12:37:30 PM PDT 24 |
Apr 30 12:37:38 PM PDT 24 |
8900043690 ps |
| T253 |
/workspace/coverage/default/30.sysrst_ctrl_combo_detect.1526471497 |
|
|
Apr 30 12:37:31 PM PDT 24 |
Apr 30 12:38:45 PM PDT 24 |
105696274671 ps |
| T274 |
/workspace/coverage/default/3.sysrst_ctrl_sec_cm.772801993 |
|
|
Apr 30 12:36:25 PM PDT 24 |
Apr 30 12:37:18 PM PDT 24 |
42053775975 ps |
| T571 |
/workspace/coverage/default/34.sysrst_ctrl_alert_test.2211477765 |
|
|
Apr 30 12:37:48 PM PDT 24 |
Apr 30 12:37:51 PM PDT 24 |
2032132502 ps |
| T92 |
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1415095005 |
|
|
Apr 30 12:38:10 PM PDT 24 |
Apr 30 12:38:52 PM PDT 24 |
15541580273 ps |
| T103 |
/workspace/coverage/default/48.sysrst_ctrl_smoke.3727936910 |
|
|
Apr 30 12:38:32 PM PDT 24 |
Apr 30 12:38:38 PM PDT 24 |
2113735324 ps |
| T104 |
/workspace/coverage/default/31.sysrst_ctrl_smoke.3042032849 |
|
|
Apr 30 12:37:30 PM PDT 24 |
Apr 30 12:37:37 PM PDT 24 |
2109548702 ps |
| T105 |
/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.473422859 |
|
|
Apr 30 12:36:55 PM PDT 24 |
Apr 30 12:41:18 PM PDT 24 |
106192777510 ps |
| T106 |
/workspace/coverage/default/28.sysrst_ctrl_combo_detect.4008087670 |
|
|
Apr 30 12:37:24 PM PDT 24 |
Apr 30 12:40:40 PM PDT 24 |
77107985312 ps |
| T107 |
/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1217970153 |
|
|
Apr 30 12:37:10 PM PDT 24 |
Apr 30 12:37:24 PM PDT 24 |
5363694924 ps |
| T108 |
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2732254999 |
|
|
Apr 30 12:38:32 PM PDT 24 |
Apr 30 12:38:35 PM PDT 24 |
2468491859 ps |
| T109 |
/workspace/coverage/default/23.sysrst_ctrl_edge_detect.1217898217 |
|
|
Apr 30 12:37:15 PM PDT 24 |
Apr 30 12:37:23 PM PDT 24 |
2897661984 ps |
| T110 |
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3379729000 |
|
|
Apr 30 12:38:42 PM PDT 24 |
Apr 30 12:40:16 PM PDT 24 |
66385861742 ps |
| T111 |
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.97799076 |
|
|
Apr 30 12:38:32 PM PDT 24 |
Apr 30 12:38:37 PM PDT 24 |
3333842707 ps |
| T213 |
/workspace/coverage/default/39.sysrst_ctrl_edge_detect.2028817255 |
|
|
Apr 30 12:38:02 PM PDT 24 |
Apr 30 12:38:05 PM PDT 24 |
2924591351 ps |
| T572 |
/workspace/coverage/default/4.sysrst_ctrl_smoke.33492640 |
|
|
Apr 30 12:36:20 PM PDT 24 |
Apr 30 12:36:22 PM PDT 24 |
2135204169 ps |
| T573 |
/workspace/coverage/default/33.sysrst_ctrl_smoke.960169700 |
|
|
Apr 30 12:37:40 PM PDT 24 |
Apr 30 12:37:42 PM PDT 24 |
2137997414 ps |
| T574 |
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2847585569 |
|
|
Apr 30 12:38:31 PM PDT 24 |
Apr 30 12:38:53 PM PDT 24 |
15525310191 ps |
| T367 |
/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2315185810 |
|
|
Apr 30 12:37:55 PM PDT 24 |
Apr 30 12:39:22 PM PDT 24 |
29831042825 ps |
| T575 |
/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3893572399 |
|
|
Apr 30 12:36:57 PM PDT 24 |
Apr 30 12:37:10 PM PDT 24 |
4342145045 ps |
| T207 |
/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.632903967 |
|
|
Apr 30 12:37:49 PM PDT 24 |
Apr 30 12:39:09 PM PDT 24 |
129016781154 ps |
| T576 |
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1880670228 |
|
|
Apr 30 12:38:14 PM PDT 24 |
Apr 30 12:38:17 PM PDT 24 |
2533883593 ps |
| T318 |
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2616394150 |
|
|
Apr 30 12:38:01 PM PDT 24 |
Apr 30 12:43:09 PM PDT 24 |
119457145285 ps |
| T577 |
/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2873864682 |
|
|
Apr 30 12:36:59 PM PDT 24 |
Apr 30 12:38:53 PM PDT 24 |
249705199883 ps |
| T578 |
/workspace/coverage/default/6.sysrst_ctrl_smoke.2771245656 |
|
|
Apr 30 12:36:25 PM PDT 24 |
Apr 30 12:36:28 PM PDT 24 |
2128237927 ps |
| T579 |
/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1068721764 |
|
|
Apr 30 12:36:53 PM PDT 24 |
Apr 30 12:36:56 PM PDT 24 |
4631588439 ps |
| T580 |
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1070170395 |
|
|
Apr 30 12:38:12 PM PDT 24 |
Apr 30 12:38:16 PM PDT 24 |
5214271766 ps |
| T581 |
/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1925022827 |
|
|
Apr 30 12:37:16 PM PDT 24 |
Apr 30 12:37:19 PM PDT 24 |
2162739801 ps |
| T153 |
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3282325720 |
|
|
Apr 30 12:36:28 PM PDT 24 |
Apr 30 12:38:10 PM PDT 24 |
306346409548 ps |
| T582 |
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3093565330 |
|
|
Apr 30 12:38:19 PM PDT 24 |
Apr 30 12:38:46 PM PDT 24 |
12861367165 ps |
| T154 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1077767474 |
|
|
Apr 30 12:37:08 PM PDT 24 |
Apr 30 12:37:36 PM PDT 24 |
38782166397 ps |
| T583 |
/workspace/coverage/default/36.sysrst_ctrl_alert_test.2018512146 |
|
|
Apr 30 12:37:54 PM PDT 24 |
Apr 30 12:37:56 PM PDT 24 |
2032690056 ps |
| T584 |
/workspace/coverage/default/37.sysrst_ctrl_stress_all.2173947596 |
|
|
Apr 30 12:37:56 PM PDT 24 |
Apr 30 12:38:06 PM PDT 24 |
13400904140 ps |
| T585 |
/workspace/coverage/default/32.sysrst_ctrl_smoke.1791315760 |
|
|
Apr 30 12:37:32 PM PDT 24 |
Apr 30 12:37:34 PM PDT 24 |
2132523391 ps |
| T586 |
/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1297084614 |
|
|
Apr 30 12:36:19 PM PDT 24 |
Apr 30 12:36:23 PM PDT 24 |
3724455516 ps |
| T587 |
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1679199591 |
|
|
Apr 30 12:38:23 PM PDT 24 |
Apr 30 12:38:29 PM PDT 24 |
2031036101 ps |
| T588 |
/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.359508824 |
|
|
Apr 30 12:37:14 PM PDT 24 |
Apr 30 12:37:20 PM PDT 24 |
3453690749 ps |
| T589 |
/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.233715597 |
|
|
Apr 30 12:36:08 PM PDT 24 |
Apr 30 12:36:11 PM PDT 24 |
2532188570 ps |
| T590 |
/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3921324658 |
|
|
Apr 30 12:36:54 PM PDT 24 |
Apr 30 12:46:10 PM PDT 24 |
220712317341 ps |
| T245 |
/workspace/coverage/default/37.sysrst_ctrl_combo_detect.852661156 |
|
|
Apr 30 12:37:54 PM PDT 24 |
Apr 30 12:41:47 PM PDT 24 |
83460361879 ps |
| T591 |
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1159075860 |
|
|
Apr 30 12:38:42 PM PDT 24 |
Apr 30 12:39:03 PM PDT 24 |
59345575073 ps |