Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2281

1

T9

7

T11

10

T16

23

auto[1]

679

1

T9

1

T11

6

T16

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2236

1

T9

3

T11

14

T16

23

auto[1]

724

1

T9

5

T11

2

T16

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2195

1

T9

4

T11

12

T16

23

auto[1]

765

1

T9

4

T11

4

T16

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2214

1

T11

16

T16

17

T30

9

auto[1]

746

1

T9

8

T16

7

T30

16

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2702

1

T9

8

T11

16

T16

21

auto[1]

258

1

T16

3

T32

5

T31

11

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2662

1

T9

8

T11

16

T16

18

auto[1]

298

1

T16

6

T31

4

T43

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2651

1

T9

8

T11

14

T16

21

auto[1]

309

1

T11

2

T16

3

T32

13

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2629

1

T9

8

T11

16

T16

23

auto[1]

331

1

T16

1

T32

7

T31

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2735

1

T9

8

T11

10

T16

23

auto[1]

225

1

T11

6

T16

1

T31

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2218

1

T9

4

T11

16

T16

22

auto[1]

742

1

T9

4

T16

2

T30

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

922

1

T9

8

T30

25

T41

14

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

80

1

T47

8

T158

5

T344

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T11

1

T244

2

T336

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T16

1

T31

6

T345

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

134

1

T32

4

T31

2

T47

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T158

2

T346

7

T229

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T47

6

T158

2

T333

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T347

1

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

121

1

T32

5

T46

1

T333

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T16

2

T32

5

T47

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T11

1

T348

5

T349

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T66

1

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T32

3

T257

1

T337

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T346

7

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T344

1

T348

4

T350

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

118

1

T16

5

T105

4

T266

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T351

1

T348

8

T352

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

10

1

T344

4

T287

2

T353

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T31

2

T43

1

T108

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

23

1

T195

2

T353

5

T354

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T66

30

T117

1

T335

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T31

2

T66

7

T350

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T355

3

T356

4

T357

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

12

1

T16

1

T358

3

T359

2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133

1

T16

1

T104

8

T277

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

114

1

T245

13

T336

6

T360

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T105

4

T248

2

T249

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

146

1

T16

5

T30

11

T31

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

63

1

T41

8

T44

7

T331

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

94

1

T16

2

T44

6

T47

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

52

1

T45

1

T242

2

T267

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

168

1

T30

9

T43

1

T44

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T11

1

T31

2

T45

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

100

1

T32

4

T242

5

T104

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T341

1

T361

4

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T9

3

T31

2

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T266

1

T344

4

T236

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32

1

T30

1

T104

5

T177

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T243

1

T331

2

T360

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

86

1

T267

2

T247

10

T177

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

74

1

T11

1

T83

3

T106

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T32

3

T158

5

T336

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T242

1

T247

3

T177

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

83

1

T30

4

T32

5

T66

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T176

4

T94

1

T195

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T9

4

T32

5

T44

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T46

1

T106

1

T245

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

139

1

T16

1

T31

6

T47

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T41

6

T47

10

T331

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T176

5

T233

6

T362

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T331

2

T250

2

T363

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T235

2

T110

4

T341

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T9

1

T45

1

T258

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T106

1

T260

3

T239

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T331

1

T248

1

T277

4

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded