Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T9

8

T10

8

T51

10

auto[1]

1159

1

T9

12

T10

12

T51

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T9

4

T10

5

T51

4

from_0to1

552

1

T9

3

T10

4

T51

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T9

15

T10

12

T51

8

auto[1]

1137

1

T9

5

T10

8

T51

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T9

10

T10

12

T51

9

auto[1]

1136

1

T9

10

T10

8

T51

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T9

1

T51

1

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T10

1

T20

1

T65

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T63

1

T45

2

T83

3

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T20

2

T45

3

T83

5

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T20

1

T54

1

T63

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T9

2

T63

1

T65

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T10

1

T20

2

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T51

1

T20

1

T54

2

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T9

1

T10

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T9

1

T10

2

T51

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T51

1

T20

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T9

1

T10

1

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T51

1

T45

3

T83

4

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T10

2

T63

1

T65

2

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T10

1

T51

1

T20

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T9

1

T54

1

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T9

8

T10

9

T51

12

auto[1]

1122

1

T9

12

T10

11

T51

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

536

1

T9

3

T10

5

T51

7

from_0to1

538

1

T9

3

T10

5

T51

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T9

12

T10

12

T51

11

auto[1]

1078

1

T9

8

T10

8

T51

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T9

9

T10

10

T51

12

auto[1]

1094

1

T9

11

T10

10

T51

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T10

2

T54

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T51

1

T83

4

T36

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T51

1

T45

2

T83

5

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T20

1

T63

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T51

1

T63

1

T65

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T10

2

T51

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T10

1

T51

1

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T9

1

T51

2

T83

4

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T51

3

T54

1

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T9

2

T10

1

T51

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T51

1

T20

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T9

1

T10

2

T20

2

auto[1]

from_0to1

auto[0]

auto[0]

83

1

T10

1

T51

1

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T54

1

T63

1

T45

3

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T51

1

T54

2

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T9

2

T10

1

T20

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T9

14

T10

11

T51

11

auto[1]

1152

1

T9

6

T10

9

T51

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T9

4

T10

4

T51

5

from_0to1

535

1

T9

5

T10

5

T51

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T9

9

T10

8

T51

10

auto[1]

1180

1

T9

11

T10

12

T51

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T9

11

T10

8

T51

12

auto[1]

1111

1

T9

9

T10

12

T51

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T9

3

T10

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

81

1

T9

1

T20

1

T45

4

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T20

3

T45

3

T83

4

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T10

1

T51

1

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T9

1

T10

1

T51

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T10

1

T51

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T9

2

T51

2

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T9

1

T10

1

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T54

1

T63

1

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T10

2

T20

1

T63

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T51

2

T54

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T51

2

T54

1

T65

2

auto[1]

from_0to1

auto[0]

auto[0]

80

1

T9

1

T20

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T10

1

T51

2

T20

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T45

3

T83

5

T36

3

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T10

1

T65

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T9

12

T10

8

T51

9

auto[1]

1162

1

T9

8

T10

12

T51

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T9

4

T10

2

T51

6

from_0to1

522

1

T9

4

T10

3

T51

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T9

9

T10

10

T51

8

auto[1]

1143

1

T9

11

T10

10

T51

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1145

1

T9

8

T10

11

T51

11

auto[1]

1106

1

T9

12

T10

9

T51

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T83

1

T36

2

T98

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T9

1

T20

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T9

1

T45

3

T83

3

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T9

2

T51

2

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T20

1

T54

1

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T20

1

T65

2

T45

2

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T9

2

T10

1

T51

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T51

1

T45

1

T83

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T51

1

T20

1

T65

2

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T20

2

T54

1

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T10

1

T51

2

T65

2

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T10

1

T51

1

T54

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T9

1

T10

1

T65

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T9

1

T10

1

T51

3

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T20

1

T54

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T54

2

T45

1

T83

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T9

11

T10

7

T51

8

auto[1]

1138

1

T9

9

T10

13

T51

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

550

1

T9

6

T10

5

T51

6

from_0to1

547

1

T9

6

T10

6

T51

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T9

14

T10

7

T51

12

auto[1]

1066

1

T9

6

T10

13

T51

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T9

9

T10

13

T51

12

auto[1]

1086

1

T9

11

T10

7

T51

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T9

2

T51

1

T20

2

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T51

2

T20

2

T65

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T45

1

T83

3

T36

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T9

1

T10

2

T54

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T9

2

T51

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T9

2

T10

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T10

1

T20

1

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T51

1

T63

1

T36

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T51

1

T54

1

T45

3

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T9

2

T51

1

T65

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T10

3

T51

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T9

1

T63

2

T65

1

auto[1]

from_0to1

auto[0]

auto[0]

88

1

T9

1

T10

2

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T54

1

T63

2

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T10

2

T51

2

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T9

1

T51

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T9

10

T10

10

T51

8

auto[1]

1111

1

T9

10

T10

10

T51

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

551

1

T9

6

T10

4

T51

6

from_0to1

543

1

T9

7

T10

4

T51

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T9

7

T10

12

T51

11

auto[1]

1085

1

T9

13

T10

8

T51

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T9

9

T10

13

T51

11

auto[1]

1090

1

T9

11

T10

7

T51

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

83

1

T51

1

T54

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T9

1

T45

1

T83

2

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T9

2

T10

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T9

1

T54

2

T83

4

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T10

1

T54

2

T63

2

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T10

1

T51

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T9

1

T51

1

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T9

1

T51

1

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T9

1

T10

2

T51

2

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T10

1

T51

2

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T51

1

T20

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T9

1

T20

2

T54

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T9

1

T51

1

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

87

1

T9

1

T51

1

T20

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T10

1

T65

1

T45

3

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T9

3

T10

1

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T9

14

T10

7

T51

9

auto[1]

1090

1

T9

6

T10

13

T51

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T9

5

T10

7

T51

6

from_0to1

551

1

T9

5

T10

6

T51

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T9

9

T10

13

T51

10

auto[1]

1111

1

T9

11

T10

7

T51

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T9

8

T10

10

T51

7

auto[1]

1118

1

T9

12

T10

10

T51

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T10

1

T51

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T9

1

T63

1

T65

2

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T9

2

T10

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T9

1

T63

2

T45

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T10

1

T20

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T54

1

T65

1

T45

3

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T9

1

T63

1

T65

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T9

2

T51

4

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T10

1

T51

1

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T10

2

T51

2

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T9

1

T51

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T10

2

T51

1

T20

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T51

1

T20

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T9

2

T10

2

T51

1

auto[1]

from_0to1

auto[1]

auto[0]

84

1

T10

3

T63

2

T83

5

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T51

1

T65

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T9

9

T10

10

T51

11

auto[1]

1126

1

T9

11

T10

10

T51

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T9

5

T10

4

T51

5

from_0to1

527

1

T9

6

T10

4

T51

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T9

10

T10

12

T51

6

auto[1]

1176

1

T9

10

T10

8

T51

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T9

10

T10

9

T51

9

auto[1]

1140

1

T9

10

T10

11

T51

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T9

1

T10

2

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T54

1

T45

2

T83

3

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T9

1

T10

1

T51

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T20

1

T45

2

T83

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T20

1

T54

2

T83

6

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T9

1

T63

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

80

1

T9

2

T51

1

T20

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T9

1

T10

1

T51

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T20

1

T65

1

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T9

1

T51

1

T54

2

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T20

1

T45

3

T83

6

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T9

2

T10

1

T51

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T9

1

T10

2

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T9

1

T10

1

T51

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T51

1

T54

2

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T54

1

T63

1

T65

1