Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	161024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123594

1

T4

17

T1

7

T2

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	147849	1			T4	23		T1	7		T2	6
values[0x0]	67907	1			T4	5		T1	4		T2	3
values[0x1]	68862	1			T4	6		T1	1		T2	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130423	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

154195

1

T4

18

T1

9

T2

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	918	1			T51	1		T11	8		T16	4
valid_sources[0x01]	1784	1			T11	1		T16	2		T29	2
valid_sources[0x02]	1011	1			T51	1		T16	3		T141	3
valid_sources[0x03]	1775	1			T11	2		T16	5		T53	3
valid_sources[0x04]	896	1			T51	1		T11	1		T16	5
valid_sources[0x05]	930	1			T11	1		T16	2		T65	1
valid_sources[0x06]	862	1			T9	20		T16	5		T54	2
valid_sources[0x07]	1081	1			T15	1		T51	1		T16	3
valid_sources[0x08]	936	1			T11	6		T16	5		T28	6
valid_sources[0x09]	1204	1			T11	3		T16	2		T65	3
valid_sources[0x0a]	936	1			T14	2		T16	2		T20	1
valid_sources[0x0b]	869	1			T1	1		T11	2		T16	4
valid_sources[0x0c]	913	1			T16	4		T54	3		T29	1
valid_sources[0x0d]	1128	1			T1	3		T11	3		T16	5
valid_sources[0x0e]	849	1			T13	12		T15	2		T16	1
valid_sources[0x0f]	1298	1			T23	1		T16	3		T20	1
valid_sources[0x10]	1067	1			T50	1		T23	1		T16	5
valid_sources[0x11]	994	1			T9	2		T51	1		T11	1
valid_sources[0x12]	913	1			T11	17		T16	5		T32	5
valid_sources[0x13]	1062	1			T11	9		T16	2		T141	3
valid_sources[0x14]	917	1			T1	1		T11	4		T16	3
valid_sources[0x15]	1096	1			T16	6		T65	1		T32	6
valid_sources[0x16]	2005	1			T51	1		T11	7		T16	5
valid_sources[0x17]	1002	1			T2	1		T6	1		T11	1
valid_sources[0x18]	1334	1			T11	10		T16	4		T32	8
valid_sources[0x19]	954	1			T1	2		T9	29		T11	7
valid_sources[0x1a]	963	1			T15	1		T11	2		T16	5
valid_sources[0x1b]	908	1			T16	3		T29	1		T53	1
valid_sources[0x1c]	975	1			T11	11		T16	3		T56	1
valid_sources[0x1d]	924	1			T16	2		T54	1		T142	2
valid_sources[0x1e]	1315	1			T14	2		T15	1		T51	3
valid_sources[0x1f]	825	1			T23	1		T16	3		T85	10
valid_sources[0x20]	1087	1			T9	3		T11	1		T16	3
valid_sources[0x21]	1703	1			T51	1		T11	5		T16	2
valid_sources[0x22]	893	1			T11	3		T16	2		T20	1
valid_sources[0x23]	947	1			T11	3		T16	2		T20	2
valid_sources[0x24]	962	1			T11	11		T16	4		T54	1
valid_sources[0x25]	982	1			T11	2		T16	4		T142	1
valid_sources[0x26]	1467	1			T23	1		T51	2		T11	3
valid_sources[0x27]	1105	1			T51	2		T16	3		T20	1
valid_sources[0x28]	821	1			T51	1		T16	4		T20	2
valid_sources[0x29]	1021	1			T11	3		T16	2		T20	2
valid_sources[0x2a]	817	1			T23	1		T51	1		T16	3
valid_sources[0x2b]	963	1			T23	1		T51	1		T11	5
valid_sources[0x2c]	988	1			T23	1		T51	1		T16	3
valid_sources[0x2d]	1800	1			T9	1		T11	2		T16	3
valid_sources[0x2e]	2027	1			T11	1		T16	5		T53	5
valid_sources[0x2f]	879	1			T23	1		T51	1		T16	4
valid_sources[0x30]	898	1			T50	1		T51	1		T11	4
valid_sources[0x31]	1054	1			T51	2		T11	3		T16	9
valid_sources[0x32]	862	1			T51	1		T11	4		T16	3
valid_sources[0x33]	1109	1			T11	1		T16	1		T55	2
valid_sources[0x34]	897	1			T23	1		T11	5		T16	4
valid_sources[0x35]	787	1			T12	2		T50	1		T11	8
valid_sources[0x36]	965	1			T23	2		T11	6		T16	2
valid_sources[0x37]	927	1			T23	1		T16	6		T20	1
valid_sources[0x38]	2169	1			T51	1		T16	6		T20	3
valid_sources[0x39]	992	1			T15	1		T11	5		T16	2
valid_sources[0x3a]	889	1			T11	9		T32	6		T86	3
valid_sources[0x3b]	1714	1			T14	1		T11	7		T16	5
valid_sources[0x3c]	807	1			T6	1		T11	4		T16	2
valid_sources[0x3d]	1056	1			T51	1		T11	13		T16	4
valid_sources[0x3e]	881	1			T23	1		T51	2		T11	1
valid_sources[0x3f]	1000	1			T51	1		T11	12		T16	1
valid_sources[0x40]	1103	1			T51	1		T16	3		T20	4
valid_sources[0x41]	821	1			T2	1		T16	1		T32	1
valid_sources[0x42]	1307	1			T11	1		T16	5		T20	3
valid_sources[0x43]	969	1			T23	2		T16	2		T20	2
valid_sources[0x44]	1984	1			T23	2		T11	4		T16	8
valid_sources[0x45]	952	1			T51	2		T11	13		T16	3
valid_sources[0x46]	1376	1			T11	1		T16	3		T142	1
valid_sources[0x47]	1058	1			T23	1		T51	1		T11	1
valid_sources[0x48]	1130	1			T11	7		T16	4		T20	1
valid_sources[0x49]	1069	1			T16	3		T20	2		T142	1
valid_sources[0x4a]	1183	1			T16	7		T20	1		T32	4
valid_sources[0x4b]	945	1			T23	1		T51	1		T11	4
valid_sources[0x4c]	843	1			T16	4		T65	2		T32	1
valid_sources[0x4d]	983	1			T2	1		T11	1		T16	1
valid_sources[0x4e]	905	1			T51	1		T11	1		T16	2
valid_sources[0x4f]	1018	1			T23	1		T11	4		T16	3
valid_sources[0x50]	1085	1			T23	2		T11	3		T16	6
valid_sources[0x51]	1374	1			T54	1		T64	1		T32	4
valid_sources[0x52]	1523	1			T11	5		T16	7		T65	2
valid_sources[0x53]	1039	1			T11	9		T16	9		T54	1
valid_sources[0x54]	909	1			T14	1		T51	1		T11	7
valid_sources[0x55]	1179	1			T23	1		T16	6		T65	1
valid_sources[0x56]	891	1			T11	1		T16	2		T64	1
valid_sources[0x57]	1017	1			T11	5		T16	4		T141	1
valid_sources[0x58]	870	1			T23	1		T51	1		T11	3
valid_sources[0x59]	1209	1			T51	1		T11	3		T16	1
valid_sources[0x5a]	981	1			T9	8		T11	4		T16	3
valid_sources[0x5b]	1923	1			T15	2		T16	6		T32	2
valid_sources[0x5c]	995	1			T51	1		T16	2		T54	2
valid_sources[0x5d]	1022	1			T5	17		T51	2		T11	2
valid_sources[0x5e]	1166	1			T15	1		T10	199		T16	2
valid_sources[0x5f]	914	1			T51	2		T11	7		T16	2
valid_sources[0x60]	1029	1			T51	1		T16	1		T54	1
valid_sources[0x61]	1054	1			T16	2		T32	5		T21	3
valid_sources[0x62]	935	1			T51	1		T16	4		T20	3
valid_sources[0x63]	921	1			T15	1		T51	1		T16	4
valid_sources[0x64]	846	1			T9	7		T16	8		T29	1
valid_sources[0x65]	1063	1			T51	1		T16	2		T20	1
valid_sources[0x66]	1092	1			T11	5		T16	7		T20	5
valid_sources[0x67]	1090	1			T51	1		T11	14		T16	6
valid_sources[0x68]	1065	1			T51	1		T16	1		T54	4
valid_sources[0x69]	1388	1			T51	2		T11	3		T16	4
valid_sources[0x6a]	1433	1			T9	452		T11	2		T16	5
valid_sources[0x6b]	998	1			T11	15		T16	7		T54	1
valid_sources[0x6c]	1311	1			T51	1		T16	1		T54	1
valid_sources[0x6d]	967	1			T16	4		T54	1		T56	1
valid_sources[0x6e]	908	1			T11	8		T16	1		T65	1
valid_sources[0x6f]	1031	1			T2	1		T23	1		T11	4
valid_sources[0x70]	1140	1			T23	1		T51	1		T11	2
valid_sources[0x71]	1073	1			T11	1		T16	4		T20	1
valid_sources[0x72]	867	1			T11	1		T16	5		T32	6
valid_sources[0x73]	934	1			T16	6		T20	2		T54	1
valid_sources[0x74]	1036	1			T11	9		T16	5		T54	1
valid_sources[0x75]	886	1			T51	1		T11	7		T16	2
valid_sources[0x76]	1152	1			T9	7		T51	2		T11	1
valid_sources[0x77]	1080	1			T51	1		T11	2		T16	1
valid_sources[0x78]	889	1			T11	6		T16	3		T32	1
valid_sources[0x79]	1696	1			T2	1		T23	1		T16	2
valid_sources[0x7a]	912	1			T51	1		T11	1		T16	1
valid_sources[0x7b]	845	1			T9	4		T51	2		T16	3
valid_sources[0x7c]	840	1			T51	1		T11	5		T16	4
valid_sources[0x7d]	893	1			T23	1		T11	3		T16	2
valid_sources[0x7e]	1097	1			T23	1		T51	1		T11	4
valid_sources[0x7f]	1550	1			T11	5		T16	1		T32	3
valid_sources[0x80]	1022	1			T11	13		T16	2		T32	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67236

1

T4

14

T1

4

T2

3

values[0x0]

all_enables

biggest_size

32967

1

T1

3

T2

1

T12

2

values[0x1]

all_enables

biggest_size

23391

1

T4

3

T3

7

T15

2