Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T15,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T7,T9
1	0	Covered	T4,T2,T3
1	1	Covered	T15,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T7,T9
0	1	Covered	T114,T119
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T9,T42
0	1	Covered	T15,T9,T42
1	0	Covered	T7

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T7,T9
1	-	Covered	T15,T9,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T7,T9
DetectSt	168	Covered	T15,T7,T9
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T15,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T7,T9
DebounceSt->IdleSt	163	Covered	T42,T34,T102
DetectSt->IdleSt	186	Covered	T114,T119
DetectSt->StableSt	191	Covered	T15,T7,T9
IdleSt->DebounceSt	148	Covered	T15,T7,T9
StableSt->IdleSt	206	Covered	T15,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T7,T9
0	1	Covered	T15,T7,T9
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T7,T9
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T102,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T114,T119
DetectSt	-	-	-	-	0	1	-	Covered	T15,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T15,T9,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	342	0	0
CntIncr_A	7587864	195715	0	0
CntNoWrap_A	7587864	6915930	0	0
DetectStDropOut_A	7587864	2	0	0
DetectedOut_A	7587864	1047	0	0
DetectedPulseOut_A	7587864	155	0	0
DisabledIdleSt_A	7587864	6712431	0	0
DisabledNoDetection_A	7587864	6714792	0	0
EnterDebounceSt_A	7587864	188	0	0
EnterDetectSt_A	7587864	157	0	0
EnterStableSt_A	7587864	155	0	0
PulseIsPulse_A	7587864	155	0	0
StayInStableSt	7587864	892	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	7177	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	154	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	342	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	2	0	0
T8	934	0	0	0
T9	25421	4	0	0
T10	1907	0	0	0
T15	631	2	0	0
T23	524	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T42	0	5	0	0
T45	0	6	0	0
T48	0	4	0	0
T49	0	4	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	195715	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	16	0	0
T8	934	0	0	0
T9	25421	99	0	0
T10	1907	0	0	0
T15	631	68	0	0
T23	524	0	0	0
T34	0	30	0	0
T36	0	92	0	0
T42	0	128	0	0
T45	0	149	0	0
T48	0	66	0	0
T49	0	124	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	121	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6915930	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	228	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	2	0	0
T73	4434	0	0	0
T114	11277	1	0	0
T119	0	1	0	0
T120	8722	0	0	0
T121	14578	0	0	0
T122	678	0	0	0
T123	30636	0	0	0
T124	494	0	0	0
T125	402	0	0	0
T126	521	0	0	0
T127	572	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1047	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	12	0	0
T10	1907	0	0	0
T15	631	11	0	0
T23	524	0	0	0
T36	0	12	0	0
T42	0	5	0	0
T45	0	22	0	0
T48	0	13	0	0
T49	0	18	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	5	0	0
T128	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	155	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	2	0	0
T10	1907	0	0	0
T15	631	1	0	0
T23	524	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T45	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	1	0	0
T128	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6712431	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6714792	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	188	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	2	0	0
T10	1907	0	0	0
T15	631	1	0	0
T23	524	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	0	3	0	0
T45	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	157	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	2	0	0
T10	1907	0	0	0
T15	631	1	0	0
T23	524	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T45	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	1	0	0
T128	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	155	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	2	0	0
T10	1907	0	0	0
T15	631	1	0	0
T23	524	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T45	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	1	0	0
T128	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	155	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	2	0	0
T10	1907	0	0	0
T15	631	1	0	0
T23	524	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T45	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T102	0	1	0	0
T128	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	892	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T8	934	0	0	0
T9	25421	10	0	0
T10	1907	0	0	0
T15	631	10	0	0
T23	524	0	0	0
T36	0	11	0	0
T42	0	3	0	0
T45	0	19	0	0
T48	0	11	0	0
T49	0	16	0	0
T50	1055	0	0	0
T51	501	0	0	0
T98	0	22	0	0
T102	0	4	0	0
T128	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	7177	0	0
T1	54432	0	0	0
T2	578	1	0	0
T3	1539	4	0	0
T4	852	4	0	0
T5	733	1	0	0
T6	986	2	0	0
T7	0	36	0	0
T12	721	0	0	0
T13	500	1	0	0
T14	730	2	0	0
T15	631	3	0	0
T50	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	154	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T8	934	0	0	0
T9	25421	2	0	0
T10	1907	0	0	0
T15	631	1	0	0
T23	524	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T45	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T98	0	3	0	0
T102	0	1	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T7,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T7,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T20,T29,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T20
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T7,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T29,T53
0	1	Covered	T53,T100,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T29,T53
0	1	Unreachable
1	0	Covered	T20,T29,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T20
DetectSt	168	Covered	T20,T29,T53
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T20,T29,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T29,T53
DebounceSt->IdleSt	163	Covered	T4,T7,T28
DetectSt->IdleSt	186	Covered	T53,T100,T101
DetectSt->StableSt	191	Covered	T20,T29,T53
IdleSt->DebounceSt	148	Covered	T4,T7,T20
StableSt->IdleSt	206	Covered	T20,T29,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T20
0	1	Covered	T4,T7,T20
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T29,T53
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T7,T34
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T29,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T28,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T20
DetectSt	-	-	-	-	1	-	-	Covered	T53,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T20,T29,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T29,T53
StableSt	-	-	-	-	-	-	0	Covered	T20,T29,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	172	0	0
CntIncr_A	7587864	97457	0	0
CntNoWrap_A	7587864	6916100	0	0
DetectStDropOut_A	7587864	17	0	0
DetectedOut_A	7587864	281170	0	0
DetectedPulseOut_A	7587864	43	0	0
DisabledIdleSt_A	7587864	5507667	0	0
DisabledNoDetection_A	7587864	5510093	0	0
EnterDebounceSt_A	7587864	114	0	0
EnterDetectSt_A	7587864	60	0	0
EnterStableSt_A	7587864	43	0	0
PulseIsPulse_A	7587864	43	0	0
StayInStableSt	7587864	281127	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	7177	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_sticky_sva.StableStDropOut_A	7587864	726463	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	172	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	1	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	2	0	0
T28	0	3	0	0
T29	0	4	0	0
T34	0	1	0	0
T45	0	1	0	0
T53	0	11	0	0
T67	0	2	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	97457	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	31	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	23	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	74	0	0
T28	0	297	0	0
T29	0	56	0	0
T34	0	15	0	0
T45	0	35	0	0
T53	0	426	0	0
T67	0	62	0	0
T68	0	118	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916100	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	450	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	17	0	0
T21	491	0	0	0
T22	493	0	0	0
T32	13031	0	0	0
T39	705	0	0	0
T41	30185	0	0	0
T42	652	0	0	0
T53	1324	4	0	0
T64	523	0	0	0
T65	504	0	0	0
T77	0	2	0	0
T86	402	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	281170	0	0
T20	2296	252	0	0
T28	1740	0	0	0
T29	0	39	0	0
T53	0	144	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	11	0	0
T135	0	470	0	0
T136	0	160	0	0
T137	0	412	0	0
T138	0	16	0	0
T139	0	489	0	0
T140	0	359	0	0
T141	416	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	43	0	0
T20	2296	1	0	0
T28	1740	0	0	0
T29	0	2	0	0
T53	0	1	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	416	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5507667	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	341	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5510093	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	342	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	114	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	1	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	1	0	0
T28	0	3	0	0
T29	0	2	0	0
T34	0	2	0	0
T45	0	1	0	0
T53	0	6	0	0
T67	0	2	0	0
T68	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	60	0	0
T20	2296	1	0	0
T28	1740	0	0	0
T29	0	2	0	0
T53	0	5	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	416	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	43	0	0
T20	2296	1	0	0
T28	1740	0	0	0
T29	0	2	0	0
T53	0	1	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	416	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	43	0	0
T20	2296	1	0	0
T28	1740	0	0	0
T29	0	2	0	0
T53	0	1	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	416	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	281127	0	0
T20	2296	251	0	0
T28	1740	0	0	0
T29	0	37	0	0
T53	0	143	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	10	0	0
T135	0	469	0	0
T136	0	158	0	0
T137	0	411	0	0
T138	0	15	0	0
T139	0	488	0	0
T140	0	358	0	0
T141	416	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	7177	0	0
T1	54432	0	0	0
T2	578	1	0	0
T3	1539	4	0	0
T4	852	4	0	0
T5	733	1	0	0
T6	986	2	0	0
T7	0	36	0	0
T12	721	0	0	0
T13	500	1	0	0
T14	730	2	0	0
T15	631	3	0	0
T50	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	726463	0	0
T20	2296	93	0	0
T28	1740	0	0	0
T29	0	345	0	0
T53	0	77	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	28627	0	0
T135	0	104	0	0
T136	0	56	0	0
T137	0	304	0	0
T138	0	35	0	0
T139	0	118	0	0
T140	0	219	0	0
T141	416	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T7,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T7,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T28,T29,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T20
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T7,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T53
0	1	Covered	T53,T98,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T53
0	1	Unreachable
1	0	Covered	T28,T29,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T20
DetectSt	168	Covered	T28,T29,T53
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T28,T29,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T29,T53
DebounceSt->IdleSt	163	Covered	T4,T7,T20
DetectSt->IdleSt	186	Covered	T53,T98,T99
DetectSt->StableSt	191	Covered	T28,T29,T53
IdleSt->DebounceSt	148	Covered	T4,T7,T20
StableSt->IdleSt	206	Covered	T28,T29,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T20
0	1	Covered	T4,T7,T20
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T53
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T7,T34
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T29,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T20,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T20
DetectSt	-	-	-	-	1	-	-	Covered	T53,T98,T99
DetectSt	-	-	-	-	0	1	-	Covered	T28,T29,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T29,T53
StableSt	-	-	-	-	-	-	0	Covered	T28,T29,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	172	0	0
CntIncr_A	7587864	47534	0	0
CntNoWrap_A	7587864	6916100	0	0
DetectStDropOut_A	7587864	17	0	0
DetectedOut_A	7587864	190423	0	0
DetectedPulseOut_A	7587864	43	0	0
DisabledIdleSt_A	7587864	5507667	0	0
DisabledNoDetection_A	7587864	5510093	0	0
EnterDebounceSt_A	7587864	114	0	0
EnterDetectSt_A	7587864	60	0	0
EnterStableSt_A	7587864	43	0	0
PulseIsPulse_A	7587864	43	0	0
StayInStableSt	7587864	190380	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_sticky_sva.StableStDropOut_A	7587864	654827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	172	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	1	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	4	0	0
T28	0	2	0	0
T29	0	4	0	0
T34	0	1	0	0
T45	0	2	0	0
T53	0	8	0	0
T67	0	2	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	47534	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	74	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	23	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	252	0	0
T28	0	31	0	0
T29	0	130	0	0
T34	0	15	0	0
T45	0	5217	0	0
T53	0	232	0	0
T67	0	176	0	0
T68	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916100	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	450	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	17	0	0
T21	491	0	0	0
T22	493	0	0	0
T32	13031	0	0	0
T39	705	0	0	0
T41	30185	0	0	0
T42	652	0	0	0
T53	1324	3	0	0
T64	523	0	0	0
T65	504	0	0	0
T77	0	2	0	0
T86	402	0	0	0
T98	0	1	0	0
T99	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	190423	0	0
T28	1740	113	0	0
T29	1658	224	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	6017	0	0
T53	1324	238	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	85	0	0
T97	0	49	0	0
T129	422	0	0	0
T135	0	379	0	0
T136	0	94	0	0
T138	0	39	0	0
T139	0	255	0	0
T142	451	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	43	0	0
T28	1740	1	0	0
T29	1658	2	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	1	0	0
T53	1324	1	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T129	422	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T142	451	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5507667	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	341	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5510093	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	342	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	114	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	1	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	4	0	0
T28	0	1	0	0
T29	0	2	0	0
T34	0	2	0	0
T45	0	1	0	0
T53	0	4	0	0
T67	0	2	0	0
T68	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	60	0	0
T28	1740	1	0	0
T29	1658	2	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	1	0	0
T53	1324	4	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T129	422	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	1	0	0
T142	451	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	43	0	0
T28	1740	1	0	0
T29	1658	2	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	1	0	0
T53	1324	1	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T129	422	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T142	451	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	43	0	0
T28	1740	1	0	0
T29	1658	2	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	1	0	0
T53	1324	1	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T129	422	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T142	451	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	190380	0	0
T28	1740	112	0	0
T29	1658	222	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	6016	0	0
T53	1324	237	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	84	0	0
T97	0	47	0	0
T129	422	0	0	0
T135	0	378	0	0
T136	0	92	0	0
T138	0	38	0	0
T139	0	254	0	0
T142	451	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	654827	0	0
T28	1740	198	0	0
T29	1658	89	0	0
T32	13031	0	0	0
T33	236553	0	0	0
T39	705	0	0	0
T45	0	120	0	0
T53	1324	200	0	0
T64	523	0	0	0
T65	504	0	0	0
T96	0	57	0	0
T97	0	70199	0	0
T129	422	0	0	0
T135	0	190	0	0
T136	0	175	0	0
T138	0	30	0	0
T139	0	334	0	0
T142	451	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T7,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T7,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T20,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T20
1	0	Covered	T4,T1,T3
1	1	Covered	T4,T7,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T28,T29
0	1	Covered	T68,T96,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T28,T29
0	1	Unreachable
1	0	Covered	T20,T28,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T20
DetectSt	168	Covered	T20,T28,T29
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T20,T28,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T28,T29
DebounceSt->IdleSt	163	Covered	T4,T7,T34
DetectSt->IdleSt	186	Covered	T68,T96,T97
DetectSt->StableSt	191	Covered	T20,T28,T29
IdleSt->DebounceSt	148	Covered	T4,T7,T20
StableSt->IdleSt	206	Covered	T20,T28,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T20
0	1	Covered	T4,T7,T20
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T28,T29
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T7,T34
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T67,T139
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T20
DetectSt	-	-	-	-	1	-	-	Covered	T68,T96,T97
DetectSt	-	-	-	-	0	1	-	Covered	T20,T28,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T28,T29
StableSt	-	-	-	-	-	-	0	Covered	T20,T28,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	181	0	0
CntIncr_A	7587864	601363	0	0
CntNoWrap_A	7587864	6916091	0	0
DetectStDropOut_A	7587864	21	0	0
DetectedOut_A	7587864	206745	0	0
DetectedPulseOut_A	7587864	40	0	0
DisabledIdleSt_A	7587864	5507667	0	0
DisabledNoDetection_A	7587864	5510093	0	0
EnterDebounceSt_A	7587864	122	0	0
EnterDetectSt_A	7587864	61	0	0
EnterStableSt_A	7587864	40	0	0
PulseIsPulse_A	7587864	40	0	0
StayInStableSt	7587864	206705	0	0
gen_high_event_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_sticky_sva.StableStDropOut_A	7587864	382204	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	181	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	1	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	2	0	0
T28	0	2	0	0
T29	0	4	0	0
T34	0	1	0	0
T45	0	2	0	0
T53	0	4	0	0
T67	0	2	0	0
T68	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	601363	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	91	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	23	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	38	0	0
T28	0	50	0	0
T29	0	176	0	0
T34	0	15	0	0
T45	0	80	0	0
T53	0	68	0	0
T67	0	192	0	0
T68	0	190	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916091	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	450	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	21	0	0
T49	53255	0	0	0
T61	492	0	0	0
T68	1422	2	0	0
T72	4402	0	0	0
T96	2267	1	0	0
T97	0	4	0	0
T133	0	2	0	0
T135	1073	0	0	0
T145	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	527	0	0	0
T157	408	0	0	0
T158	21204	0	0	0
T159	470	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	206745	0	0
T20	2296	247	0	0
T28	1740	191	0	0
T29	0	221	0	0
T45	0	145	0	0
T53	0	272	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	328	0	0
T136	0	150	0	0
T137	0	565	0	0
T138	0	17	0	0
T141	416	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	40	0	0
T20	2296	1	0	0
T28	1740	1	0	0
T29	0	2	0	0
T45	0	1	0	0
T53	0	2	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T141	416	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5507667	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	341	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5510093	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	342	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	122	0	0
T1	54432	0	0	0
T2	578	0	0	0
T3	1539	0	0	0
T4	852	1	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T20	0	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T34	0	2	0	0
T45	0	1	0	0
T53	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	61	0	0
T20	2296	1	0	0
T28	1740	1	0	0
T29	0	2	0	0
T45	0	1	0	0
T53	0	2	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T68	0	2	0	0
T84	404	0	0	0
T85	409	0	0	0
T96	0	1	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T141	416	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	40	0	0
T20	2296	1	0	0
T28	1740	1	0	0
T29	0	2	0	0
T45	0	1	0	0
T53	0	2	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T141	416	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	40	0	0
T20	2296	1	0	0
T28	1740	1	0	0
T29	0	2	0	0
T45	0	1	0	0
T53	0	2	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T141	416	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	206705	0	0
T20	2296	246	0	0
T28	1740	190	0	0
T29	0	219	0	0
T45	0	144	0	0
T53	0	270	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T135	0	327	0	0
T136	0	148	0	0
T137	0	564	0	0
T138	0	16	0	0
T141	416	0	0	0
T160	0	55	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	382204	0	0
T20	2296	146	0	0
T28	1740	115	0	0
T29	0	65	0	0
T45	0	11130	0	0
T53	0	432	0	0
T54	508	0	0	0
T55	593	0	0	0
T56	551	0	0	0
T57	869	0	0	0
T63	507	0	0	0
T84	404	0	0	0
T85	409	0	0	0
T98	0	26	0	0
T135	0	254	0	0
T136	0	153	0	0
T137	0	364	0	0
T138	0	52	0	0
T141	416	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T8,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T7,T8,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T8,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T7,T8,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T39,T34
0	1	Covered	T8
1	0	Covered	T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T39,T34
0	1	Covered	T130,T134,T161
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T39,T34
1	-	Covered	T130,T134,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T33
DetectSt	168	Covered	T7,T8,T33
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T33,T39,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T33
DebounceSt->IdleSt	163	Covered	T106
DetectSt->IdleSt	186	Covered	T7,T8
DetectSt->StableSt	191	Covered	T33,T39,T34
IdleSt->DebounceSt	148	Covered	T7,T8,T33
StableSt->IdleSt	206	Covered	T34,T162,T92

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T33
0	1	Covered	T7,T8,T33
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T33
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T106
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T33
DetectSt	-	-	-	-	1	-	-	Covered	T7,T8
DetectSt	-	-	-	-	0	1	-	Covered	T33,T39,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T130,T134
StableSt	-	-	-	-	-	-	0	Covered	T33,T39,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	59	0	0
CntIncr_A	7587864	33013	0	0
CntNoWrap_A	7587864	6916213	0	0
DetectStDropOut_A	7587864	1	0	0
DetectedOut_A	7587864	34360	0	0
DetectedPulseOut_A	7587864	27	0	0
DisabledIdleSt_A	7587864	6502907	0	0
DisabledNoDetection_A	7587864	6505288	0	0
EnterDebounceSt_A	7587864	30	0	0
EnterDetectSt_A	7587864	29	0	0
EnterStableSt_A	7587864	27	0	0
PulseIsPulse_A	7587864	27	0	0
StayInStableSt	7587864	34316	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	59	0	0
T7	6427	2	0	0
T8	934	2	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	2	0	0
T93	0	2	0	0
T106	0	1	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	33013	0	0
T7	6427	23	0	0
T8	934	74	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	31573	0	0
T34	0	26	0	0
T39	0	45	0	0
T40	0	20	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	98	0	0
T93	0	45	0	0
T106	0	56	0	0
T162	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916213	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1	0	0
T8	934	1	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T20	2296	0	0	0
T23	524	0	0	0
T30	40559	0	0	0
T51	501	0	0	0
T52	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34360	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	31629	0	0
T34	0	11	0	0
T39	705	41	0	0
T40	0	41	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T92	0	217	0	0
T93	0	88	0	0
T129	422	0	0	0
T130	0	172	0	0
T134	0	80	0	0
T162	0	214	0	0
T163	0	430	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	27	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	1	0	0
T34	0	1	0	0
T39	705	1	0	0
T40	0	1	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T129	422	0	0	0
T130	0	2	0	0
T134	0	2	0	0
T162	0	1	0	0
T163	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6502907	0	0
T1	54432	54031	0	0
T2	578	4	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6505288	0	0
T1	54432	54032	0	0
T2	578	4	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	30	0	0
T7	6427	1	0	0
T8	934	1	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T106	0	1	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	29	0	0
T7	6427	1	0	0
T8	934	1	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T130	0	2	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	27	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	1	0	0
T34	0	1	0	0
T39	705	1	0	0
T40	0	1	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T129	422	0	0	0
T130	0	2	0	0
T134	0	2	0	0
T162	0	1	0	0
T163	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	27	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	1	0	0
T34	0	1	0	0
T39	705	1	0	0
T40	0	1	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T129	422	0	0	0
T130	0	2	0	0
T134	0	2	0	0
T162	0	1	0	0
T163	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34316	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	31627	0	0
T34	0	10	0	0
T39	705	39	0	0
T40	0	39	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T92	0	215	0	0
T93	0	86	0	0
T129	422	0	0	0
T130	0	169	0	0
T134	0	78	0	0
T162	0	212	0	0
T163	0	426	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	9	0	0
T119	593	0	0	0
T130	14972	1	0	0
T131	6312	0	0	0
T132	17821	0	0	0
T133	220208	0	0	0
T134	777	2	0	0
T161	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	506	0	0	0
T170	603	0	0	0
T171	5470	0	0	0
T172	36313	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T6,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T34
0	1	Covered	T114
1	0	Covered	T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T34
0	1	Covered	T6,T8,T38
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T34
1	-	Covered	T6,T8,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T8
DetectSt	168	Covered	T6,T7,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T8,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T8
DebounceSt->IdleSt	163	Covered	T59,T173,T127
DetectSt->IdleSt	186	Covered	T7,T114
DetectSt->StableSt	191	Covered	T6,T8,T34
IdleSt->DebounceSt	148	Covered	T6,T7,T8
StableSt->IdleSt	206	Covered	T6,T8,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T173,T127,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T7,T114
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T34
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	114	0	0
CntIncr_A	7587864	189992	0	0
CntNoWrap_A	7587864	6916158	0	0
DetectStDropOut_A	7587864	1	0	0
DetectedOut_A	7587864	93592	0	0
DetectedPulseOut_A	7587864	53	0	0
DisabledIdleSt_A	7587864	6379789	0	0
DisabledNoDetection_A	7587864	6382166	0	0
EnterDebounceSt_A	7587864	60	0	0
EnterDetectSt_A	7587864	55	0	0
EnterStableSt_A	7587864	53	0	0
PulseIsPulse_A	7587864	53	0	0
StayInStableSt	7587864	93521	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	2667	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	114	0	0
T6	986	4	0	0
T7	6427	2	0	0
T8	934	4	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	2	0	0
T38	0	6	0	0
T40	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T96	0	4	0	0
T175	0	4	0	0
T176	0	4	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	189992	0	0
T6	986	132	0	0
T7	6427	23	0	0
T8	934	148	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	26	0	0
T38	0	144	0	0
T40	0	20	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T59	0	2328	0	0
T96	0	152	0	0
T175	0	132	0	0
T176	0	108	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916158	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	581	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1	0	0
T73	4434	0	0	0
T114	11277	1	0	0
T120	8722	0	0	0
T121	14578	0	0	0
T122	678	0	0	0
T123	30636	0	0	0
T124	494	0	0	0
T125	402	0	0	0
T126	521	0	0	0
T127	572	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	93592	0	0
T6	986	45	0	0
T7	6427	0	0	0
T8	934	300	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	10	0	0
T38	0	219	0	0
T40	0	105	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	141	0	0
T96	0	189	0	0
T175	0	174	0	0
T176	0	225	0	0
T177	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	53	0	0
T6	986	2	0	0
T7	6427	0	0	0
T8	934	2	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	1	0	0
T96	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6379789	0	0
T1	54432	54031	0	0
T2	578	4	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	3	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6382166	0	0
T1	54432	54032	0	0
T2	578	4	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	3	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	60	0	0
T6	986	2	0	0
T7	6427	1	0	0
T8	934	2	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T59	0	1	0	0
T96	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	55	0	0
T6	986	2	0	0
T7	6427	1	0	0
T8	934	2	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T96	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	53	0	0
T6	986	2	0	0
T7	6427	0	0	0
T8	934	2	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	1	0	0
T96	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	53	0	0
T6	986	2	0	0
T7	6427	0	0	0
T8	934	2	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	1	0	0
T96	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	93521	0	0
T6	986	43	0	0
T7	6427	0	0	0
T8	934	297	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T34	0	9	0	0
T38	0	215	0	0
T40	0	104	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	140	0	0
T96	0	186	0	0
T175	0	172	0	0
T176	0	222	0	0
T177	0	50	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	2667	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	4	0	0
T5	733	1	0	0
T6	986	2	0	0
T7	6427	3	0	0
T8	0	2	0	0
T9	0	41	0	0
T10	0	15	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T23	0	6	0	0
T51	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34	0	0
T6	986	2	0	0
T7	6427	0	0	0
T8	934	1	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T92	0	1	0	0
T96	0	1	0	0
T114	0	4	0	0
T175	0	2	0	0
T176	0	1	0	0
T178	0	1	0	0