Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T6,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T33
0	1	Covered	T33,T39,T38
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T9
1	-	Covered	T33,T39,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T9
DetectSt	168	Covered	T6,T7,T9
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T9
DebounceSt->IdleSt	163	Covered	T96
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T7,T9
IdleSt->DebounceSt	148	Covered	T6,T7,T9
StableSt->IdleSt	206	Covered	T7,T9,T33

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T9
0	1	Covered	T6,T7,T9
0	0	Excluded	T4,T1,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T9
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T96
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T33,T39
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	83	0	0
CntIncr_A	7587864	65596	0	0
CntNoWrap_A	7587864	6916189	0	0
DetectStDropOut_A	7587864	0	0	0
DetectedOut_A	7587864	84914	0	0
DetectedPulseOut_A	7587864	41	0	0
DisabledIdleSt_A	7587864	6386644	0	0
DisabledNoDetection_A	7587864	6389022	0	0
EnterDebounceSt_A	7587864	42	0	0
EnterDetectSt_A	7587864	41	0	0
EnterStableSt_A	7587864	41	0	0
PulseIsPulse_A	7587864	41	0	0
StayInStableSt	7587864	84849	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	15	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7587864	83
T6	986	2
T7	6427	2
T8	934	0
T9	25421	2
T10	1907	0
T11	9821	0
T23	524	0
T33	0	4
T34	0	2
T36	0	2
T38	0	2
T39	0	4
T40	0	2
T50	1055	0
T51	501	0
T52	422	0
T96	0	1

CntIncr_A

Name	Attempts	Real Successes
Total	7587864	65596
T6	986	66
T7	6427	23
T8	934	0
T9	25421	44
T10	1907	0
T11	9821	0
T23	524	0
T33	0	63146
T34	0	26
T36	0	89
T38	0	48
T39	0	90
T40	0	20
T50	1055	0
T51	501	0
T52	422	0
T96	0	76

CntNoWrap_A

Name	Attempts	Real Successes
Total	7587864	6916189
T1	54432	54031
T2	578	177
T3	1539	337
T4	852	451
T5	733	332
T6	986	583
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7587864	84914
T6	986	269
T7	6427	1
T8	934	0
T9	25421	53
T10	1907	0
T11	9821	0
T23	524	0
T33	0	81636
T34	0	11
T36	0	41
T38	0	129
T39	0	82
T40	0	42
T50	1055	0
T51	501	0
T52	422	0
T179	0	43

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7587864	41
T6	986	1
T7	6427	1
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T36	0	1
T38	0	1
T39	0	2
T40	0	1
T50	1055	0
T51	501	0
T52	422	0
T179	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7587864	6386644
T1	54432	54031
T2	578	177
T3	1539	127
T4	852	451
T5	733	4
T6	986	3
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7587864	6389022
T1	54432	54032
T2	578	178
T3	1539	128
T4	852	452
T5	733	4
T6	986	3
T12	721	321
T13	500	100
T14	730	330
T15	631	231

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7587864	42
T6	986	1
T7	6427	1
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T36	0	1
T38	0	1
T39	0	2
T40	0	1
T50	1055	0
T51	501	0
T52	422	0
T96	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7587864	41
T6	986	1
T7	6427	1
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T36	0	1
T38	0	1
T39	0	2
T40	0	1
T50	1055	0
T51	501	0
T52	422	0
T179	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7587864	41
T6	986	1
T7	6427	1
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T36	0	1
T38	0	1
T39	0	2
T40	0	1
T50	1055	0
T51	501	0
T52	422	0
T179	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7587864	41
T6	986	1
T7	6427	1
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T36	0	1
T38	0	1
T39	0	2
T40	0	1
T50	1055	0
T51	501	0
T52	422	0
T179	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7587864	84849
T6	986	267
T7	6427	0
T8	934	0
T9	25421	51
T10	1907	0
T11	9821	0
T23	524	0
T33	0	81633
T34	0	10
T36	0	39
T38	0	128
T39	0	79
T40	0	40
T50	1055	0
T51	501	0
T52	422	0
T179	0	42
T180	0	40

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7587864	6918701
T1	54432	54032
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7587864	15
T21	491	0
T29	1658	0
T32	13031	0
T33	236553	1
T38	0	1
T39	705	1
T53	1324	0
T64	523	0
T65	504	0
T86	402	0
T92	0	1
T129	422	0
T179	0	1
T181	0	1
T182	0	1
T183	0	1
T184	0	2
T185	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T12,T3
1	1	Covered	T2,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T7
0	1	Covered	T92,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T8
0	1	Covered	T8,T33,T38
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T7
1	-	Covered	T8,T33,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T5,T7
DetectSt	168	Covered	T2,T5,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T5,T7
DebounceSt->IdleSt	163	Covered	T187,T188,T174
DetectSt->IdleSt	186	Covered	T92,T186
DetectSt->StableSt	191	Covered	T2,T5,T7
IdleSt->DebounceSt	148	Covered	T2,T5,T7
StableSt->IdleSt	206	Covered	T7,T8,T33

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T5,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T187,T188,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T92,T186
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	134	0	0
CntIncr_A	7587864	215023	0	0
CntNoWrap_A	7587864	6916138	0	0
DetectStDropOut_A	7587864	2	0	0
DetectedOut_A	7587864	150052	0	0
DetectedPulseOut_A	7587864	63	0	0
DisabledIdleSt_A	7587864	6151615	0	0
DisabledNoDetection_A	7587864	6153988	0	0
EnterDebounceSt_A	7587864	69	0	0
EnterDetectSt_A	7587864	65	0	0
EnterStableSt_A	7587864	63	0	0
PulseIsPulse_A	7587864	63	0	0
StayInStableSt	7587864	149959	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	3051	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	31	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7587864	134
T2	578	2
T3	1539	0
T5	733	2
T6	986	0
T7	6427	2
T8	0	4
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	4
T34	0	2
T38	0	4
T40	0	2
T50	1055	0
T187	0	3
T189	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7587864	215023
T2	578	42
T3	1539	0
T5	733	46
T6	986	0
T7	6427	23
T8	0	148
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	63146
T34	0	26
T38	0	96
T40	0	20
T50	1055	0
T187	0	104
T189	0	93

CntNoWrap_A

Name	Attempts	Real Successes
Total	7587864	6916138
T1	54432	54031
T2	578	175
T3	1539	337
T4	852	451
T5	733	330
T6	986	585
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7587864	2
T92	12311	1
T181	843	0
T186	0	1
T190	408	0
T191	493	0
T192	9014	0
T193	503	0
T194	674	0
T195	29168	0
T196	484	0
T197	2290	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7587864	150052
T2	578	127
T3	1539	0
T5	733	278
T6	986	0
T7	6427	1
T8	0	50
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	28212
T34	0	12
T38	0	244
T40	0	6
T50	1055	0
T187	0	42
T189	0	61

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7587864	63
T2	578	1
T3	1539	0
T5	733	1
T6	986	0
T7	6427	1
T8	0	2
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T38	0	2
T40	0	1
T50	1055	0
T187	0	1
T189	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7587864	6151615
T1	54432	54031
T2	578	4
T3	1539	337
T4	852	451
T5	733	4
T6	986	585
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7587864	6153988
T1	54432	54032
T2	578	4
T3	1539	339
T4	852	452
T5	733	4
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7587864	69
T2	578	1
T3	1539	0
T5	733	1
T6	986	0
T7	6427	1
T8	0	2
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T38	0	2
T40	0	1
T50	1055	0
T187	0	2
T189	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7587864	65
T2	578	1
T3	1539	0
T5	733	1
T6	986	0
T7	6427	1
T8	0	2
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T38	0	2
T40	0	1
T50	1055	0
T187	0	1
T189	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7587864	63
T2	578	1
T3	1539	0
T5	733	1
T6	986	0
T7	6427	1
T8	0	2
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T38	0	2
T40	0	1
T50	1055	0
T187	0	1
T189	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7587864	63
T2	578	1
T3	1539	0
T5	733	1
T6	986	0
T7	6427	1
T8	0	2
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T38	0	2
T40	0	1
T50	1055	0
T187	0	1
T189	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7587864	149959
T2	578	125
T3	1539	0
T5	733	276
T6	986	0
T7	6427	0
T8	0	47
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	28210
T34	0	11
T38	0	241
T40	0	5
T50	1055	0
T176	0	166
T187	0	40
T189	0	59

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7587864	3051
T1	54432	1
T2	578	1
T3	1539	5
T5	733	1
T6	986	1
T7	6427	7
T8	0	2
T9	0	58
T12	721	3
T13	500	0
T14	730	0
T15	631	0
T23	0	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7587864	6918701
T1	54432	54032
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7587864	31
T8	934	1
T9	25421	0
T10	1907	0
T11	9821	0
T16	13422	0
T20	2296	0
T23	524	0
T30	40559	0
T33	0	2
T38	0	1
T40	0	1
T51	501	0
T52	422	0
T93	0	1
T114	0	2
T176	0	1
T177	0	2
T178	0	1
T180	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T3
1	1	Covered	T4,T1,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T4,T3,T13
1	1	Covered	T1,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T33
0	1	Covered	T122,T133
1	0	Covered	T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T33
0	1	Covered	T6,T33,T37
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T33
1	-	Covered	T6,T33,T37

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T7
DetectSt	168	Covered	T1,T6,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T6,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T7
DebounceSt->IdleSt	163	Covered	T162,T92,T161
DetectSt->IdleSt	186	Covered	T7,T122,T133
DetectSt->StableSt	191	Covered	T1,T6,T33
IdleSt->DebounceSt	148	Covered	T1,T6,T7
StableSt->IdleSt	206	Covered	T6,T33,T34

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T162,T161,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T122,T133
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T33,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	134	0	0
CntIncr_A	7587864	198709	0	0
CntNoWrap_A	7587864	6916138	0	0
DetectStDropOut_A	7587864	2	0	0
DetectedOut_A	7587864	102704	0	0
DetectedPulseOut_A	7587864	62	0	0
DisabledIdleSt_A	7587864	6097174	0	0
DisabledNoDetection_A	7587864	6099552	0	0
EnterDebounceSt_A	7587864	70	0	0
EnterDetectSt_A	7587864	65	0	0
EnterStableSt_A	7587864	62	0	0
PulseIsPulse_A	7587864	62	0	0
StayInStableSt	7587864	102615	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	34	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7587864	134
T1	54432	2
T2	578	0
T3	1539	0
T5	733	0
T6	986	2
T7	6427	2
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	4
T34	0	2
T37	0	4
T106	0	4
T162	0	1
T176	0	6
T199	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7587864	198709
T1	54432	26987
T2	578	0
T3	1539	0
T5	733	0
T6	986	66
T7	6427	23
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	63146
T34	0	26
T37	0	38
T106	0	112
T162	0	99
T176	0	162
T199	0	75

CntNoWrap_A

Name	Attempts	Real Successes
Total	7587864	6916138
T1	54432	54029
T2	578	177
T3	1539	337
T4	852	451
T5	733	332
T6	986	583
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7587864	2
T73	4434	0
T122	678	1
T123	30636	0
T124	494	0
T125	402	0
T126	521	0
T127	572	0
T133	0	1
T200	422	0
T201	443	0
T202	692	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7587864	102704
T1	54432	27035
T2	578	0
T3	1539	0
T5	733	0
T6	986	108
T7	6427	0
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	59802
T34	0	11
T37	0	177
T92	0	471
T106	0	108
T176	0	195
T199	0	188
T203	0	268

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7587864	62
T1	54432	1
T2	578	0
T3	1539	0
T5	733	0
T6	986	1
T7	6427	0
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T37	0	2
T92	0	2
T106	0	2
T176	0	3
T199	0	1
T203	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7587864	6097174
T1	54432	3
T2	578	177
T3	1539	337
T4	852	451
T5	733	332
T6	986	3
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7587864	6099552
T1	54432	3
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	3
T12	721	321
T13	500	100
T14	730	330
T15	631	231

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7587864	70
T1	54432	1
T2	578	0
T3	1539	0
T5	733	0
T6	986	1
T7	6427	1
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T37	0	2
T106	0	2
T162	0	1
T176	0	3
T199	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7587864	65
T1	54432	1
T2	578	0
T3	1539	0
T5	733	0
T6	986	1
T7	6427	1
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T37	0	2
T106	0	2
T176	0	3
T199	0	1
T203	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7587864	62
T1	54432	1
T2	578	0
T3	1539	0
T5	733	0
T6	986	1
T7	6427	0
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T37	0	2
T92	0	2
T106	0	2
T176	0	3
T199	0	1
T203	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7587864	62
T1	54432	1
T2	578	0
T3	1539	0
T5	733	0
T6	986	1
T7	6427	0
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T37	0	2
T92	0	2
T106	0	2
T176	0	3
T199	0	1
T203	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7587864	102615
T1	54432	27033
T2	578	0
T3	1539	0
T5	733	0
T6	986	107
T7	6427	0
T12	721	0
T13	500	0
T14	730	0
T15	631	0
T33	0	59799
T34	0	10
T37	0	174
T92	0	468
T106	0	106
T176	0	191
T199	0	186
T203	0	267

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7587864	6918701
T1	54432	54032
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7587864	34
T6	986	1
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T37	0	1
T50	1055	0
T51	501	0
T52	422	0
T92	0	1
T106	0	2
T114	0	1
T176	0	2
T183	0	1
T203	0	1
T204	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T3
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T7,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T3,T13
1	1	Covered	T6,T7,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T36
0	1	Not Covered
1	0	Covered	T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T36
0	1	Covered	T37,T162,T122
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T34,T36
1	-	Covered	T37,T162,T122

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T34
DetectSt	168	Covered	T6,T7,T34
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T34,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T34
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T6,T34,T36
IdleSt->DebounceSt	148	Covered	T6,T7,T34
StableSt->IdleSt	206	Covered	T34,T36,T37

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T34
0	1	Covered	T6,T7,T34
0	0	Excluded	T4,T1,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T34
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T34
DetectSt	-	-	-	-	1	-	-	Covered	T7
DetectSt	-	-	-	-	0	1	-	Covered	T6,T34,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T37,T162
StableSt	-	-	-	-	-	-	0	Covered	T6,T34,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	68	0	0
CntIncr_A	7587864	15781	0	0
CntNoWrap_A	7587864	6916204	0	0
DetectStDropOut_A	7587864	0	0	0
DetectedOut_A	7587864	2522	0	0
DetectedPulseOut_A	7587864	33	0	0
DisabledIdleSt_A	7587864	6611216	0	0
DisabledNoDetection_A	7587864	6613601	0	0
EnterDebounceSt_A	7587864	34	0	0
EnterDetectSt_A	7587864	34	0	0
EnterStableSt_A	7587864	33	0	0
PulseIsPulse_A	7587864	33	0	0
StayInStableSt	7587864	2469	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	6728	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	12	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7587864	68
T6	986	2
T7	6427	2
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	2
T36	0	2
T37	0	2
T50	1055	0
T51	501	0
T52	422	0
T114	0	2
T120	0	2
T122	0	2
T162	0	6
T175	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7587864	15781
T6	986	66
T7	6427	23
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	26
T36	0	89
T37	0	19
T50	1055	0
T51	501	0
T52	422	0
T114	0	92
T120	0	26
T122	0	46
T162	0	167
T175	0	66

CntNoWrap_A

Name	Attempts	Real Successes
Total	7587864	6916204
T1	54432	54031
T2	578	177
T3	1539	337
T4	852	451
T5	733	332
T6	986	583
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7587864	2522
T6	986	269
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	11
T36	0	41
T37	0	9
T50	1055	0
T51	501	0
T52	422	0
T114	0	133
T120	0	86
T122	0	42
T127	0	42
T162	0	133
T175	0	40

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7587864	33
T6	986	1
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	1
T36	0	1
T37	0	1
T50	1055	0
T51	501	0
T52	422	0
T114	0	1
T120	0	1
T122	0	1
T127	0	1
T162	0	3
T175	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7587864	6611216
T1	54432	3
T2	578	4
T3	1539	337
T4	852	451
T5	733	332
T6	986	3
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7587864	6613601
T1	54432	3
T2	578	4
T3	1539	339
T4	852	452
T5	733	333
T6	986	3
T12	721	321
T13	500	100
T14	730	330
T15	631	231

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7587864	34
T6	986	1
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	1
T36	0	1
T37	0	1
T50	1055	0
T51	501	0
T52	422	0
T114	0	1
T120	0	1
T122	0	1
T162	0	3
T175	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7587864	34
T6	986	1
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	1
T36	0	1
T37	0	1
T50	1055	0
T51	501	0
T52	422	0
T114	0	1
T120	0	1
T122	0	1
T162	0	3
T175	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7587864	33
T6	986	1
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	1
T36	0	1
T37	0	1
T50	1055	0
T51	501	0
T52	422	0
T114	0	1
T120	0	1
T122	0	1
T127	0	1
T162	0	3
T175	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7587864	33
T6	986	1
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	1
T36	0	1
T37	0	1
T50	1055	0
T51	501	0
T52	422	0
T114	0	1
T120	0	1
T122	0	1
T127	0	1
T162	0	3
T175	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7587864	2469
T6	986	267
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T34	0	10
T36	0	39
T37	0	8
T50	1055	0
T51	501	0
T52	422	0
T114	0	131
T120	0	84
T122	0	41
T127	0	40
T162	0	129
T175	0	38

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7587864	6728
T1	54432	0
T2	578	0
T3	1539	5
T4	852	4
T5	733	0
T6	986	1
T7	0	24
T8	0	1
T9	0	57
T10	0	10
T12	721	0
T13	500	1
T14	730	0
T15	631	0
T23	0	5
T50	0	6

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7587864	6918701
T1	54432	54032
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7587864	12
T37	691	1
T38	928	0
T68	1422	0
T96	2267	0
T105	16160	0
T122	0	1
T133	0	1
T134	0	1
T156	527	0
T161	0	1
T162	0	2
T167	0	1
T189	737	0
T205	0	1
T206	0	1
T207	0	1
T208	422	0
T209	403	0
T210	422	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T5,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T3,T5,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T9
0	1	Not Covered
1	0	Covered	T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T9
0	1	Covered	T5,T6,T33
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T6,T9
1	-	Covered	T5,T6,T33

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T6
DetectSt	168	Covered	T5,T6,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T7
DebounceSt->IdleSt	163	Covered	T3,T106,T162
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T5,T6,T9
IdleSt->DebounceSt	148	Covered	T3,T5,T6
StableSt->IdleSt	206	Covered	T5,T6,T9

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
0	0	Excluded	T4,T1,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T106,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T6
DetectSt	-	-	-	-	1	-	-	Covered	T7
DetectSt	-	-	-	-	0	1	-	Covered	T5,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T6,T33
StableSt	-	-	-	-	-	-	0	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	142	0	0
CntIncr_A	7587864	219954	0	0
CntNoWrap_A	7587864	6916130	0	0
DetectStDropOut_A	7587864	0	0	0
DetectedOut_A	7587864	110433	0	0
DetectedPulseOut_A	7587864	67	0	0
DisabledIdleSt_A	7587864	6182740	0	0
DisabledNoDetection_A	7587864	6185115	0	0
EnterDebounceSt_A	7587864	74	0	0
EnterDetectSt_A	7587864	68	0	0
EnterStableSt_A	7587864	67	0	0
PulseIsPulse_A	7587864	67	0	0
StayInStableSt	7587864	110338	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	38	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7587864	142
T3	1539	1
T5	733	4
T6	986	4
T7	6427	2
T8	934	0
T9	25421	2
T13	500	0
T14	730	0
T15	631	0
T33	0	4
T34	0	2
T37	0	2
T38	0	6
T39	0	2
T50	1055	0

CntIncr_A

Name	Attempts	Real Successes
Total	7587864	219954
T3	1539	79
T5	733	92
T6	986	132
T7	6427	23
T8	934	0
T9	25421	44
T13	500	0
T14	730	0
T15	631	0
T33	0	63146
T34	0	26
T37	0	19
T38	0	144
T39	0	45
T50	1055	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7587864	6916130
T1	54432	54031
T2	578	177
T3	1539	336
T4	852	451
T5	733	328
T6	986	581
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7587864	110433
T5	733	144
T6	986	82
T7	6427	0
T8	934	0
T9	25421	54
T10	1907	0
T11	9821	0
T23	524	0
T33	0	18446
T34	0	12
T37	0	13
T38	0	193
T39	0	95
T50	1055	0
T51	501	0
T106	0	75
T175	0	214

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7587864	67
T5	733	2
T6	986	2
T7	6427	0
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T37	0	1
T38	0	3
T39	0	1
T50	1055	0
T51	501	0
T106	0	2
T175	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7587864	6182740
T1	54432	54031
T2	578	177
T3	1539	127
T4	852	451
T5	733	4
T6	986	3
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7587864	6185115
T1	54432	54032
T2	578	178
T3	1539	128
T4	852	452
T5	733	4
T6	986	3
T12	721	321
T13	500	100
T14	730	330
T15	631	231

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7587864	74
T3	1539	1
T5	733	2
T6	986	2
T7	6427	1
T8	934	0
T9	25421	1
T13	500	0
T14	730	0
T15	631	0
T33	0	2
T34	0	1
T37	0	1
T38	0	3
T39	0	1
T50	1055	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7587864	68
T5	733	2
T6	986	2
T7	6427	1
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T37	0	1
T38	0	3
T39	0	1
T50	1055	0
T51	501	0
T106	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	7587864	67
T5	733	2
T6	986	2
T7	6427	0
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T37	0	1
T38	0	3
T39	0	1
T50	1055	0
T51	501	0
T106	0	2
T175	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7587864	67
T5	733	2
T6	986	2
T7	6427	0
T8	934	0
T9	25421	1
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	1
T37	0	1
T38	0	3
T39	0	1
T50	1055	0
T51	501	0
T106	0	2
T175	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7587864	110338
T5	733	141
T6	986	80
T7	6427	0
T8	934	0
T9	25421	52
T10	1907	0
T11	9821	0
T23	524	0
T33	0	18443
T34	0	11
T37	0	12
T38	0	189
T39	0	94
T50	1055	0
T51	501	0
T106	0	72
T175	0	213

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7587864	6918701
T1	54432	54032
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7587864	38
T5	733	1
T6	986	2
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T37	0	1
T38	0	2
T39	0	1
T50	1055	0
T51	501	0
T106	0	1
T162	0	2
T175	0	1
T176	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T5,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T3,T7,T8
1	1	Covered	T5,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T6
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T33
0	1	Covered	T5,T33,T179
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T6,T7
1	-	Covered	T5,T33,T179

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T7
DetectSt	168	Covered	T5,T6,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T7
DebounceSt->IdleSt	163	Covered	T92,T114,T211
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T5,T6,T7
IdleSt->DebounceSt	148	Covered	T5,T6,T7
StableSt->IdleSt	206	Covered	T5,T7,T33

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T114,T212
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T6
DetectSt	-	-	-	-	0	1	-	Covered	T5,T6,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T33
StableSt	-	-	-	-	-	-	0	Covered	T5,T6,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	76	0	0
CntIncr_A	7587864	124757	0	0
CntNoWrap_A	7587864	6916196	0	0
DetectStDropOut_A	7587864	1	0	0
DetectedOut_A	7587864	127651	0	0
DetectedPulseOut_A	7587864	36	0	0
DisabledIdleSt_A	7587864	6133337	0	0
DisabledNoDetection_A	7587864	6135711	0	0
EnterDebounceSt_A	7587864	41	0	0
EnterDetectSt_A	7587864	37	0	0
EnterStableSt_A	7587864	36	0	0
PulseIsPulse_A	7587864	36	0	0
StayInStableSt	7587864	127595	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	6480	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	14	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7587864	76
T5	733	2
T6	986	4
T7	6427	2
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	2
T34	0	2
T39	0	2
T50	1055	0
T51	501	0
T92	0	2
T162	0	2
T175	0	2
T179	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7587864	124757
T5	733	46
T6	986	132
T7	6427	23
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	31573
T34	0	26
T39	0	45
T50	1055	0
T51	501	0
T92	0	144
T162	0	34
T175	0	66
T179	0	46

CntNoWrap_A

Name	Attempts	Real Successes
Total	7587864	6916196
T1	54432	54031
T2	578	177
T3	1539	337
T4	852	451
T5	733	330
T6	986	581
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7587864	1
T6	986	1
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T50	1055	0
T51	501	0
T52	422	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7587864	127651
T5	733	39
T6	986	160
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	31615
T34	0	11
T39	0	110
T50	1055	0
T51	501	0
T92	0	40
T162	0	79
T175	0	132
T179	0	44

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7587864	36
T5	733	1
T6	986	1
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T34	0	1
T39	0	1
T50	1055	0
T51	501	0
T92	0	1
T162	0	1
T175	0	1
T179	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7587864	6133337
T1	54432	3
T2	578	4
T3	1539	337
T4	852	451
T5	733	4
T6	986	3
T12	721	320
T13	500	99
T14	730	329
T15	631	230

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7587864	6135711
T1	54432	3
T2	578	4
T3	1539	339
T4	852	452
T5	733	4
T6	986	3
T12	721	321
T13	500	100
T14	730	330
T15	631	231

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7587864	41
T5	733	1
T6	986	2
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T34	0	1
T39	0	1
T50	1055	0
T51	501	0
T92	0	2
T162	0	1
T175	0	1
T179	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7587864	37
T5	733	1
T6	986	2
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T34	0	1
T39	0	1
T50	1055	0
T51	501	0
T92	0	1
T162	0	1
T175	0	1
T179	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7587864	36
T5	733	1
T6	986	1
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T34	0	1
T39	0	1
T50	1055	0
T51	501	0
T92	0	1
T162	0	1
T175	0	1
T179	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7587864	36
T5	733	1
T6	986	1
T7	6427	1
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T34	0	1
T39	0	1
T50	1055	0
T51	501	0
T92	0	1
T162	0	1
T175	0	1
T179	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7587864	127595
T5	733	38
T6	986	158
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	31614
T34	0	10
T39	0	108
T50	1055	0
T51	501	0
T92	0	38
T114	0	97
T162	0	77
T175	0	130
T179	0	43

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7587864	6480
T3	1539	7
T5	733	1
T6	986	2
T7	6427	26
T8	934	1
T9	25421	64
T10	0	11
T11	0	28
T13	500	0
T14	730	0
T15	631	0
T23	0	4
T50	1055	0
T51	0	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7587864	6918701
T1	54432	54032
T2	578	178
T3	1539	339
T4	852	452
T5	733	333
T6	986	586
T12	721	321
T13	500	100
T14	730	330
T15	631	231

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7587864	14
T5	733	1
T6	986	0
T7	6427	0
T8	934	0
T9	25421	0
T10	1907	0
T11	9821	0
T23	524	0
T33	0	1
T50	1055	0
T51	501	0
T114	0	1
T130	0	1
T144	0	1
T163	0	1
T179	0	1
T183	0	1
T184	0	2
T213	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr