Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T5,T33,T38
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T5
1	-	Covered	T5,T33,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T5
DetectSt	168	Covered	T1,T3,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T5
DebounceSt->IdleSt	163	Covered	T96,T106,T92
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T3,T5
IdleSt->DebounceSt	148	Covered	T1,T3,T5
StableSt->IdleSt	206	Covered	T5,T7,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T96,T106,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	145	0	0
CntIncr_A	7587864	222368	0	0
CntNoWrap_A	7587864	6916127	0	0
DetectStDropOut_A	7587864	0	0	0
DetectedOut_A	7587864	92212	0	0
DetectedPulseOut_A	7587864	67	0	0
DisabledIdleSt_A	7587864	6253771	0	0
DisabledNoDetection_A	7587864	6256143	0	0
EnterDebounceSt_A	7587864	79	0	0
EnterDetectSt_A	7587864	67	0	0
EnterStableSt_A	7587864	67	0	0
PulseIsPulse_A	7587864	67	0	0
StayInStableSt	7587864	92115	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	145	0	0
T1	54432	2	0	0
T2	578	0	0	0
T3	1539	2	0	0
T5	733	2	0	0
T6	986	0	0	0
T7	6427	2	0	0
T8	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T96	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	222368	0	0
T1	54432	26987	0	0
T2	578	0	0	0
T3	1539	79	0	0
T5	733	46	0	0
T6	986	0	0	0
T7	6427	23	0	0
T8	0	74	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	63146	0	0
T34	0	26	0	0
T38	0	96	0	0
T39	0	45	0	0
T96	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916127	0	0
T1	54432	54029	0	0
T2	578	177	0	0
T3	1539	335	0	0
T4	852	451	0	0
T5	733	330	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	92212	0	0
T1	54432	27036	0	0
T2	578	0	0	0
T3	1539	126	0	0
T5	733	43	0	0
T6	986	0	0	0
T7	6427	2	0	0
T8	0	450	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	59800	0	0
T34	0	12	0	0
T38	0	153	0	0
T39	0	40	0	0
T106	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	67	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6253771	0	0
T1	54432	3	0	0
T2	578	177	0	0
T3	1539	127	0	0
T4	852	451	0	0
T5	733	4	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6256143	0	0
T1	54432	3	0	0
T2	578	178	0	0
T3	1539	128	0	0
T4	852	452	0	0
T5	733	4	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	79	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T96	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	67	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	67	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	67	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	92115	0	0
T1	54432	27034	0	0
T2	578	0	0	0
T3	1539	124	0	0
T5	733	42	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	448	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	59797	0	0
T34	0	11	0	0
T38	0	150	0	0
T39	0	38	0	0
T106	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	35	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	0	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T92	0	1	0	0
T162	0	3	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T7,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T5,T6
1	1	Covered	T7,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T33,T34
0	1	Covered	T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T33,T35,T37
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T33,T34
1	-	Covered	T33,T35,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T33,T34
DetectSt	168	Covered	T7,T33,T34
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T7,T33,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T33,T34
DebounceSt->IdleSt	163	Covered	T176,T162,T186
DetectSt->IdleSt	186	Covered	T114
DetectSt->StableSt	191	Covered	T7,T33,T34
IdleSt->DebounceSt	148	Covered	T7,T33,T34
StableSt->IdleSt	206	Covered	T7,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T33,T34
0	1	Covered	T7,T33,T34
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T33,T34
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T176,T162,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T114
DetectSt	-	-	-	-	0	1	-	Covered	T7,T33,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T33,T34
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	77	0	0
CntIncr_A	7587864	153747	0	0
CntNoWrap_A	7587864	6916195	0	0
DetectStDropOut_A	7587864	1	0	0
DetectedOut_A	7587864	147129	0	0
DetectedPulseOut_A	7587864	36	0	0
DisabledIdleSt_A	7587864	6058896	0	0
DisabledNoDetection_A	7587864	6061266	0	0
EnterDebounceSt_A	7587864	40	0	0
EnterDetectSt_A	7587864	37	0	0
EnterStableSt_A	7587864	36	0	0
PulseIsPulse_A	7587864	36	0	0
StayInStableSt	7587864	147075	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	6441	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	77	0	0
T7	6427	2	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	2	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	153747	0	0
T7	6427	23	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	31573	0	0
T34	0	26	0	0
T35	0	67	0	0
T36	0	89	0	0
T37	0	19	0	0
T38	0	48	0	0
T40	0	20	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	56	0	0
T179	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916195	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1	0	0
T73	4434	0	0	0
T114	11277	1	0	0
T120	8722	0	0	0
T121	14578	0	0	0
T122	678	0	0	0
T123	30636	0	0	0
T124	494	0	0	0
T125	402	0	0	0
T126	521	0	0	0
T127	572	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	147129	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	81622	0	0
T34	0	12	0	0
T35	0	60	0	0
T36	0	42	0	0
T37	0	68	0	0
T38	0	219	0	0
T40	0	6	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	233	0	0
T179	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	36	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	1	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6058896	0	0
T1	54432	54031	0	0
T2	578	4	0	0
T3	1539	127	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6061266	0	0
T1	54432	54032	0	0
T2	578	4	0	0
T3	1539	128	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	40	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	37	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	1	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	36	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	1	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	36	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T106	0	1	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	147075	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	81621	0	0
T34	0	11	0	0
T35	0	59	0	0
T36	0	40	0	0
T37	0	67	0	0
T38	0	218	0	0
T39	705	0	0	0
T40	0	5	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T106	0	232	0	0
T129	422	0	0	0
T175	0	199	0	0
T179	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6441	0	0
T3	1539	5	0	0
T5	733	1	0	0
T6	986	1	0	0
T7	6427	25	0	0
T8	934	0	0	0
T9	25421	62	0	0
T10	0	10	0	0
T11	0	25	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T16	0	29	0	0
T23	0	5	0	0
T50	1055	0	0	0
T51	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	16	0	0
T21	491	0	0	0
T29	1658	0	0	0
T32	13031	0	0	0
T33	236553	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	705	0	0	0
T40	0	1	0	0
T53	1324	0	0	0
T64	523	0	0	0
T65	504	0	0	0
T86	402	0	0	0
T106	0	1	0	0
T114	0	1	0	0
T129	422	0	0	0
T162	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T1,T114,T214
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T8,T9,T37
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T7
1	-	Covered	T8,T9,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T5
DetectSt	168	Covered	T1,T3,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T5
DebounceSt->IdleSt	163	Covered	T215,T92,T143
DetectSt->IdleSt	186	Covered	T1,T114,T214
DetectSt->StableSt	191	Covered	T3,T5,T7
IdleSt->DebounceSt	148	Covered	T1,T3,T5
StableSt->IdleSt	206	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T215,T143,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T1,T114,T214
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	152	0	0
CntIncr_A	7587864	102740	0	0
CntNoWrap_A	7587864	6916120	0	0
DetectStDropOut_A	7587864	3	0	0
DetectedOut_A	7587864	32420	0	0
DetectedPulseOut_A	7587864	70	0	0
DisabledIdleSt_A	7587864	6685844	0	0
DisabledNoDetection_A	7587864	6688208	0	0
EnterDebounceSt_A	7587864	80	0	0
EnterDetectSt_A	7587864	73	0	0
EnterStableSt_A	7587864	70	0	0
PulseIsPulse_A	7587864	70	0	0
StayInStableSt	7587864	32316	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	152	0	0
T1	54432	2	0	0
T2	578	0	0	0
T3	1539	2	0	0
T5	733	2	0	0
T6	986	0	0	0
T7	6427	2	0	0
T8	0	4	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	2	0	0
T37	0	4	0	0
T96	0	2	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	102740	0	0
T1	54432	26987	0	0
T2	578	0	0	0
T3	1539	79	0	0
T5	733	46	0	0
T6	986	0	0	0
T7	6427	23	0	0
T8	0	148	0	0
T9	0	44	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	26	0	0
T37	0	38	0	0
T96	0	76	0	0
T189	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916120	0	0
T1	54432	54029	0	0
T2	578	177	0	0
T3	1539	335	0	0
T4	852	451	0	0
T5	733	330	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	3	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T114	0	1	0	0
T214	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	32420	0	0
T3	1539	46	0	0
T5	733	278	0	0
T6	986	0	0	0
T7	6427	2	0	0
T8	934	171	0	0
T9	25421	121	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	11	0	0
T37	0	181	0	0
T50	1055	0	0	0
T96	0	29	0	0
T189	0	235	0	0
T199	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	70	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	2	0	0
T9	25421	1	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T50	1055	0	0	0
T96	0	1	0	0
T189	0	1	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6685844	0	0
T1	54432	3	0	0
T2	578	177	0	0
T3	1539	127	0	0
T4	852	451	0	0
T5	733	4	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6688208	0	0
T1	54432	3	0	0
T2	578	178	0	0
T3	1539	128	0	0
T4	852	452	0	0
T5	733	4	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	80	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T96	0	1	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	73	0	0
T1	54432	1	0	0
T2	578	0	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T96	0	1	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	70	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	2	0	0
T9	25421	1	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T50	1055	0	0	0
T96	0	1	0	0
T189	0	1	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	70	0	0
T3	1539	1	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	2	0	0
T9	25421	1	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T50	1055	0	0	0
T96	0	1	0	0
T189	0	1	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	32316	0	0
T3	1539	44	0	0
T5	733	276	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	934	168	0	0
T9	25421	120	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	10	0	0
T37	0	178	0	0
T50	1055	0	0	0
T96	0	28	0	0
T189	0	233	0	0
T199	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34	0	0
T8	934	1	0	0
T9	25421	1	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T20	2296	0	0	0
T23	524	0	0	0
T30	40559	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	501	0	0	0
T52	422	0	0	0
T96	0	1	0	0
T162	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T179	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T8,T33,T39
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T8,T33,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T92,T165
DetectSt->IdleSt	186	Covered	T134
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T7,T8,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T134
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	100	0	0
CntIncr_A	7587864	328548	0	0
CntNoWrap_A	7587864	6916172	0	0
DetectStDropOut_A	7587864	1	0	0
DetectedOut_A	7587864	143257	0	0
DetectedPulseOut_A	7587864	48	0	0
DisabledIdleSt_A	7587864	5900507	0	0
DisabledNoDetection_A	7587864	5902883	0	0
EnterDebounceSt_A	7587864	51	0	0
EnterDetectSt_A	7587864	49	0	0
EnterStableSt_A	7587864	48	0	0
PulseIsPulse_A	7587864	48	0	0
StayInStableSt	7587864	143182	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	6453	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	100	0	0
T1	54432	2	0	0
T2	578	2	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	2	0	0
T8	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	328548	0	0
T1	54432	26987	0	0
T2	578	42	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	23	0	0
T8	0	74	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	63146	0	0
T34	0	26	0	0
T35	0	67	0	0
T37	0	19	0	0
T38	0	96	0	0
T39	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916172	0	0
T1	54432	54029	0	0
T2	578	175	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1	0	0
T119	593	0	0	0
T134	777	1	0	0
T152	48135	0	0	0
T169	506	0	0	0
T170	603	0	0	0
T171	5470	0	0	0
T172	36313	0	0	0
T217	14862	0	0	0
T218	493	0	0	0
T219	1932	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	143257	0	0
T1	54432	48	0	0
T2	578	43	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	129	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	81636	0	0
T34	0	12	0	0
T35	0	61	0	0
T37	0	42	0	0
T38	0	260	0	0
T39	0	111	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	48	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5900507	0	0
T1	54432	3	0	0
T2	578	4	0	0
T3	1539	127	0	0
T4	852	451	0	0
T5	733	4	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	5902883	0	0
T1	54432	3	0	0
T2	578	4	0	0
T3	1539	128	0	0
T4	852	452	0	0
T5	733	4	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	51	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	49	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	48	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	48	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T8	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	143182	0	0
T1	54432	46	0	0
T2	578	41	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T8	0	128	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	81633	0	0
T34	0	11	0	0
T35	0	60	0	0
T37	0	41	0	0
T38	0	257	0	0
T39	0	110	0	0
T40	0	71	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6453	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	5	0	0
T5	733	0	0	0
T6	986	2	0	0
T7	6427	29	0	0
T8	0	1	0	0
T9	0	60	0	0
T10	0	10	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T23	0	4	0	0
T51	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	19	0	0
T8	934	1	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T20	2296	0	0	0
T23	524	0	0	0
T30	40559	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T51	501	0	0	0
T52	422	0	0	0
T175	0	1	0	0
T179	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T3,T13
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T93,T133
1	0	Covered	T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T33
0	1	Covered	T2,T9,T33
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T33
1	-	Covered	T2,T9,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T2,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T9,T59,T36
DetectSt->IdleSt	186	Covered	T7,T93,T133
DetectSt->StableSt	191	Covered	T1,T2,T9
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T2,T9,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T36,T106
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T93,T133
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	113	0	0
CntIncr_A	7587864	126671	0	0
CntNoWrap_A	7587864	6916159	0	0
DetectStDropOut_A	7587864	2	0	0
DetectedOut_A	7587864	173578	0	0
DetectedPulseOut_A	7587864	49	0	0
DisabledIdleSt_A	7587864	6248925	0	0
DisabledNoDetection_A	7587864	6251307	0	0
EnterDebounceSt_A	7587864	62	0	0
EnterDetectSt_A	7587864	52	0	0
EnterStableSt_A	7587864	49	0	0
PulseIsPulse_A	7587864	49	0	0
StayInStableSt	7587864	173509	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	113	0	0
T1	54432	2	0	0
T2	578	2	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	2	0	0
T9	0	3	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T106	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	126671	0	0
T1	54432	26987	0	0
T2	578	42	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	23	0	0
T9	0	88	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	31573	0	0
T34	0	26	0	0
T36	0	89	0	0
T37	0	19	0	0
T59	0	2327	0	0
T106	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916159	0	0
T1	54432	54029	0	0
T2	578	175	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	2	0	0
T93	143648	1	0	0
T111	46245	0	0	0
T133	0	1	0	0
T220	502	0	0	0
T221	435	0	0	0
T222	435	0	0	0
T223	508	0	0	0
T224	406	0	0	0
T225	510	0	0	0
T226	425	0	0	0
T227	19782	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	173578	0	0
T1	54432	27036	0	0
T2	578	39	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	81580	0	0
T34	0	12	0	0
T37	0	40	0	0
T40	0	134	0	0
T106	0	83	0	0
T176	0	355	0	0
T187	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	49	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T106	0	2	0	0
T176	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6248925	0	0
T1	54432	3	0	0
T2	578	4	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6251307	0	0
T1	54432	3	0	0
T2	578	4	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	62	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T59	0	1	0	0
T106	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	52	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T106	0	2	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	49	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T106	0	2	0	0
T176	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	49	0	0
T1	54432	1	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T106	0	2	0	0
T176	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	173509	0	0
T1	54432	27034	0	0
T2	578	38	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	81579	0	0
T34	0	11	0	0
T37	0	39	0	0
T40	0	132	0	0
T106	0	80	0	0
T162	0	119	0	0
T176	0	353	0	0
T187	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	28	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	0	0	0
T6	986	0	0	0
T7	6427	0	0	0
T9	0	1	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T50	1055	0	0	0
T93	0	2	0	0
T106	0	1	0	0
T120	0	1	0	0
T178	0	1	0	0
T182	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T3,T13
1	1	Covered	T2,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T7
0	1	Covered	T93,T228
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T9
0	1	Covered	T9,T106,T162
1	0	Covered	T7,T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T7
1	-	Covered	T9,T106,T162

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T5,T7
DetectSt	168	Covered	T2,T5,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T5,T7
DebounceSt->IdleSt	163	Covered	T106,T92
DetectSt->IdleSt	186	Covered	T93,T228
DetectSt->StableSt	191	Covered	T2,T5,T7
IdleSt->DebounceSt	148	Covered	T2,T5,T7
StableSt->IdleSt	206	Covered	T7,T9,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T5,T7
0	1	Covered	T2,T5,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T106
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T93,T228
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	73	0	0
CntIncr_A	7587864	64914	0	0
CntNoWrap_A	7587864	6916199	0	0
DetectStDropOut_A	7587864	2	0	0
DetectedOut_A	7587864	28461	0	0
DetectedPulseOut_A	7587864	34	0	0
DisabledIdleSt_A	7587864	6372025	0	0
DisabledNoDetection_A	7587864	6374396	0	0
EnterDebounceSt_A	7587864	38	0	0
EnterDetectSt_A	7587864	36	0	0
EnterStableSt_A	7587864	34	0	0
PulseIsPulse_A	7587864	34	0	0
StayInStableSt	7587864	28408	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7587864	7177	0	0
gen_low_level_sva.LowLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	73	0	0
T2	578	2	0	0
T3	1539	0	0	0
T5	733	2	0	0
T6	986	0	0	0
T7	6427	2	0	0
T9	0	4	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T50	1055	0	0	0
T106	0	3	0	0
T162	0	4	0	0
T203	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	64914	0	0
T2	578	42	0	0
T3	1539	0	0	0
T5	733	46	0	0
T6	986	0	0	0
T7	6427	23	0	0
T9	0	88	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	26	0	0
T36	0	89	0	0
T37	0	19	0	0
T50	1055	0	0	0
T106	0	112	0	0
T162	0	68	0	0
T203	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6916199	0	0
T1	54432	54031	0	0
T2	578	175	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	330	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	2	0	0
T93	143648	1	0	0
T111	46245	0	0	0
T220	502	0	0	0
T221	435	0	0	0
T222	435	0	0	0
T223	508	0	0	0
T224	406	0	0	0
T225	510	0	0	0
T226	425	0	0	0
T227	19782	0	0	0
T228	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	28461	0	0
T2	578	44	0	0
T3	1539	0	0	0
T5	733	41	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	95	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	11	0	0
T36	0	41	0	0
T37	0	76	0	0
T50	1055	0	0	0
T106	0	126	0	0
T162	0	44	0	0
T203	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	1055	0	0	0
T106	0	1	0	0
T162	0	2	0	0
T203	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6372025	0	0
T1	54432	3	0	0
T2	578	4	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	4	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6374396	0	0
T1	54432	3	0	0
T2	578	4	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	4	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	38	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	1055	0	0	0
T106	0	2	0	0
T162	0	2	0	0
T203	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	36	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	1055	0	0	0
T106	0	1	0	0
T162	0	2	0	0
T203	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	1055	0	0	0
T106	0	1	0	0
T162	0	2	0	0
T203	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	34	0	0
T2	578	1	0	0
T3	1539	0	0	0
T5	733	1	0	0
T6	986	0	0	0
T7	6427	1	0	0
T9	0	2	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	1055	0	0	0
T106	0	1	0	0
T162	0	2	0	0
T203	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	28408	0	0
T2	578	42	0	0
T3	1539	0	0	0
T5	733	39	0	0
T6	986	0	0	0
T7	6427	0	0	0
T9	0	92	0	0
T12	721	0	0	0
T13	500	0	0	0
T14	730	0	0	0
T15	631	0	0	0
T34	0	10	0	0
T36	0	39	0	0
T37	0	74	0	0
T50	1055	0	0	0
T92	0	40	0	0
T106	0	125	0	0
T162	0	41	0	0
T203	0	172	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	7177	0	0
T1	54432	0	0	0
T2	578	1	0	0
T3	1539	4	0	0
T4	852	4	0	0
T5	733	1	0	0
T6	986	2	0	0
T7	0	36	0	0
T12	721	0	0	0
T13	500	1	0	0
T14	730	2	0	0
T15	631	3	0	0
T50	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	13	0	0
T9	25421	1	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T20	2296	0	0	0
T23	524	0	0	0
T30	40559	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T54	508	0	0	0
T92	0	1	0	0
T106	0	1	0	0
T114	0	2	0	0
T162	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T203	0	1	0	0
T216	0	1	0	0