Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T11,T16
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T11,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T11,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T11,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T16
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T16
0	1	Covered	T7,T43,T34
1	0	Covered	T7,T43,T34

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T16
0	1	Covered	T7,T11,T16
1	0	Covered	T95

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T16
1	-	Covered	T7,T11,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T16
DetectSt	168	Covered	T7,T11,T16
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T7,T11,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T16
DebounceSt->IdleSt	163	Covered	T7,T34,T230
DetectSt->IdleSt	186	Covered	T7,T43,T34
DetectSt->StableSt	191	Covered	T7,T11,T16
IdleSt->DebounceSt	148	Covered	T7,T11,T16
StableSt->IdleSt	206	Covered	T7,T11,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T11,T16
0	1	Covered	T7,T11,T16
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T16
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T16
IdleSt	0	-	-	-	-	-	-	Covered	T7,T11,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T7,T34
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T34,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T16
DetectSt	-	-	-	-	1	-	-	Covered	T7,T43,T34
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T16
DetectSt	-	-	-	-	0	0	-	Covered	T7,T11,T16
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T16
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T16
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	3326	0	0
CntIncr_A	7587864	120286	0	0
CntNoWrap_A	7587864	6912946	0	0
DetectStDropOut_A	7587864	287	0	0
DetectedOut_A	7587864	99523	0	0
DetectedPulseOut_A	7587864	1190	0	0
DisabledIdleSt_A	7587864	6383188	0	0
DisabledNoDetection_A	7587864	6385374	0	0
EnterDebounceSt_A	7587864	1674	0	0
EnterDetectSt_A	7587864	1654	0	0
EnterStableSt_A	7587864	1190	0	0
PulseIsPulse_A	7587864	1190	0	0
StayInStableSt	7587864	98183	0	0
gen_high_event_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	1030	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	3326	0	0
T7	6427	17	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	38	0	0
T16	13422	64	0	0
T23	524	0	0	0
T31	0	54	0	0
T32	0	16	0	0
T34	0	16	0	0
T43	0	50	0	0
T46	0	20	0	0
T47	0	60	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	120286	0	0
T7	6427	388	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	1444	0	0
T16	13422	2240	0	0
T23	524	0	0	0
T31	0	2403	0	0
T32	0	424	0	0
T34	0	662	0	0
T43	0	1512	0	0
T46	0	600	0	0
T47	0	1950	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	350	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6912946	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	287	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	0	0	0
T16	13422	0	0	0
T23	524	0	0	0
T34	0	1	0	0
T43	0	15	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T105	0	8	0	0
T107	0	19	0	0
T109	0	16	0	0
T113	0	21	0	0
T233	0	15	0	0
T244	0	8	0	0
T256	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	99523	0	0
T7	6427	303	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	2107	0	0
T16	13422	2282	0	0
T23	524	0	0	0
T31	0	1687	0	0
T32	0	1319	0	0
T34	0	451	0	0
T46	0	72	0	0
T47	0	3547	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	588	0	0
T158	0	282	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1190	0	0
T7	6427	5	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	19	0	0
T16	13422	32	0	0
T23	524	0	0	0
T31	0	27	0	0
T32	0	8	0	0
T34	0	5	0	0
T46	0	10	0	0
T47	0	30	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	5	0	0
T158	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6383188	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6385374	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1674	0	0
T7	6427	10	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	19	0	0
T16	13422	32	0	0
T23	524	0	0	0
T31	0	27	0	0
T32	0	8	0	0
T34	0	9	0	0
T43	0	25	0	0
T46	0	10	0	0
T47	0	30	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1654	0	0
T7	6427	7	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	19	0	0
T16	13422	32	0	0
T23	524	0	0	0
T31	0	27	0	0
T32	0	8	0	0
T34	0	7	0	0
T43	0	25	0	0
T46	0	10	0	0
T47	0	30	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1190	0	0
T7	6427	5	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	19	0	0
T16	13422	32	0	0
T23	524	0	0	0
T31	0	27	0	0
T32	0	8	0	0
T34	0	5	0	0
T46	0	10	0	0
T47	0	30	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	5	0	0
T158	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1190	0	0
T7	6427	5	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	19	0	0
T16	13422	32	0	0
T23	524	0	0	0
T31	0	27	0	0
T32	0	8	0	0
T34	0	5	0	0
T46	0	10	0	0
T47	0	30	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	5	0	0
T158	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	98183	0	0
T7	6427	298	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	2088	0	0
T16	13422	2249	0	0
T23	524	0	0	0
T31	0	1658	0	0
T32	0	1310	0	0
T34	0	446	0	0
T46	0	62	0	0
T47	0	3510	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	582	0	0
T158	0	267	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1030	0	0
T7	6427	5	0	0
T8	934	0	0	0
T9	25421	0	0	0
T10	1907	0	0	0
T11	9821	19	0	0
T16	13422	31	0	0
T23	524	0	0	0
T31	0	25	0	0
T32	0	7	0	0
T34	0	5	0	0
T46	0	10	0	0
T47	0	23	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0
T66	0	4	0	0
T158	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T9,T11
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T7,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T3,T7,T9
1	1	Covered	T7,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Covered	T83,T234,T248
1	0	Covered	T7,T34

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Covered	T9,T11,T16
1	0	Covered	T7,T34,T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T11
1	-	Covered	T9,T11,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T11
DetectSt	168	Covered	T7,T9,T11
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T7,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T11
DebounceSt->IdleSt	163	Covered	T7,T30,T34
DetectSt->IdleSt	186	Covered	T7,T34,T83
DetectSt->StableSt	191	Covered	T7,T9,T11
IdleSt->DebounceSt	148	Covered	T7,T9,T11
StableSt->IdleSt	206	Covered	T7,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T11
0	1	Covered	T7,T9,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T11
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T7,T34
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T243,T247
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T7,T34,T83
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T7,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7587864	1012	0	0
CntIncr_A	7587864	55935	0	0
CntNoWrap_A	7587864	6915260	0	0
DetectStDropOut_A	7587864	81	0	0
DetectedOut_A	7587864	20169	0	0
DetectedPulseOut_A	7587864	394	0	0
DisabledIdleSt_A	7587864	6499800	0	0
DisabledNoDetection_A	7587864	6501527	0	0
EnterDebounceSt_A	7587864	535	0	0
EnterDetectSt_A	7587864	480	0	0
EnterStableSt_A	7587864	394	0	0
PulseIsPulse_A	7587864	394	0	0
StayInStableSt	7587864	19729	0	0
gen_high_level_sva.HighLevelEvent_A	7587864	6918701	0	0
gen_not_sticky_sva.StableStDropOut_A	7587864	344	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	1012	0	0
T7	6427	8	0	0
T8	934	0	0	0
T9	25421	6	0	0
T10	1907	0	0	0
T11	9821	6	0	0
T16	13422	8	0	0
T23	524	0	0	0
T30	0	22	0	0
T31	0	8	0	0
T32	0	4	0	0
T34	0	8	0	0
T41	0	12	0	0
T44	0	8	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	55935	0	0
T7	6427	168	0	0
T8	934	0	0	0
T9	25421	111	0	0
T10	1907	0	0	0
T11	9821	249	0	0
T16	13422	296	0	0
T23	524	0	0	0
T30	0	1301	0	0
T31	0	300	0	0
T32	0	44	0	0
T34	0	305	0	0
T41	0	696	0	0
T44	0	672	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6915260	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	81	0	0
T36	14575	0	0	0
T46	7455	0	0	0
T47	29814	0	0	0
T60	491	0	0	0
T83	23689	5	0	0
T93	0	1	0	0
T111	0	5	0	0
T112	0	4	0	0
T151	0	12	0	0
T234	0	3	0	0
T242	22330	0	0	0
T248	0	1	0	0
T252	547	0	0	0
T253	422	0	0	0
T254	501	0	0	0
T255	507	0	0	0
T258	0	10	0	0
T259	0	5	0	0
T260	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	20169	0	0
T7	6427	68	0	0
T8	934	0	0	0
T9	25421	101	0	0
T10	1907	0	0	0
T11	9821	129	0	0
T16	13422	204	0	0
T23	524	0	0	0
T30	0	868	0	0
T31	0	207	0	0
T32	0	413	0	0
T34	0	76	0	0
T41	0	63	0	0
T44	0	132	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	394	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	3	0	0
T10	1907	0	0	0
T11	9821	3	0	0
T16	13422	4	0	0
T23	524	0	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	1	0	0
T41	0	6	0	0
T44	0	4	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6499800	0	0
T1	54432	54031	0	0
T2	578	177	0	0
T3	1539	337	0	0
T4	852	451	0	0
T5	733	332	0	0
T6	986	585	0	0
T12	721	320	0	0
T13	500	99	0	0
T14	730	329	0	0
T15	631	230	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6501527	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	535	0	0
T7	6427	5	0	0
T8	934	0	0	0
T9	25421	3	0	0
T10	1907	0	0	0
T11	9821	3	0	0
T16	13422	4	0	0
T23	524	0	0	0
T30	0	13	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	5	0	0
T41	0	6	0	0
T44	0	4	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	480	0	0
T7	6427	3	0	0
T8	934	0	0	0
T9	25421	3	0	0
T10	1907	0	0	0
T11	9821	3	0	0
T16	13422	4	0	0
T23	524	0	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	3	0	0
T41	0	6	0	0
T44	0	4	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	394	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	3	0	0
T10	1907	0	0	0
T11	9821	3	0	0
T16	13422	4	0	0
T23	524	0	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	1	0	0
T41	0	6	0	0
T44	0	4	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	394	0	0
T7	6427	1	0	0
T8	934	0	0	0
T9	25421	3	0	0
T10	1907	0	0	0
T11	9821	3	0	0
T16	13422	4	0	0
T23	524	0	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	1	0	0
T41	0	6	0	0
T44	0	4	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	19729	0	0
T7	6427	67	0	0
T8	934	0	0	0
T9	25421	98	0	0
T10	1907	0	0	0
T11	9821	126	0	0
T16	13422	200	0	0
T23	524	0	0	0
T30	0	859	0	0
T31	0	203	0	0
T32	0	411	0	0
T34	0	75	0	0
T41	0	57	0	0
T44	0	128	0	0
T50	1055	0	0	0
T51	501	0	0	0
T52	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	6918701	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7587864	344	0	0
T9	25421	3	0	0
T10	1907	0	0	0
T11	9821	3	0	0
T16	13422	4	0	0
T20	2296	0	0	0
T23	524	0	0	0
T30	40559	9	0	0
T31	0	3	0	0
T32	0	2	0	0
T41	0	6	0	0
T44	0	4	0	0
T45	0	5	0	0
T51	501	0	0	0
T52	422	0	0	0
T54	508	0	0	0
T242	0	8	0	0