Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1198461200	10686	0	0
auto_block_debounce_ctl_rd_A	1198461200	1770	0	0
auto_block_out_ctl_rd_A	1198461200	2367	0	0
com_det_ctl_0_rd_A	1198461200	3934	0	0
com_det_ctl_1_rd_A	1198461200	3870	0	0
com_det_ctl_2_rd_A	1198461200	4037	0	0
com_det_ctl_3_rd_A	1198461200	3981	0	0
com_out_ctl_0_rd_A	1198461200	4266	0	0
com_out_ctl_1_rd_A	1198461200	4456	0	0
com_out_ctl_2_rd_A	1198461200	4343	0	0
com_out_ctl_3_rd_A	1198461200	4496	0	0
com_pre_det_ctl_0_rd_A	1198461200	1434	0	0
com_pre_det_ctl_1_rd_A	1198461200	1451	0	0
com_pre_det_ctl_2_rd_A	1198461200	1268	0	0
com_pre_det_ctl_3_rd_A	1198461200	1337	0	0
com_pre_sel_ctl_0_rd_A	1198461200	4380	0	0
com_pre_sel_ctl_1_rd_A	1198461200	4738	0	0
com_pre_sel_ctl_2_rd_A	1198461200	4452	0	0
com_pre_sel_ctl_3_rd_A	1198461200	4606	0	0
com_sel_ctl_0_rd_A	1198461200	4319	0	0
com_sel_ctl_1_rd_A	1198461200	4395	0	0
com_sel_ctl_2_rd_A	1198461200	4227	0	0
com_sel_ctl_3_rd_A	1198461200	4491	0	0
ec_rst_ctl_rd_A	1198461200	2383	0	0
intr_enable_rd_A	1198461200	2185	0	0
key_intr_ctl_rd_A	1198461200	3519	0	0
key_intr_debounce_ctl_rd_A	1198461200	1373	0	0
key_invert_ctl_rd_A	1198461200	4823	0	0
pin_allowed_ctl_rd_A	1198461200	5344	0	0
pin_out_ctl_rd_A	1198461200	4140	0	0
pin_out_value_rd_A	1198461200	4283	0	0
regwen_rd_A	1198461200	1910	0	0
ulp_ac_debounce_ctl_rd_A	1198461200	1534	0	0
ulp_ctl_rd_A	1198461200	1453	0	0
ulp_lid_debounce_ctl_rd_A	1198461200	1542	0	0
ulp_pwrb_debounce_ctl_rd_A	1198461200	1562	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	10686	0	0
T9	752284	19	0	0
T10	915847	0	0	0
T11	491074	0	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T23	131019	0	0	0
T30	194679	0	0	0
T36	0	22	0	0
T45	0	23	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T59	0	11	0	0
T83	0	10	0	0
T103	0	1	0	0
T162	0	23	0	0
T215	0	11	0	0
T268	0	11	0	0
T269	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1770	0	0
T31	235363	0	0	0
T34	378297	0	0	0
T42	286850	5	0	0
T43	321882	0	0	0
T44	165086	0	0	0
T58	61428	0	0	0
T100	0	4	0	0
T128	0	2	0	0
T177	0	41	0	0
T197	0	16	0	0
T236	0	7	0	0
T269	0	9	0	0
T270	0	17	0	0
T271	0	18	0	0
T272	0	15	0	0
T273	202840	0	0	0
T274	131693	0	0	0
T275	103939	0	0	0
T276	46889	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2367	0	0
T31	235363	0	0	0
T34	378297	0	0	0
T42	286850	5	0	0
T43	321882	0	0	0
T44	165086	0	0	0
T58	61428	0	0	0
T100	0	9	0	0
T128	0	4	0	0
T177	0	47	0	0
T197	0	10	0	0
T236	0	9	0	0
T269	0	17	0	0
T270	0	1	0	0
T271	0	11	0	0
T272	0	14	0	0
T273	202840	0	0	0
T274	131693	0	0	0
T275	103939	0	0	0
T276	46889	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	3934	0	0
T11	491074	18	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	41	0	0
T43	0	46	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	80	0	0
T84	99239	0	0	0
T104	0	83	0	0
T105	0	59	0	0
T242	0	48	0	0
T243	0	64	0	0
T247	0	71	0	0
T269	0	10	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	3870	0	0
T11	491074	31	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	33	0	0
T43	0	46	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	91	0	0
T84	99239	0	0	0
T104	0	71	0	0
T105	0	56	0	0
T242	0	76	0	0
T243	0	67	0	0
T247	0	78	0	0
T269	0	7	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4037	0	0
T11	491074	35	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	31	0	0
T43	0	45	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	108	0	0
T84	99239	0	0	0
T104	0	88	0	0
T105	0	54	0	0
T242	0	53	0	0
T243	0	86	0	0
T247	0	100	0	0
T269	0	12	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	3981	0	0
T11	491074	26	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	48	0	0
T43	0	62	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	86	0	0
T84	99239	0	0	0
T104	0	69	0	0
T105	0	46	0	0
T242	0	56	0	0
T243	0	62	0	0
T247	0	63	0	0
T269	0	11	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4266	0	0
T11	491074	21	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	36	0	0
T43	0	53	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	71	0	0
T84	99239	0	0	0
T104	0	76	0	0
T105	0	56	0	0
T242	0	81	0	0
T243	0	74	0	0
T247	0	70	0	0
T269	0	9	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4456	0	0
T11	491074	29	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	55	0	0
T43	0	67	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	99	0	0
T84	99239	0	0	0
T104	0	58	0	0
T105	0	53	0	0
T242	0	80	0	0
T243	0	69	0	0
T247	0	58	0	0
T269	0	16	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4343	0	0
T11	491074	28	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	29	0	0
T43	0	41	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	88	0	0
T84	99239	0	0	0
T104	0	77	0	0
T105	0	50	0	0
T242	0	72	0	0
T243	0	62	0	0
T247	0	58	0	0
T277	0	27	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4496	0	0
T11	491074	13	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	34	0	0
T43	0	49	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	70	0	0
T84	99239	0	0	0
T104	0	80	0	0
T105	0	38	0	0
T242	0	75	0	0
T243	0	109	0	0
T247	0	65	0	0
T269	0	9	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1434	0	0
T17	0	33	0	0
T26	0	10	0	0
T27	0	15	0	0
T40	236781	0	0	0
T136	252556	0	0	0
T137	662151	0	0	0
T138	230566	0	0	0
T163	0	23	0	0
T177	0	16	0	0
T183	0	16	0	0
T236	0	19	0	0
T269	292038	9	0	0
T270	364110	0	0	0
T278	0	4	0	0
T279	0	12	0	0
T280	123802	0	0	0
T281	101762	0	0	0
T282	46585	0	0	0
T283	94902	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1451	0	0
T17	0	18	0	0
T26	0	16	0	0
T40	236781	0	0	0
T70	0	13	0	0
T136	252556	0	0	0
T137	662151	0	0	0
T138	230566	0	0	0
T163	0	25	0	0
T177	0	35	0	0
T183	0	24	0	0
T236	0	8	0	0
T269	292038	11	0	0
T270	364110	0	0	0
T278	0	18	0	0
T279	0	34	0	0
T280	123802	0	0	0
T281	101762	0	0	0
T282	46585	0	0	0
T283	94902	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1268	0	0
T17	0	15	0	0
T26	0	13	0	0
T27	0	3	0	0
T75	0	17	0	0
T109	228765	0	0	0
T163	0	16	0	0
T177	139715	23	0	0
T183	0	7	0	0
T236	0	12	0	0
T278	0	4	0	0
T279	0	23	0	0
T284	105798	0	0	0
T285	20477	0	0	0
T286	61953	0	0	0
T287	855196	0	0	0
T288	92142	0	0	0
T289	388983	0	0	0
T290	91554	0	0	0
T291	19421	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1337	0	0
T17	0	13	0	0
T26	0	7	0	0
T40	236781	0	0	0
T70	0	8	0	0
T136	252556	0	0	0
T137	662151	0	0	0
T138	230566	0	0	0
T163	0	20	0	0
T177	0	18	0	0
T183	0	15	0	0
T236	0	13	0	0
T269	292038	15	0	0
T270	364110	0	0	0
T278	0	11	0	0
T279	0	23	0	0
T280	123802	0	0	0
T281	101762	0	0	0
T282	46585	0	0	0
T283	94902	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4380	0	0
T11	491074	19	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	21	0	0
T43	0	51	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	55	0	0
T84	99239	0	0	0
T104	0	61	0	0
T105	0	34	0	0
T242	0	92	0	0
T243	0	66	0	0
T247	0	45	0	0
T269	0	18	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4738	0	0
T11	491074	24	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	33	0	0
T43	0	59	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	89	0	0
T84	99239	0	0	0
T104	0	73	0	0
T105	0	67	0	0
T242	0	76	0	0
T243	0	63	0	0
T247	0	77	0	0
T269	0	23	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4452	0	0
T11	491074	35	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	16	0	0
T43	0	37	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	94	0	0
T84	99239	0	0	0
T104	0	70	0	0
T105	0	59	0	0
T242	0	80	0	0
T243	0	76	0	0
T247	0	74	0	0
T269	0	6	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4606	0	0
T11	491074	24	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	33	0	0
T43	0	59	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	105	0	0
T84	99239	0	0	0
T104	0	68	0	0
T105	0	61	0	0
T242	0	54	0	0
T243	0	75	0	0
T247	0	55	0	0
T269	0	8	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4319	0	0
T11	491074	27	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	19	0	0
T43	0	57	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	71	0	0
T84	99239	0	0	0
T104	0	72	0	0
T105	0	58	0	0
T242	0	87	0	0
T243	0	67	0	0
T247	0	47	0	0
T269	0	16	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4395	0	0
T11	491074	28	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	43	0	0
T43	0	62	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	84	0	0
T84	99239	0	0	0
T104	0	44	0	0
T105	0	57	0	0
T242	0	80	0	0
T243	0	82	0	0
T247	0	70	0	0
T269	0	3	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4227	0	0
T11	491074	25	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	33	0	0
T43	0	40	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	75	0	0
T84	99239	0	0	0
T104	0	78	0	0
T105	0	44	0	0
T242	0	50	0	0
T243	0	65	0	0
T247	0	72	0	0
T269	0	8	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4491	0	0
T11	491074	12	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T30	194679	0	0	0
T31	0	31	0	0
T43	0	52	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	0	0	0
T66	0	87	0	0
T84	99239	0	0	0
T104	0	77	0	0
T105	0	79	0	0
T242	0	103	0	0
T243	0	76	0	0
T247	0	73	0	0
T269	0	5	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2383	0	0
T28	221703	0	0	0
T31	0	6	0	0
T33	591383	0	0	0
T43	0	5	0	0
T55	142501	1	0	0
T56	129446	0	0	0
T57	67374	0	0	0
T63	63461	0	0	0
T66	0	37	0	0
T84	99239	0	0	0
T85	36847	0	0	0
T104	0	41	0	0
T105	0	20	0	0
T141	204161	0	0	0
T142	29332	0	0	0
T242	0	34	0	0
T243	0	15	0	0
T247	0	58	0	0
T264	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2185	0	0
T40	236781	0	0	0
T136	252556	0	0	0
T137	662151	0	0	0
T138	230566	0	0	0
T163	0	23	0	0
T177	0	28	0	0
T183	0	28	0	0
T236	0	8	0	0
T269	292038	16	0	0
T270	364110	0	0	0
T278	0	13	0	0
T279	0	63	0	0
T280	123802	0	0	0
T281	101762	0	0	0
T282	46585	0	0	0
T283	94902	0	0	0
T292	0	16	0	0
T293	0	17	0	0
T294	0	29	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	3519	0	0
T5	231481	3	0	0
T6	113539	4	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	0	0	0
T23	131019	0	0	0
T33	0	2	0	0
T37	0	10	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T177	0	29	0	0
T180	0	1	0	0
T203	0	2	0	0
T236	0	15	0	0
T269	0	13	0	0
T292	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1373	0	0
T17	0	11	0	0
T26	0	10	0	0
T40	236781	0	0	0
T70	0	9	0	0
T136	252556	0	0	0
T137	662151	0	0	0
T138	230566	0	0	0
T163	0	37	0	0
T177	0	22	0	0
T183	0	17	0	0
T236	0	17	0	0
T269	292038	10	0	0
T270	364110	0	0	0
T278	0	13	0	0
T279	0	14	0	0
T280	123802	0	0	0
T281	101762	0	0	0
T282	46585	0	0	0
T283	94902	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4823	0	0
T22	59149	72	0	0
T31	235363	0	0	0
T34	378297	0	0	0
T41	739549	0	0	0
T42	286850	0	0	0
T43	321882	0	0	0
T44	165086	0	0	0
T58	61428	93	0	0
T177	0	90	0	0
T191	0	58	0	0
T236	0	2	0	0
T269	0	57	0	0
T273	202840	0	0	0
T274	131693	0	0	0
T295	0	73	0	0
T296	0	56	0	0
T297	0	33	0	0
T298	0	37	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	5344	0	0
T11	491074	0	0	0
T16	328847	0	0	0
T20	433141	60	0	0
T30	194679	0	0	0
T51	248418	71	0	0
T52	101414	0	0	0
T54	48266	53	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	58	0	0
T65	0	92	0	0
T269	0	8	0	0
T292	0	52	0	0
T299	0	88	0	0
T300	0	87	0	0
T301	0	83	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4140	0	0
T11	491074	0	0	0
T16	328847	0	0	0
T20	433141	91	0	0
T30	194679	0	0	0
T51	248418	73	0	0
T52	101414	0	0	0
T54	48266	28	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	55	0	0
T65	0	62	0	0
T269	0	8	0	0
T292	0	45	0	0
T299	0	57	0	0
T300	0	55	0	0
T301	0	73	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	4283	0	0
T11	491074	0	0	0
T16	328847	0	0	0
T20	433141	68	0	0
T30	194679	0	0	0
T51	248418	63	0	0
T52	101414	0	0	0
T54	48266	73	0	0
T55	142501	0	0	0
T56	129446	0	0	0
T63	63461	51	0	0
T65	0	67	0	0
T269	0	3	0	0
T292	0	61	0	0
T299	0	71	0	0
T300	0	62	0	0
T301	0	61	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1910	0	0
T17	0	21	0	0
T26	0	12	0	0
T40	236781	0	0	0
T70	0	4	0	0
T136	252556	0	0	0
T137	662151	0	0	0
T138	230566	0	0	0
T163	0	36	0	0
T177	0	13	0	0
T183	0	6	0	0
T236	0	8	0	0
T269	292038	2	0	0
T270	364110	0	0	0
T278	0	3	0	0
T279	0	34	0	0
T280	123802	0	0	0
T281	101762	0	0	0
T282	46585	0	0	0
T283	94902	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1534	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T13	50407	3	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	6	0	0
T23	131019	0	0	0
T50	52445	6	0	0
T97	0	7	0	0
T136	0	5	0	0
T138	0	9	0	0
T177	0	11	0	0
T269	0	5	0	0
T302	0	3	0	0
T303	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1453	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T13	50407	1	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	2	0	0
T23	131019	0	0	0
T50	52445	9	0	0
T97	0	4	0	0
T136	0	4	0	0
T138	0	8	0	0
T177	0	19	0	0
T269	0	4	0	0
T302	0	5	0	0
T303	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1542	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T13	50407	1	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T23	131019	0	0	0
T50	52445	2	0	0
T97	0	7	0	0
T136	0	3	0	0
T138	0	3	0	0
T177	0	23	0	0
T236	0	9	0	0
T269	0	14	0	0
T302	0	2	0	0
T303	0	14	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1562	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T13	50407	6	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	3	0	0
T23	131019	0	0	0
T50	52445	10	0	0
T97	0	12	0	0
T136	0	12	0	0
T138	0	4	0	0
T177	0	10	0	0
T236	0	13	0	0
T269	0	13	0	0
T303	0	5	0	0