Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T12,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T12,T3
1	1	Covered	T4,T12,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T12,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T12,T3
1	1	Covered	T4,T12,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T20
1	-	Covered	T4,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T12,T13
0	0	1	Covered	T4,T12,T13
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T12,T13
0	0	1	Covered	T4,T12,T13
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	117670301	0	0
DstReqKnown_A	266610082	237365084	0	0
SrcAckBusyChk_A	2147483647	119665	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117670301	0	0
T1	80464	0	0	0
T2	138972	0	0	0
T3	554199	0	0	0
T5	1157405	0	0	0
T6	567695	0	0	0
T7	7937400	146836	0	0
T8	7473988	0	0	0
T9	17302532	5047	0	0
T10	21064481	2805	0	0
T11	10312554	17152	0	0
T12	1028313	0	0	0
T13	151221	0	0	0
T14	1807980	8877	0	0
T15	774495	5097	0	0
T16	6905787	21525	0	0
T20	433141	0	0	0
T23	3013437	0	0	0
T30	194679	224568	0	0
T31	0	19889	0	0
T32	0	20757	0	0
T34	0	21573	0	0
T36	0	7236	0	0
T41	0	81881	0	0
T42	0	11384	0	0
T43	0	16615	0	0
T44	0	127744	0	0
T45	0	7752	0	0
T46	0	373	0	0
T47	0	3842	0	0
T48	0	5008	0	0
T49	0	3751	0	0
T50	1206235	0	0	0
T51	5216778	0	0	0
T52	2129694	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266610082	237365084	0	0
T1	1850688	1837088	0	0
T2	19652	6052	0	0
T3	52326	11526	0	0
T4	28968	15368	0	0
T5	24922	11322	0	0
T6	33524	19924	0	0
T12	24514	10914	0	0
T13	17000	3400	0	0
T14	24820	11220	0	0
T15	21454	7854	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119665	0	0
T1	80464	0	0	0
T2	138972	0	0	0
T3	554199	0	0	0
T5	1157405	0	0	0
T6	567695	0	0	0
T7	7937400	84	0	0
T8	7473988	0	0	0
T9	17302532	53	0	0
T10	21064481	2	0	0
T11	10312554	9	0	0
T12	1028313	0	0	0
T13	151221	0	0	0
T14	1807980	6	0	0
T15	774495	6	0	0
T16	6905787	27	0	0
T20	433141	0	0	0
T23	3013437	0	0	0
T30	194679	136	0	0
T31	0	54	0	0
T32	0	27	0	0
T34	0	12	0	0
T36	0	8	0	0
T41	0	104	0	0
T42	0	7	0	0
T43	0	9	0	0
T44	0	84	0	0
T45	0	7	0	0
T46	0	1	0	0
T47	0	10	0	0
T48	0	7	0	0
T49	0	9	0	0
T50	1206235	0	0	0
T51	5216778	0	0	0
T52	2129694	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1367888	1366120	0	0
T2	2362524	2359770	0	0
T3	6280922	6275006	0	0
T4	7198990	7196304	0	0
T5	7870354	7868654	0	0
T6	3860326	3858048	0	0
T12	11654214	11652378	0	0
T13	1713838	1711526	0	0
T14	12294264	12290898	0	0
T15	5266566	5263676	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T9,T11,T16
1	1	Covered	T7,T9,T11

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T7,T34,T17
1	-	Covered	T9,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T9,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T9,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1191386	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1238	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1191386	0	0
T7	317496	1281	0	0
T8	324956	0	0	0
T9	752284	289	0	0
T10	915847	0	0	0
T11	491074	1964	0	0
T16	328847	5124	0	0
T20	0	618	0	0
T23	131019	0	0	0
T28	0	1844	0	0
T29	0	789	0	0
T30	0	18680	0	0
T32	0	1748	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T53	0	825	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1238	0	0
T9	752284	3	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	6	0	0
T20	433141	1	0	0
T23	131019	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	194679	11	0	0
T32	0	2	0	0
T41	0	6	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T53	0	2	0	0
T54	48266	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T12,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T12,T7,T9
1	1	Covered	T12,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T12,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T7,T9
1	1	Covered	T12,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T12,T7,T9
0	0	1	Covered	T12,T7,T9
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T12,T7,T9
0	0	1	Covered	T12,T7,T9
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	2001068	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	2019	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2001068	0	0
T3	184733	0	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	1485	0	0
T8	324956	0	0	0
T9	0	983	0	0
T10	0	1390	0	0
T11	0	1811	0	0
T12	342771	1898	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T16	0	2331	0	0
T30	0	27918	0	0
T32	0	2081	0	0
T50	52445	0	0	0
T55	0	692	0	0
T56	0	938	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2019	0	0
T3	184733	0	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	1	0	0
T8	324956	0	0	0
T9	0	11	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	342771	1	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T16	0	3	0	0
T30	0	17	0	0
T32	0	3	0	0
T50	52445	0	0	0
T55	0	1	0	0
T56	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T13,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T13,T7
1	1	Covered	T4,T13,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T13,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T7
1	1	Covered	T4,T13,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T13,T7
0	0	1	Covered	T4,T13,T7
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T13,T7
0	0	1	Covered	T4,T13,T7
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1177681	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1043	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1177681	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	4763	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	1485	0	0
T9	0	89	0	0
T12	342771	0	0	0
T13	50407	471	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	670	0	0
T28	0	5138	0	0
T29	0	1143	0	0
T50	0	986	0	0
T53	0	1185	0	0
T57	0	959	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1043	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	3	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	342771	0	0	0
T13	50407	1	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	1	0	0
T28	0	3	0	0
T29	0	3	0	0
T50	0	2	0	0
T53	0	3	0	0
T57	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T13,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T13,T7
1	1	Covered	T4,T13,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T13,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T7
1	1	Covered	T4,T13,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T13,T7
0	0	1	Covered	T4,T13,T7
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T13,T7
0	0	1	Covered	T4,T13,T7
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1185836	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1054	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1185836	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	4729	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	1483	0	0
T9	0	87	0	0
T12	342771	0	0	0
T13	50407	456	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	651	0	0
T28	0	5115	0	0
T29	0	1137	0	0
T50	0	968	0	0
T53	0	1179	0	0
T57	0	955	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1054	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	3	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	342771	0	0	0
T13	50407	1	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	1	0	0
T28	0	3	0	0
T29	0	3	0	0
T50	0	2	0	0
T53	0	3	0	0
T57	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T13,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T13,T7
1	1	Covered	T4,T13,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T13,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T7
1	1	Covered	T4,T13,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T13,T7
0	0	1	Covered	T4,T13,T7
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T13,T7
0	0	1	Covered	T4,T13,T7
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1219267	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1062	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1219267	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	4705	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	1481	0	0
T9	0	85	0	0
T12	342771	0	0	0
T13	50407	441	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	643	0	0
T28	0	5095	0	0
T29	0	1131	0	0
T50	0	948	0	0
T53	0	1173	0	0
T57	0	951	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1062	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	3	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	342771	0	0	0
T13	50407	1	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	1	0	0
T28	0	3	0	0
T29	0	3	0	0
T50	0	2	0	0
T53	0	3	0	0
T57	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T9,T21,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T9,T21,T22
1	1	Covered	T9,T21,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T9,T21,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T21,T22
1	1	Covered	T9,T21,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T9,T21,T22
0	0	1	Covered	T9,T21,T22
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T9,T21,T22
0	0	1	Covered	T9,T21,T22
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	2764313	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	3114	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2764313	0	0
T9	752284	6306	0	0
T10	915847	0	0	0
T11	491074	0	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T21	0	16320	0	0
T22	0	7793	0	0
T23	131019	0	0	0
T30	194679	0	0	0
T35	0	67131	0	0
T36	0	35763	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T58	0	8116	0	0
T59	0	22667	0	0
T60	0	34303	0	0
T61	0	34442	0	0
T62	0	35506	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	3114	0	0
T9	752284	60	0	0
T10	915847	0	0	0
T11	491074	0	0	0
T16	328847	0	0	0
T20	433141	0	0	0
T21	0	20	0	0
T22	0	20	0	0
T23	131019	0	0	0
T30	194679	0	0	0
T35	0	40	0	0
T36	0	40	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T54	48266	0	0	0
T58	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T3,T9,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T3,T9,T23
1	1	Covered	T3,T9,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T3,T9,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T9,T23
1	1	Covered	T3,T9,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T3,T9,T23
0	0	1	Covered	T3,T9,T23
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T3,T9,T23
0	0	1	Covered	T3,T9,T23
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	5615448	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	6510	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	5615448	0	0
T3	184733	8447	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	8492	0	0
T10	0	68383	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	30025	0	0
T23	0	16627	0	0
T50	52445	0	0	0
T51	0	35138	0	0
T54	0	5753	0	0
T63	0	8589	0	0
T64	0	16496	0	0
T65	0	16167	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	6510	0	0
T3	184733	20	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	83	0	0
T10	0	40	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	40	0	0
T23	0	20	0	0
T50	52445	0	0	0
T51	0	20	0	0
T54	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T3,T7
1	1	Covered	T12,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T12,T3,T7
0	0	1	Covered	T12,T3,T7
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	6715030	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	7687	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	6715030	0	0
T3	184733	8527	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	1481	0	0
T8	324956	0	0	0
T9	0	9890	0	0
T10	0	70338	0	0
T11	0	1990	0	0
T12	342771	1900	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T16	0	2441	0	0
T23	0	16934	0	0
T30	0	28273	0	0
T50	52445	0	0	0
T51	0	35544	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7687	0	0
T3	184733	20	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	1	0	0
T8	324956	0	0	0
T9	0	95	0	0
T10	0	41	0	0
T11	0	1	0	0
T12	342771	1	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T16	0	3	0	0
T23	0	20	0	0
T30	0	17	0	0
T50	52445	0	0	0
T51	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T3,T9,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T3,T9,T23
1	1	Covered	T3,T9,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T3,T9,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T9,T23
1	1	Covered	T3,T9,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T3,T9,T23
0	0	1	Covered	T3,T9,T23
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T3,T9,T23
0	0	1	Covered	T3,T9,T23
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	5551951	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	6402	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	5551951	0	0
T3	184733	8487	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	8307	0	0
T10	0	68671	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	30447	0	0
T23	0	16763	0	0
T50	52445	0	0	0
T51	0	35312	0	0
T54	0	5897	0	0
T63	0	8828	0	0
T64	0	16536	0	0
T65	0	16367	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	6402	0	0
T3	184733	20	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	0	0	0
T8	324956	0	0	0
T9	752284	80	0	0
T10	0	40	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	40	0	0
T23	0	20	0	0
T50	52445	0	0	0
T51	0	20	0	0
T54	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1240115	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1074	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1240115	0	0
T1	40232	247	0	0
T2	69486	476	0	0
T3	184733	359	0	0
T5	231481	1960	0	0
T6	113539	516	0	0
T7	317496	48468	0	0
T8	0	1940	0	0
T9	0	86	0	0
T12	342771	0	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T33	0	96	0	0
T39	0	982	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1074	0	0
T1	40232	1	0	0
T2	69486	1	0	0
T3	184733	1	0	0
T5	231481	1	0	0
T6	113539	1	0	0
T7	317496	28	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	342771	0	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T33	0	1	0	0
T39	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	2024252	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	2037	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2024252	0	0
T1	40232	236	0	0
T2	69486	466	0	0
T3	184733	357	0	0
T5	231481	1955	0	0
T6	113539	502	0	0
T7	317496	3454	0	0
T8	0	1927	0	0
T9	0	714	0	0
T10	0	1384	0	0
T11	0	1799	0	0
T12	342771	0	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2037	0	0
T1	40232	1	0	0
T2	69486	1	0	0
T3	184733	1	0	0
T5	231481	1	0	0
T6	113539	1	0	0
T7	317496	2	0	0
T8	0	1	0	0
T9	0	8	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	342771	0	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T14,T15,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T14,T15,T7
1	1	Covered	T14,T15,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T14,T15,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T15,T7
1	1	Covered	T14,T15,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T14,T15,T7
0	0	1	Covered	T14,T15,T7
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T14,T15,T7
0	0	1	Covered	T14,T15,T7
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1493410	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1442	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1493410	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	3466	0	0
T8	324956	0	0	0
T9	752284	624	0	0
T10	915847	0	0	0
T14	361596	4450	0	0
T15	154899	3412	0	0
T23	131019	0	0	0
T34	0	3361	0	0
T36	0	4496	0	0
T42	0	6588	0	0
T45	0	4432	0	0
T48	0	2975	0	0
T49	0	2463	0	0
T50	52445	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1442	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	2	0	0
T8	324956	0	0	0
T9	752284	6	0	0
T10	915847	0	0	0
T14	361596	3	0	0
T15	154899	4	0	0
T23	131019	0	0	0
T34	0	2	0	0
T36	0	5	0	0
T42	0	4	0	0
T45	0	4	0	0
T48	0	4	0	0
T49	0	6	0	0
T50	52445	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T14,T15,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T14,T15,T7
1	1	Covered	T14,T15,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T14,T15,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T15,T7
1	1	Covered	T14,T15,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T14,T15,T7
0	0	1	Covered	T14,T15,T7
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T14,T15,T7
0	0	1	Covered	T14,T15,T7
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1287242	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1218	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1287242	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	1485	0	0
T8	324956	0	0	0
T9	752284	287	0	0
T10	915847	0	0	0
T14	361596	4427	0	0
T15	154899	1685	0	0
T23	131019	0	0	0
T34	0	1921	0	0
T36	0	2740	0	0
T42	0	4796	0	0
T45	0	3320	0	0
T48	0	2033	0	0
T49	0	1288	0	0
T50	52445	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1218	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	317496	1	0	0
T8	324956	0	0	0
T9	752284	3	0	0
T10	915847	0	0	0
T14	361596	3	0	0
T15	154899	2	0	0
T23	131019	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T42	0	3	0	0
T45	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	52445	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	7484924	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	7446	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7484924	0	0
T7	317496	19293	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	124812	0	0
T16	328847	65920	0	0
T23	131019	0	0	0
T31	0	36799	0	0
T32	0	71157	0	0
T34	0	19670	0	0
T43	0	91834	0	0
T46	0	24645	0	0
T47	0	37786	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	10730	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7446	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	73	0	0
T16	328847	78	0	0
T23	131019	0	0	0
T31	0	89	0	0
T32	0	80	0	0
T34	0	11	0	0
T43	0	55	0	0
T46	0	57	0	0
T47	0	93	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	67	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	7663316	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	7616	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7663316	0	0
T7	317496	19287	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	134015	0	0
T16	328847	67331	0	0
T23	131019	0	0	0
T31	0	31116	0	0
T32	0	57172	0	0
T34	0	19663	0	0
T43	0	107246	0	0
T46	0	37019	0	0
T47	0	33498	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	8988	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7616	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	79	0	0
T16	328847	80	0	0
T23	131019	0	0	0
T31	0	79	0	0
T32	0	65	0	0
T34	0	11	0	0
T43	0	65	0	0
T46	0	86	0	0
T47	0	85	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	60	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	7461350	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	7591	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7461350	0	0
T7	317496	19287	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	106668	0	0
T16	328847	63369	0	0
T23	131019	0	0	0
T31	0	33018	0	0
T32	0	59209	0	0
T34	0	19662	0	0
T43	0	89624	0	0
T46	0	34502	0	0
T47	0	29459	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	9626	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7591	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	64	0	0
T16	328847	76	0	0
T23	131019	0	0	0
T31	0	87	0	0
T32	0	68	0	0
T34	0	11	0	0
T43	0	55	0	0
T46	0	81	0	0
T47	0	77	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	60	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	7359712	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	7507	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7359712	0	0
T7	317496	19287	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	103974	0	0
T16	328847	48839	0	0
T23	131019	0	0	0
T31	0	24551	0	0
T32	0	67792	0	0
T34	0	19663	0	0
T43	0	104547	0	0
T46	0	33869	0	0
T47	0	26582	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	10475	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7507	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	63	0	0
T16	328847	58	0	0
T23	131019	0	0	0
T31	0	65	0	0
T32	0	79	0	0
T34	0	11	0	0
T43	0	65	0	0
T46	0	80	0	0
T47	0	72	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	69	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1374553	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1264	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1374553	0	0
T7	317496	15809	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1994	0	0
T16	328847	2445	0	0
T23	131019	0	0	0
T31	0	2415	0	0
T32	0	2503	0	0
T34	0	16291	0	0
T43	0	1950	0	0
T46	0	373	0	0
T47	0	3842	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	1510	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1264	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T31	0	6	0	0
T32	0	3	0	0
T34	0	9	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	10	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1358926	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1268	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1358926	0	0
T7	317496	15803	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1935	0	0
T16	328847	2415	0	0
T23	131019	0	0	0
T31	0	2139	0	0
T32	0	2395	0	0
T34	0	16284	0	0
T43	0	1884	0	0
T46	0	363	0	0
T47	0	3527	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	1481	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1268	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T31	0	6	0	0
T32	0	3	0	0
T34	0	9	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	10	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1386466	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1265	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1386466	0	0
T7	317496	15803	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1892	0	0
T16	328847	2385	0	0
T23	131019	0	0	0
T31	0	2106	0	0
T32	0	2299	0	0
T34	0	16283	0	0
T43	0	1820	0	0
T46	0	353	0	0
T47	0	3167	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	1430	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1265	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T31	0	6	0	0
T32	0	3	0	0
T34	0	9	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	10	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T11,T16
1	1	Covered	T7,T11,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T11,T16
0	0	1	Covered	T7,T11,T16
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1386855	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1283	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1386855	0	0
T7	317496	15803	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1860	0	0
T16	328847	2355	0	0
T23	131019	0	0	0
T31	0	2291	0	0
T32	0	2169	0	0
T34	0	16284	0	0
T43	0	1774	0	0
T46	0	343	0	0
T47	0	3292	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	1521	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1283	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	0	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T31	0	6	0	0
T32	0	3	0	0
T34	0	9	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	10	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0
T66	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	8157798	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	8108	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8157798	0	0
T7	317496	19257	0	0
T8	324956	0	0	0
T9	752284	745	0	0
T10	915847	1413	0	0
T11	491074	125470	0	0
T16	328847	66058	0	0
T23	131019	0	0	0
T30	0	28326	0	0
T31	0	37453	0	0
T32	0	71625	0	0
T41	0	10949	0	0
T43	0	92337	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8108	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	7	0	0
T10	915847	1	0	0
T11	491074	73	0	0
T16	328847	78	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	89	0	0
T32	0	80	0	0
T41	0	13	0	0
T43	0	55	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	8219936	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	8179	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8219936	0	0
T7	317496	19251	0	0
T8	324956	0	0	0
T9	752284	533	0	0
T10	915847	0	0	0
T11	491074	134690	0	0
T16	328847	67473	0	0
T23	131019	0	0	0
T30	0	28292	0	0
T31	0	31669	0	0
T32	0	57555	0	0
T41	0	10852	0	0
T43	0	107891	0	0
T44	0	21898	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8179	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	79	0	0
T16	328847	80	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	79	0	0
T32	0	65	0	0
T41	0	13	0	0
T43	0	65	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	8026696	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	8171	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8026696	0	0
T7	317496	19251	0	0
T8	324956	0	0	0
T9	752284	523	0	0
T10	915847	0	0	0
T11	491074	107288	0	0
T16	328847	63503	0	0
T23	131019	0	0	0
T30	0	28258	0	0
T31	0	34132	0	0
T32	0	59647	0	0
T41	0	10764	0	0
T43	0	90178	0	0
T44	0	21816	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8171	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	64	0	0
T16	328847	76	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	87	0	0
T32	0	68	0	0
T41	0	13	0	0
T43	0	55	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	7892060	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	8061	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	7892060	0	0
T7	317496	19251	0	0
T8	324956	0	0	0
T9	752284	513	0	0
T10	915847	0	0	0
T11	491074	104503	0	0
T16	328847	48937	0	0
T23	131019	0	0	0
T30	0	28224	0	0
T31	0	24900	0	0
T32	0	68261	0	0
T41	0	10665	0	0
T43	0	105264	0	0
T44	0	21725	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	8061	0	0
T7	317496	11	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	63	0	0
T16	328847	58	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	65	0	0
T32	0	79	0	0
T41	0	13	0	0
T43	0	65	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	2028949	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1960	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	2028949	0	0
T7	317496	15773	0	0
T8	324956	0	0	0
T9	752284	701	0	0
T10	915847	1408	0	0
T11	491074	1971	0	0
T16	328847	2433	0	0
T23	131019	0	0	0
T30	0	28190	0	0
T31	0	2303	0	0
T32	0	2450	0	0
T41	0	10544	0	0
T43	0	1925	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1960	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	7	0	0
T10	915847	1	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1874733	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1816	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1874733	0	0
T7	317496	15767	0	0
T8	324956	0	0	0
T9	752284	493	0	0
T10	915847	0	0	0
T11	491074	1912	0	0
T16	328847	2403	0	0
T23	131019	0	0	0
T30	0	28156	0	0
T31	0	2019	0	0
T32	0	2353	0	0
T41	0	10453	0	0
T43	0	1867	0	0
T44	0	21559	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1816	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1907233	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1864	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1907233	0	0
T7	317496	15767	0	0
T8	324956	0	0	0
T9	752284	483	0	0
T10	915847	0	0	0
T11	491074	1882	0	0
T16	328847	2373	0	0
T23	131019	0	0	0
T30	0	28122	0	0
T31	0	2340	0	0
T32	0	2235	0	0
T41	0	10371	0	0
T43	0	1803	0	0
T44	0	21465	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1864	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1877376	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1868	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1877376	0	0
T7	317496	15767	0	0
T8	324956	0	0	0
T9	752284	473	0	0
T10	915847	0	0	0
T11	491074	1834	0	0
T16	328847	2343	0	0
T23	131019	0	0	0
T30	0	28088	0	0
T31	0	2194	0	0
T32	0	2128	0	0
T41	0	10284	0	0
T43	0	1761	0	0
T44	0	21389	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1868	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1952972	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1912	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1952972	0	0
T7	317496	15755	0	0
T8	324956	0	0	0
T9	752284	657	0	0
T10	915847	1397	0	0
T11	491074	1956	0	0
T16	328847	2427	0	0
T23	131019	0	0	0
T30	0	28054	0	0
T31	0	2242	0	0
T32	0	2425	0	0
T41	0	10203	0	0
T43	0	1907	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1912	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	7	0	0
T10	915847	1	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1922856	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1883	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1922856	0	0
T7	317496	15749	0	0
T8	324956	0	0	0
T9	752284	453	0	0
T10	915847	0	0	0
T11	491074	1903	0	0
T16	328847	2397	0	0
T23	131019	0	0	0
T30	0	28020	0	0
T31	0	1957	0	0
T32	0	2338	0	0
T41	0	10088	0	0
T43	0	1851	0	0
T44	0	21188	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1883	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1864654	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1845	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1864654	0	0
T7	317496	15749	0	0
T8	324956	0	0	0
T9	752284	443	0	0
T10	915847	0	0	0
T11	491074	1874	0	0
T16	328847	2367	0	0
T23	131019	0	0	0
T30	0	27986	0	0
T31	0	2284	0	0
T32	0	2217	0	0
T41	0	10008	0	0
T43	0	1799	0	0
T44	0	21112	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1845	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1824814	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1817	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1824814	0	0
T7	317496	15749	0	0
T8	324956	0	0	0
T9	752284	433	0	0
T10	915847	0	0	0
T11	491074	1826	0	0
T16	328847	2337	0	0
T23	131019	0	0	0
T30	0	27952	0	0
T31	0	2135	0	0
T32	0	2108	0	0
T41	0	9930	0	0
T43	0	1752	0	0
T44	0	21031	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1817	0	0
T7	317496	9	0	0
T8	324956	0	0	0
T9	752284	5	0	0
T10	915847	0	0	0
T11	491074	1	0	0
T16	328847	3	0	0
T23	131019	0	0	0
T30	0	17	0	0
T31	0	6	0	0
T32	0	3	0	0
T41	0	13	0	0
T43	0	1	0	0
T44	0	14	0	0
T50	52445	0	0	0
T51	248418	0	0	0
T52	101414	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T7,T20

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T7,T20
1	1	Covered	T4,T7,T20

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T20
1	-	Covered	T4,T7,T20

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T7,T20

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T20
1	1	Covered	T4,T7,T20

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T7,T20
0	0	1	Covered	T4,T7,T20
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T7,T20
0	0	1	Covered	T4,T7,T20
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1198461200	1177123	0	0
DstReqKnown_A	7841473	6981326	0	0
SrcAckBusyChk_A	1198461200	1041	0	0
SrcBusyKnown_A	1198461200	1196651741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1177123	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	2873	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	5931	0	0
T12	342771	0	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	1310	0	0
T28	0	3731	0	0
T29	0	1480	0	0
T34	0	6209	0	0
T45	0	2210	0	0
T53	0	1539	0	0
T67	0	392	0	0
T68	0	831	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7841473	6981326	0	0
T1	54432	54032	0	0
T2	578	178	0	0
T3	1539	339	0	0
T4	852	452	0	0
T5	733	333	0	0
T6	986	586	0	0
T12	721	321	0	0
T13	500	100	0	0
T14	730	330	0	0
T15	631	231	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1041	0	0
T1	40232	0	0	0
T2	69486	0	0	0
T3	184733	0	0	0
T4	211735	2	0	0
T5	231481	0	0	0
T6	113539	0	0	0
T7	0	4	0	0
T12	342771	0	0	0
T13	50407	0	0	0
T14	361596	0	0	0
T15	154899	0	0	0
T20	0	2	0	0
T28	0	2	0	0
T29	0	4	0	0
T34	0	3	0	0
T45	0	2	0	0
T53	0	4	0	0
T67	0	1	0	0
T68	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198461200	1196651741	0	0
T1	40232	40180	0	0
T2	69486	69405	0	0
T3	184733	184559	0	0
T4	211735	211656	0	0
T5	231481	231431	0	0
T6	113539	113472	0	0
T12	342771	342717	0	0
T13	50407	50339	0	0
T14	361596	361497	0	0
T15	154899	154814	0	0