Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1973

1

T2

52

T6

6

T22

12

auto[1]

716

1

T3

8

T6

24

T22

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2150

1

T2

46

T3

2

T6

18

auto[1]

539

1

T2

6

T3

6

T6

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T2

36

T3

5

T6

20

auto[1]

654

1

T2

16

T3

3

T6

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1996

1

T2

42

T3

6

T6

22

auto[1]

693

1

T2

10

T3

2

T6

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2475

1

T2

46

T3

8

T6

30

auto[1]

214

1

T2

6

T31

6

T41

17

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2418

1

T2

46

T3

8

T6

30

auto[1]

271

1

T2

6

T31

4

T41

18

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2486

1

T2

50

T3

8

T6

30

auto[1]

203

1

T2

2

T39

2

T31

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2458

1

T2

38

T3

8

T6

30

auto[1]

231

1

T2

14

T31

3

T69

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2460

1

T2

42

T3

8

T6

30

auto[1]

229

1

T2

10

T31

2

T69

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1986

1

T2

40

T3

3

T6

12

auto[1]

703

1

T2

12

T3

5

T6

18

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	983	1			T3	8		T6	29		T22	24
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	54	1			T41	11		T69	4		T225	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	63	1			T30	8		T229	8		T224	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	24	1			T2	4		T31	2		T90	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	53	1			T2	12		T31	1		T229	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	36	1			T30	7		T238	4		T152	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	35	1			T88	9		T233	3		T343	8
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T344	2		T333	4		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	50	1			T39	2		T122	1		T123	7
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	20	1			T30	4		T152	5		T226	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	28	1			T123	3		T228	9		T345	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T333	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	15	1			T123	4		T229	3		T135	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T2	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T333	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T69	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	108	1			T41	12		T228	10		T346	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	10	1			T69	2		T347	2		T348	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	10	1			T2	6		T76	1		T349	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T333	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	40	1			T152	3		T343	4		T226	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T328	5		T347	2		T344	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	12	1			T180	4		T350	1		T351	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	6	1			T225	1		T352	1		T76	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	11	1			T31	3		T41	6		T350	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	13	1			T353	1		T337	2		T354	4
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	8	1			T180	5		T337	2		T355	1
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T356	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

140

1

T88

9

T269

12

T349

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

105

1

T41

6

T35

3

T148

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

69

1

T6

10

T22

5

T48

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

119

1

T2

6

T22

12

T31

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

82

1

T6

5

T22

5

T228

11

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

86

1

T48

3

T31

3

T228

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T3

2

T122

1

T107

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

131

1

T6

2

T29

8

T235

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

72

1

T104

1

T228

10

T234

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

95

1

T2

12

T31

1

T69

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

55

1

T6

1

T92

2

T329

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

66

1

T41

12

T235

3

T180

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T28

5

T235

2

T346

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T69

4

T29

3

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T153

3

T328

6

T98

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

108

1

T2

2

T69

2

T234

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

50

1

T6

5

T22

2

T48

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T28

8

T39

2

T86

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T3

3

T28

3

T239

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T123

3

T228

9

T346

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T123

7

T153

4

T330

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T41

11

T30

2

T225

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T238

4

T352

3

T357

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

31

1

T329

7

T344

2

T333

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T3

3

T30

8

T230

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T6

3

T87

4

T38

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T347

2

T358

2

T241

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T2

4

T86

2

T239

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T139

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T6

1

T148

1

T303

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T6

2

T359

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded