Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T6

13

T63

12

T65

11

auto[1]

1047

1

T6

7

T63

8

T65

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T6

5

T63

4

T65

4

from_0to1

500

1

T6

4

T63

5

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T6

10

T63

11

T65

10

auto[1]

1071

1

T6

10

T63

9

T65

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T6

8

T63

9

T65

6

auto[1]

1130

1

T6

12

T63

11

T65

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T6

1

T63

1

T22

3

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T63

1

T65

2

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T6

1

T63

1

T22

3

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T65

1

T22

3

T367

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T65

1

T22

1

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T63

1

T22

3

T125

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T6

2

T22

4

T125

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T63

1

T22

4

T367

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T6

1

T63

1

T22

3

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T6

1

T65

1

T367

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T22

1

T367

1

T35

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T6

1

T22

2

T35

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T22

2

T35

1

T284

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T6

1

T63

2

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T6

1

T63

1

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T65

2

T22

1

T367

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T6

12

T63

11

T65

5

auto[1]

1101

1

T6

8

T63

9

T65

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T6

5

T63

4

T65

3

from_0to1

505

1

T6

5

T63

4

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T6

11

T63

9

T65

9

auto[1]

1095

1

T6

9

T63

11

T65

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T6

7

T63

8

T65

13

auto[1]

1092

1

T6

13

T63

12

T65

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T6

1

T65

1

T22

3

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T6

2

T63

1

T22

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T63

1

T22

1

T367

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T6

1

T63

1

T22

3

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T65

1

T35

1

T129

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T6

1

T22

4

T367

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T6

2

T63

2

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T63

1

T22

1

T367

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T22

2

T367

1

T125

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T6

1

T63

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T65

1

T22

2

T125

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T65

1

T22

3

T35

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T6

1

T63

1

T22

3

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T65

2

T22

1

T367

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T367

1

T35

1

T284

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T6

1

T22

5

T367

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T6

8

T63

9

T65

13

auto[1]

1053

1

T6

12

T63

11

T65

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T6

5

T63

4

T65

4

from_0to1

508

1

T6

6

T63

5

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T6

9

T63

7

T65

7

auto[1]

1130

1

T6

11

T63

13

T65

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T6

11

T63

8

T65

7

auto[1]

1071

1

T6

9

T63

12

T65

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T63

1

T65

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T6

2

T65

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T65

1

T22

4

T35

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T63

1

T65

1

T22

4

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T35

1

T129

2

T284

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T65

1

T22

1

T367

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T6

1

T22

4

T367

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T6

1

T63

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T6

1

T22

3

T367

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T63

1

T367

1

T35

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T22

1

T367

1

T120

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T6

2

T63

1

T22

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T6

3

T63

2

T22

3

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T65

1

T22

1

T367

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T63

2

T22

1

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T6

1

T65

1

T22

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T6

11

T63

10

T65

9

auto[1]

1080

1

T6

9

T63

10

T65

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T6

5

T63

5

T65

5

from_0to1

502

1

T6

6

T63

5

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T6

5

T63

8

T65

7

auto[1]

1084

1

T6

15

T63

12

T65

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T6

6

T63

12

T65

8

auto[1]

1083

1

T6

14

T63

8

T65

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T63

1

T22

1

T367

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T65

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T6

1

T63

1

T22

3

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T6

2

T63

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T65

1

T22

3

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T63

1

T22

2

T367

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T6

1

T63

3

T22

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T6

1

T22

1

T367

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T65

1

T22

2

T367

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T22

2

T35

2

T284

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T6

1

T63

2

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T65

1

T22

1

T367

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T22

1

T125

1

T284

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T63

1

T65

2

T22

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T6

2

T35

3

T119

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T6

2

T65

2

T22

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T6

11

T63

7

T65

12

auto[1]

1063

1

T6

9

T63

13

T65

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T6

5

T63

3

T65

3

from_0to1

501

1

T6

5

T63

3

T65

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T6

11

T63

7

T65

13

auto[1]

1031

1

T6

9

T63

13

T65

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T6

13

T63

8

T65

11

auto[1]

1050

1

T6

7

T63

12

T65

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T6

1

T65

1

T22

3

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T63

1

T22

1

T129

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T6

1

T22

2

T367

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T63

1

T65

1

T125

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T65

2

T22

2

T125

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T6

1

T63

1

T22

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T6

1

T63

1

T22

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T6

1

T65

1

T22

2

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T6

1

T22

4

T35

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T6

1

T22

4

T367

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T6

1

T35

1

T284

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T63

1

T65

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T6

1

T22

3

T367

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T22

1

T125

1

T120

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T6

1

T63

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T22

2

T125

1

T129

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T6

10

T63

10

T65

13

auto[1]

1059

1

T6

10

T63

10

T65

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T6

5

T63

2

T65

5

from_0to1

527

1

T6

4

T63

3

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T6

11

T63

9

T65

7

auto[1]

1056

1

T6

9

T63

11

T65

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T6

10

T63

8

T65

13

auto[1]

1074

1

T6

10

T63

12

T65

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T22

2

T367

1

T125

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T6

1

T65

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T65

1

T22

1

T367

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T65

2

T22

4

T125

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T6

1

T65

1

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T63

1

T22

1

T367

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T65

1

T22

3

T367

3

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T63

1

T22

1

T35

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T63

2

T22

1

T125

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T22

4

T367

1

T125

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T6

3

T367

2

T125

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T6

1

T65

1

T22

3

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T6

2

T125

1

T35

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T6

1

T63

1

T22

2

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T65

3

T22

7

T367

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T22

1

T125

1

T119

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T6

11

T63

6

T65

9

auto[1]

1097

1

T6

9

T63

14

T65

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T6

5

T63

3

T65

5

from_0to1

513

1

T6

4

T63

4

T65

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T6

12

T63

9

T65

9

auto[1]

1113

1

T6

8

T63

11

T65

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T6

12

T63

10

T65

11

auto[1]

982

1

T6

8

T63

10

T65

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T6

1

T65

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T6

2

T65

1

T367

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T6

1

T22

2

T367

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T6

1

T65

1

T22

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T6

1

T63

1

T65

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T65

1

T22

1

T125

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T65

1

T22

3

T367

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T63

1

T22

1

T367

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T22

2

T125

2

T368

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T63

1

T65

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T65

1

T22

2

T35

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T63

2

T22

2

T125

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T63

1

T22

4

T284

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T65

1

T367

1

T35

3

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T6

1

T65

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T6

2

T63

1

T65

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T6

10

T63

8

T65

16

auto[1]

1095

1

T6

10

T63

12

T65

4

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T6

5

T63

5

T65

4

from_0to1

521

1

T6

5

T63

4

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T6

13

T63

8

T65

9

auto[1]

1082

1

T6

7

T63

12

T65

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T6

15

T63

10

T65

15

auto[1]

1058

1

T6

5

T63

10

T65

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T63

1

T22

1

T367

3

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T6

1

T125

1

T285

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T6

1

T65

3

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T63

1

T65

1

T22

4

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T6

2

T65

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T65

1

T22

2

T368

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T6

1

T65

1

T22

3

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T22

1

T367

1

T125

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T6

1

T22

4

T125

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T6

2

T63

1

T22

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T63

1

T22

1

T125

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T63

1

T367

1

T35

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T65

1

T22

1

T35

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T6

1

T63

1

T367

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T6

1

T63

2

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T63

1

T22

3

T367

1