Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156171	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119831

1

T1

2

T2

576

T3

226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144299	1			T1	4		T2	545		T3	392
values[0x0]	65608	1			T1	6		T2	433		T3	30
values[0x1]	66095	1			T1	4		T2	433		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149338

1

T1

6

T2

683

T3

272

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	885	1			T2	7		T42	1		T43	4
valid_sources[0x01]	852	1			T2	5		T3	1		T15	1
valid_sources[0x02]	878	1			T2	11		T24	1		T43	3
valid_sources[0x03]	884	1			T2	1		T7	2		T43	5
valid_sources[0x04]	884	1			T2	5		T43	2		T63	1
valid_sources[0x05]	985	1			T2	16		T3	2		T15	7
valid_sources[0x06]	1680	1			T2	11		T3	1		T5	1
valid_sources[0x07]	1024	1			T2	6		T3	5		T42	1
valid_sources[0x08]	788	1			T2	9		T3	8		T42	2
valid_sources[0x09]	873	1			T2	6		T21	1		T42	1
valid_sources[0x0a]	884	1			T2	5		T3	5		T42	2
valid_sources[0x0b]	799	1			T2	4		T43	2		T22	4
valid_sources[0x0c]	1137	1			T2	7		T3	2		T42	11
valid_sources[0x0d]	1198	1			T2	1		T4	1		T6	2
valid_sources[0x0e]	892	1			T2	7		T15	7		T42	2
valid_sources[0x0f]	701	1			T1	14		T2	2		T3	3
valid_sources[0x10]	837	1			T2	7		T15	4		T43	1
valid_sources[0x11]	899	1			T2	11		T3	2		T24	1
valid_sources[0x12]	1140	1			T2	6		T3	13		T5	2
valid_sources[0x13]	870	1			T2	2		T6	9		T7	2
valid_sources[0x14]	1094	1			T2	4		T3	1		T15	3
valid_sources[0x15]	943	1			T24	1		T7	1		T43	2
valid_sources[0x16]	831	1			T2	4		T3	1		T15	8
valid_sources[0x17]	1164	1			T2	3		T43	2		T22	8
valid_sources[0x18]	946	1			T2	3		T3	1		T11	2
valid_sources[0x19]	872	1			T2	5		T3	6		T42	5
valid_sources[0x1a]	831	1			T2	6		T5	1		T42	1
valid_sources[0x1b]	952	1			T2	5		T3	1		T11	1
valid_sources[0x1c]	904	1			T2	8		T42	2		T7	1
valid_sources[0x1d]	1135	1			T2	13		T42	3		T43	3
valid_sources[0x1e]	959	1			T2	6		T24	1		T7	1
valid_sources[0x1f]	892	1			T2	3		T42	3		T43	3
valid_sources[0x20]	1064	1			T2	6		T43	2		T22	4
valid_sources[0x21]	1019	1			T2	6		T3	1		T23	179
valid_sources[0x22]	1278	1			T2	1		T15	4		T63	1
valid_sources[0x23]	821	1			T2	7		T4	1		T7	1
valid_sources[0x24]	1629	1			T2	6		T24	1		T43	2
valid_sources[0x25]	1002	1			T2	7		T42	3		T22	5
valid_sources[0x26]	1066	1			T2	9		T15	8		T43	1
valid_sources[0x27]	3078	1			T2	5		T24	1		T7	1
valid_sources[0x28]	819	1			T2	5		T15	2		T43	2
valid_sources[0x29]	1046	1			T2	9		T24	1		T42	4
valid_sources[0x2a]	1285	1			T3	5		T5	1		T42	2
valid_sources[0x2b]	932	1			T3	1		T43	3		T63	1
valid_sources[0x2c]	967	1			T2	5		T3	2		T42	1
valid_sources[0x2d]	1244	1			T2	3		T3	2		T7	1
valid_sources[0x2e]	909	1			T2	5		T15	1		T63	1
valid_sources[0x2f]	927	1			T2	13		T3	7		T42	2
valid_sources[0x30]	853	1			T2	4		T5	2		T42	1
valid_sources[0x31]	1461	1			T2	4		T3	2		T43	2
valid_sources[0x32]	900	1			T2	10		T24	1		T42	1
valid_sources[0x33]	1061	1			T2	2		T24	1		T43	6
valid_sources[0x34]	790	1			T2	11		T3	4		T15	1
valid_sources[0x35]	1501	1			T2	1		T4	6		T7	1
valid_sources[0x36]	1031	1			T2	5		T3	3		T15	3
valid_sources[0x37]	1209	1			T2	5		T3	4		T24	1
valid_sources[0x38]	839	1			T2	2		T43	3		T85	7
valid_sources[0x39]	757	1			T2	8		T3	4		T24	1
valid_sources[0x3a]	771	1			T2	3		T3	8		T6	20
valid_sources[0x3b]	874	1			T2	4		T43	5		T65	5
valid_sources[0x3c]	1786	1			T2	5		T42	1		T43	2
valid_sources[0x3d]	863	1			T2	5		T3	1		T7	1
valid_sources[0x3e]	1003	1			T2	5		T43	3		T22	3
valid_sources[0x3f]	959	1			T2	1		T3	2		T15	14
valid_sources[0x40]	1028	1			T2	2		T3	1		T43	1
valid_sources[0x41]	962	1			T2	6		T42	6		T43	4
valid_sources[0x42]	905	1			T2	6		T3	1		T43	1
valid_sources[0x43]	1609	1			T2	8		T3	2		T15	5
valid_sources[0x44]	1207	1			T2	6		T3	1		T42	1
valid_sources[0x45]	734	1			T2	5		T3	6		T7	1
valid_sources[0x46]	892	1			T2	6		T24	1		T7	2
valid_sources[0x47]	1141	1			T2	7		T3	2		T6	20
valid_sources[0x48]	919	1			T2	3		T3	3		T6	5
valid_sources[0x49]	856	1			T2	9		T15	1		T24	2
valid_sources[0x4a]	912	1			T2	6		T3	3		T22	1
valid_sources[0x4b]	1659	1			T2	2		T3	9		T15	5
valid_sources[0x4c]	1104	1			T2	3		T42	1		T22	2
valid_sources[0x4d]	860	1			T2	1		T6	2		T43	4
valid_sources[0x4e]	916	1			T2	4		T24	1		T43	1
valid_sources[0x4f]	893	1			T2	5		T3	1		T15	2
valid_sources[0x50]	1180	1			T2	7		T15	7		T6	3
valid_sources[0x51]	722	1			T2	12		T3	1		T15	6
valid_sources[0x52]	940	1			T2	2		T3	3		T15	1
valid_sources[0x53]	962	1			T2	10		T3	3		T42	9
valid_sources[0x54]	934	1			T2	4		T3	1		T4	3
valid_sources[0x55]	881	1			T2	7		T3	7		T42	7
valid_sources[0x56]	1082	1			T2	3		T11	2		T15	13
valid_sources[0x57]	1369	1			T2	6		T3	3		T43	1
valid_sources[0x58]	1650	1			T2	4		T15	3		T43	5
valid_sources[0x59]	975	1			T2	4		T3	3		T15	7
valid_sources[0x5a]	956	1			T2	9		T3	5		T24	1
valid_sources[0x5b]	829	1			T2	8		T42	1		T63	1
valid_sources[0x5c]	781	1			T2	1		T42	3		T43	1
valid_sources[0x5d]	1193	1			T2	2		T3	1		T43	2
valid_sources[0x5e]	880	1			T2	3		T3	6		T14	3
valid_sources[0x5f]	1771	1			T2	3		T3	6		T15	3
valid_sources[0x60]	1163	1			T2	4		T3	1		T21	12
valid_sources[0x61]	930	1			T2	4		T6	20		T7	2
valid_sources[0x62]	992	1			T2	3		T43	3		T63	1
valid_sources[0x63]	1053	1			T2	4		T24	1		T65	6
valid_sources[0x64]	916	1			T2	2		T42	3		T43	1
valid_sources[0x65]	672	1			T2	9		T3	4		T43	3
valid_sources[0x66]	1761	1			T2	10		T7	2		T43	2
valid_sources[0x67]	882	1			T2	8		T42	1		T43	2
valid_sources[0x68]	1643	1			T2	8		T3	1		T4	3
valid_sources[0x69]	1085	1			T2	9		T3	4		T7	1
valid_sources[0x6a]	1094	1			T2	11		T3	7		T11	1
valid_sources[0x6b]	1202	1			T2	6		T3	1		T15	20
valid_sources[0x6c]	745	1			T2	11		T5	1		T43	1
valid_sources[0x6d]	781	1			T2	7		T42	1		T43	1
valid_sources[0x6e]	927	1			T2	4		T3	3		T63	2
valid_sources[0x6f]	1026	1			T2	2		T15	7		T4	2
valid_sources[0x70]	1102	1			T2	11		T15	9		T42	1
valid_sources[0x71]	905	1			T2	4		T3	1		T7	1
valid_sources[0x72]	846	1			T2	5		T15	2		T43	1
valid_sources[0x73]	1016	1			T2	2		T6	20		T42	1
valid_sources[0x74]	1538	1			T2	6		T3	3		T6	15
valid_sources[0x75]	840	1			T2	5		T3	4		T43	2
valid_sources[0x76]	975	1			T2	3		T15	2		T21	7
valid_sources[0x77]	931	1			T2	5		T5	1		T24	2
valid_sources[0x78]	755	1			T2	2		T3	5		T5	1
valid_sources[0x79]	1590	1			T2	5		T3	5		T43	1
valid_sources[0x7a]	1088	1			T2	2		T3	6		T24	1
valid_sources[0x7b]	957	1			T2	14		T24	1		T22	4
valid_sources[0x7c]	938	1			T2	2		T3	9		T11	1
valid_sources[0x7d]	1011	1			T2	2		T3	2		T15	1
valid_sources[0x7e]	907	1			T2	1		T3	2		T15	2
valid_sources[0x7f]	1737	1			T2	9		T6	928		T42	2
valid_sources[0x80]	693	1			T2	4		T3	2		T15	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65246

1

T2

276

T3

191

T11

5

values[0x0]

all_enables

biggest_size

31940

1

T1

2

T2

167

T3

17

values[0x1]

all_enables

biggest_size

22645

1

T2

133

T3

18

T11

2