Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T23,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T11,T23,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T23,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T25
1	0	Covered	T2,T3,T11
1	1	Covered	T11,T23,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T23,T25
0	1	Covered	T47,T38,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T23,T25
0	1	Covered	T11,T23,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T23,T25
1	-	Covered	T11,T23,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T23,T25
DetectSt	168	Covered	T11,T23,T25
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T11,T23,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T23,T25
DebounceSt->IdleSt	163	Covered	T42,T7,T44
DetectSt->IdleSt	186	Covered	T47,T38,T91
DetectSt->StableSt	191	Covered	T11,T23,T25
IdleSt->DebounceSt	148	Covered	T11,T23,T25
StableSt->IdleSt	206	Covered	T11,T23,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T23,T25
0	1	Covered	T11,T23,T25
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T23,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T23,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T23,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T7,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T23,T25
DetectSt	-	-	-	-	1	-	-	Covered	T47,T38,T91
DetectSt	-	-	-	-	0	1	-	Covered	T11,T23,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T23,T25
StableSt	-	-	-	-	-	-	0	Covered	T11,T23,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	268	0	0
CntIncr_A	5981322	236581	0	0
CntNoWrap_A	5981322	5323297	0	0
DetectStDropOut_A	5981322	5	0	0
DetectedOut_A	5981322	824	0	0
DetectedPulseOut_A	5981322	115	0	0
DisabledIdleSt_A	5981322	5080622	0	0
DisabledNoDetection_A	5981322	5083013	0	0
EnterDebounceSt_A	5981322	149	0	0
EnterDetectSt_A	5981322	120	0	0
EnterStableSt_A	5981322	115	0	0
PulseIsPulse_A	5981322	115	0	0
StayInStableSt	5981322	709	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5981322	6892	0	0
gen_low_level_sva.LowLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	115	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	268	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	3	0	0
T11	695	2	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	2	0	0
T23	2625	6	0	0
T25	610	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	236581	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	92	0	0
T11	695	76	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	97	0	0
T23	2625	174	0	0
T25	610	22	0	0
T42	0	59	0	0
T44	0	124	0	0
T45	0	271	0	0
T46	0	21	0	0
T47	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323297	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	292	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5	0	0
T28	20221	0	0	0
T34	116074	0	0	0
T36	657	0	0	0
T38	0	1	0	0
T39	11819	0	0	0
T40	13719	0	0	0
T47	682	1	0	0
T48	25906	0	0	0
T57	496	0	0	0
T91	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T102	3525	0	0	0
T103	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	824	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	6	0	0
T11	695	6	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	3	0	0
T23	2625	25	0	0
T25	610	2	0	0
T44	0	5	0	0
T45	0	20	0	0
T46	0	9	0	0
T48	0	8	0	0
T104	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	115	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	1	0	0
T11	695	1	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	1	0	0
T23	2625	3	0	0
T25	610	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T104	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5080622	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	176	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5083013	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	177	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	149	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	2	0	0
T11	695	1	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	1	0	0
T23	2625	3	0	0
T25	610	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	120	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	1	0	0
T11	695	1	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	1	0	0
T23	2625	3	0	0
T25	610	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	115	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	1	0	0
T11	695	1	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	1	0	0
T23	2625	3	0	0
T25	610	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T104	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	115	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	1	0	0
T11	695	1	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	1	0	0
T23	2625	3	0	0
T25	610	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T104	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	709	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	5	0	0
T11	695	5	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	2	0	0
T23	2625	22	0	0
T25	610	1	0	0
T44	0	4	0	0
T45	0	17	0	0
T46	0	8	0	0
T48	0	6	0	0
T104	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	6892	0	0
T2	30305	32	0	0
T3	12443	11	0	0
T4	39627	6	0	0
T5	661	1	0	0
T6	71572	71	0	0
T11	695	3	0	0
T12	18017	26	0	0
T13	421	2	0	0
T14	593	0	0	0
T15	5141	29	0	0
T23	0	18	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	115	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	0	1	0	0
T11	695	1	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	1	0	0
T23	2625	3	0	0
T25	610	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	0	2	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T9,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T20
1	0	Covered	T2,T3,T11
1	1	Covered	T4,T9,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T20
0	1	Covered	T54,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T20
0	1	Unreachable
1	0	Covered	T4,T9,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T20
DetectSt	168	Covered	T4,T9,T20
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T9,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T20
DebounceSt->IdleSt	163	Covered	T54,T56,T38
DetectSt->IdleSt	186	Covered	T54,T83,T84
DetectSt->StableSt	191	Covered	T4,T9,T20
IdleSt->DebounceSt	148	Covered	T4,T9,T20
StableSt->IdleSt	206	Covered	T4,T9,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T20
0	1	Covered	T4,T9,T20
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T38,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T20
DetectSt	-	-	-	-	1	-	-	Covered	T54,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T20
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	219	0	0
CntIncr_A	5981322	144587	0	0
CntNoWrap_A	5981322	5323346	0	0
DetectStDropOut_A	5981322	29	0	0
DetectedOut_A	5981322	70920	0	0
DetectedPulseOut_A	5981322	49	0	0
DisabledIdleSt_A	5981322	4954111	0	0
DisabledNoDetection_A	5981322	4956548	0	0
EnterDebounceSt_A	5981322	142	0	0
EnterDetectSt_A	5981322	78	0	0
EnterStableSt_A	5981322	49	0	0
PulseIsPulse_A	5981322	49	0	0
StayInStableSt	5981322	70871	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5981322	6892	0	0
gen_low_level_sva.LowLevelEvent_A	5981322	5326004	0	0
gen_sticky_sva.StableStDropOut_A	5981322	72359	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	219	0	0
T4	39627	2	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	2	0	0
T20	0	2	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	4	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	5	0	0
T55	0	2	0	0
T56	0	1	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	144587	0	0
T4	39627	14	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	98	0	0
T20	0	41	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	198	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	180	0	0
T55	0	36	0	0
T56	0	14	0	0
T71	0	54	0	0
T72	0	104	0	0
T73	0	285	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323346	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39224	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	29	0	0
T54	1806	2	0	0
T55	1831	0	0	0
T78	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T110	0	1	0	0
T111	0	4	0	0
T112	0	3	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	403	0	0	0
T117	708	0	0	0
T118	505	0	0	0
T119	502	0	0	0
T120	3727	0	0	0
T121	525	0	0	0
T122	10191	0	0	0
T123	22790	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	70920	0	0
T4	39627	5	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	864	0	0
T20	0	181	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T55	0	160	0	0
T71	0	314	0	0
T105	0	400	0	0
T106	0	39	0	0
T107	0	16	0	0
T108	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	49	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T55	0	1	0	0
T71	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4954111	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	32680	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4956548	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	32681	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	142	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	2	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	78	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T71	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	49	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T55	0	1	0	0
T71	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	49	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T55	0	1	0	0
T71	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	70871	0	0
T4	39627	4	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	863	0	0
T20	0	180	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T55	0	159	0	0
T71	0	313	0	0
T105	0	399	0	0
T106	0	38	0	0
T107	0	15	0	0
T108	0	79	0	0
T109	0	216	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	6892	0	0
T2	30305	32	0	0
T3	12443	11	0	0
T4	39627	6	0	0
T5	661	1	0	0
T6	71572	71	0	0
T11	695	3	0	0
T12	18017	26	0	0
T13	421	2	0	0
T14	593	0	0	0
T15	5141	29	0	0
T23	0	18	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	72359	0	0
T4	39627	6518	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	82	0	0
T20	0	56	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	58	0	0
T42	2306	0	0	0
T49	402	0	0	0
T55	0	339	0	0
T71	0	445	0	0
T105	0	164	0	0
T106	0	24	0	0
T107	0	24	0	0
T108	0	363	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T5
1	1	Covered	T13,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T9,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T20,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T20
1	0	Covered	T13,T4,T5
1	1	Covered	T4,T9,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T20,T54
0	1	Covered	T20,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T20,T54
0	1	Unreachable
1	0	Covered	T9,T20,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T20
DetectSt	168	Covered	T9,T20,T54
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T9,T20,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T20,T54
DebounceSt->IdleSt	163	Covered	T4,T56,T71
DetectSt->IdleSt	186	Covered	T20,T81,T82
DetectSt->StableSt	191	Covered	T9,T20,T54
IdleSt->DebounceSt	148	Covered	T4,T9,T20
StableSt->IdleSt	206	Covered	T9,T20,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T20
0	1	Covered	T4,T9,T20
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T20,T54
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T20
IdleSt	0	-	-	-	-	-	-	Covered	T13,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T20,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T71,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T9,T20,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T20,T54
StableSt	-	-	-	-	-	-	0	Covered	T9,T20,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	183	0	0
CntIncr_A	5981322	55729	0	0
CntNoWrap_A	5981322	5323382	0	0
DetectStDropOut_A	5981322	5	0	0
DetectedOut_A	5981322	98081	0	0
DetectedPulseOut_A	5981322	61	0	0
DisabledIdleSt_A	5981322	4954111	0	0
DisabledNoDetection_A	5981322	4956548	0	0
EnterDebounceSt_A	5981322	118	0	0
EnterDetectSt_A	5981322	66	0	0
EnterStableSt_A	5981322	61	0	0
PulseIsPulse_A	5981322	61	0	0
StayInStableSt	5981322	98020	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_sticky_sva.StableStDropOut_A	5981322	156114	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	183	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	2	0	0
T20	0	4	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T71	0	4	0	0
T72	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	55729	0	0
T4	39627	6512	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	27	0	0
T20	0	54	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	50	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	75	0	0
T55	0	48	0	0
T56	0	13	0	0
T71	0	320	0	0
T72	0	66	0	0
T73	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323382	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39225	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5	0	0
T20	720	1	0	0
T35	18884	0	0	0
T37	518	0	0	0
T59	504	0	0	0
T70	5270	0	0	0
T81	0	2	0	0
T82	0	1	0	0
T124	0	1	0	0
T125	2953	0	0	0
T126	524	0	0	0
T127	522	0	0	0
T128	1079	0	0	0
T129	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	98081	0	0
T9	1490	140	0	0
T10	26612	0	0	0
T20	0	29	0	0
T22	24860	0	0	0
T38	0	221	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	221	0	0
T55	0	396	0	0
T73	0	54	0	0
T83	0	114	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	463	0	0
T106	0	18	0	0
T107	0	15	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	61	0	0
T9	1490	1	0	0
T10	26612	0	0	0
T20	0	1	0	0
T22	24860	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T73	0	1	0	0
T83	0	1	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4954111	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	32680	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4956548	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	32681	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	118	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	2	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T71	0	4	0	0
T72	0	2	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	66	0	0
T9	1490	1	0	0
T10	26612	0	0	0
T20	0	2	0	0
T22	24860	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T73	0	1	0	0
T83	0	1	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	61	0	0
T9	1490	1	0	0
T10	26612	0	0	0
T20	0	1	0	0
T22	24860	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T73	0	1	0	0
T83	0	1	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	61	0	0
T9	1490	1	0	0
T10	26612	0	0	0
T20	0	1	0	0
T22	24860	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T73	0	1	0	0
T83	0	1	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	98020	0	0
T9	1490	139	0	0
T10	26612	0	0	0
T20	0	28	0	0
T22	24860	0	0	0
T38	0	220	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	220	0	0
T55	0	395	0	0
T73	0	53	0	0
T83	0	113	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	462	0	0
T106	0	17	0	0
T107	0	14	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	156114	0	0
T9	1490	885	0	0
T10	26612	0	0	0
T20	0	130	0	0
T22	24860	0	0	0
T38	0	76	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T54	0	220	0	0
T55	0	104	0	0
T73	0	274	0	0
T83	0	371	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T105	0	100	0	0
T106	0	52	0	0
T107	0	40	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T9,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T20
1	0	Covered	T2,T3,T12
1	1	Covered	T4,T9,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T54
0	1	Covered	T78,T79,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T54
0	1	Unreachable
1	0	Covered	T4,T9,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T20
DetectSt	168	Covered	T4,T9,T54
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T9,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T54
DebounceSt->IdleSt	163	Covered	T20,T56,T38
DetectSt->IdleSt	186	Covered	T78,T79,T80
DetectSt->StableSt	191	Covered	T4,T9,T54
IdleSt->DebounceSt	148	Covered	T4,T9,T20
StableSt->IdleSt	206	Covered	T4,T9,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T20
0	1	Covered	T4,T9,T20
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T54
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T20
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T38,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T20
DetectSt	-	-	-	-	1	-	-	Covered	T78,T79,T80
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T54
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	200	0	0
CntIncr_A	5981322	6556	0	0
CntNoWrap_A	5981322	5323365	0	0
DetectStDropOut_A	5981322	16	0	0
DetectedOut_A	5981322	10312	0	0
DetectedPulseOut_A	5981322	58	0	0
DisabledIdleSt_A	5981322	4954111	0	0
DisabledNoDetection_A	5981322	4956548	0	0
EnterDebounceSt_A	5981322	127	0	0
EnterDetectSt_A	5981322	74	0	0
EnterStableSt_A	5981322	58	0	0
PulseIsPulse_A	5981322	58	0	0
StayInStableSt	5981322	10254	0	0
gen_high_event_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_sticky_sva.StableStDropOut_A	5981322	266254	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	200	0	0
T4	39627	2	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	2	0	0
T20	0	3	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	6556	0	0
T4	39627	70	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	29	0	0
T20	0	102	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	57	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	94	0	0
T55	0	49	0	0
T56	0	16	0	0
T71	0	78	0	0
T72	0	146	0	0
T73	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323365	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39224	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	16	0	0
T77	7945	0	0	0
T78	1039	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T113	0	1	0	0
T115	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	5	0	0
T134	426	0	0	0
T135	24194	0	0	0
T136	763	0	0	0
T137	640	0	0	0
T138	439	0	0	0
T139	17054	0	0	0
T140	5417	0	0	0
T141	948	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	10312	0	0
T4	39627	25	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	125	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	380	0	0
T55	0	379	0	0
T71	0	518	0	0
T73	0	112	0	0
T105	0	200	0	0
T106	0	18	0	0
T107	0	7	0	0
T109	0	243	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	58	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4954111	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	32680	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4956548	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	32681	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	127	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T20	0	3	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T38	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	74	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	58	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	58	0	0
T4	39627	1	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	10254	0	0
T4	39627	24	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	124	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	379	0	0
T55	0	378	0	0
T71	0	517	0	0
T73	0	111	0	0
T105	0	199	0	0
T106	0	17	0	0
T107	0	6	0	0
T109	0	241	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	266254	0	0
T4	39627	6444	0	0
T5	661	0	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T9	0	909	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T54	0	44	0	0
T55	0	124	0	0
T71	0	223	0	0
T73	0	193	0	0
T105	0	423	0	0
T106	0	36	0	0
T107	0	58	0	0
T109	0	156	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T35,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T10,T35,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T35,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T35,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T38
0	1	Covered	T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T38
0	1	Covered	T35,T38,T143
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T35,T38
1	-	Covered	T35,T38,T143

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T35,T56
DetectSt	168	Covered	T10,T35,T38
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T10,T35,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T35,T38
DebounceSt->IdleSt	163	Covered	T56,T144,T74
DetectSt->IdleSt	186	Covered	T142
DetectSt->StableSt	191	Covered	T10,T35,T38
IdleSt->DebounceSt	148	Covered	T10,T35,T56
StableSt->IdleSt	206	Covered	T35,T38,T143

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T35,T56
0	1	Covered	T10,T35,T56
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T35,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T35,T56
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T35,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T144
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T35,T56
DetectSt	-	-	-	-	1	-	-	Covered	T142
DetectSt	-	-	-	-	0	1	-	Covered	T10,T35,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T38,T143
StableSt	-	-	-	-	-	-	0	Covered	T10,T35,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	73	0	0
CntIncr_A	5981322	59578	0	0
CntNoWrap_A	5981322	5323492	0	0
DetectStDropOut_A	5981322	1	0	0
DetectedOut_A	5981322	123078	0	0
DetectedPulseOut_A	5981322	34	0	0
DisabledIdleSt_A	5981322	5054260	0	0
DisabledNoDetection_A	5981322	5056641	0	0
EnterDebounceSt_A	5981322	38	0	0
EnterDetectSt_A	5981322	35	0	0
EnterStableSt_A	5981322	34	0	0
PulseIsPulse_A	5981322	34	0	0
StayInStableSt	5981322	123027	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	73	0	0
T10	26612	2	0	0
T22	24860	0	0	0
T35	0	4	0	0
T38	0	4	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T56	0	1	0	0
T85	450	0	0	0
T93	0	4	0	0
T100	426	0	0	0
T101	424	0	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	59578	0	0
T10	26612	4217	0	0
T22	24860	0	0	0
T35	0	116	0	0
T38	0	106	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T56	0	23	0	0
T85	450	0	0	0
T93	0	146	0	0
T100	426	0	0	0
T101	424	0	0	0
T142	0	94	0	0
T143	0	66	0	0
T144	0	95	0	0
T145	0	58	0	0
T146	0	21	0	0
T147	404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323492	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1	0	0
T94	4596	0	0	0
T142	6249	1	0	0
T146	19915	0	0	0
T148	19836	0	0	0
T149	668	0	0	0
T150	503	0	0	0
T151	754	0	0	0
T152	18478	0	0	0
T153	13793	0	0	0
T154	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	123078	0	0
T10	26612	9149	0	0
T22	24860	0	0	0
T35	0	224	0	0
T38	0	90	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T93	0	275	0	0
T100	426	0	0	0
T101	424	0	0	0
T143	0	248	0	0
T145	0	322	0	0
T146	0	74	0	0
T147	404	0	0	0
T155	0	150	0	0
T156	0	40	0	0
T157	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	34	0	0
T10	26612	1	0	0
T22	24860	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T93	0	2	0	0
T100	426	0	0	0
T101	424	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	404	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5054260	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5056641	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	38	0	0
T10	26612	1	0	0
T22	24860	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T56	0	1	0	0
T85	450	0	0	0
T93	0	2	0	0
T100	426	0	0	0
T101	424	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	35	0	0
T10	26612	1	0	0
T22	24860	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T93	0	2	0	0
T100	426	0	0	0
T101	424	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	404	0	0	0
T155	0	2	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	34	0	0
T10	26612	1	0	0
T22	24860	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T93	0	2	0	0
T100	426	0	0	0
T101	424	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	404	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	34	0	0
T10	26612	1	0	0
T22	24860	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T93	0	2	0	0
T100	426	0	0	0
T101	424	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	404	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	123027	0	0
T10	26612	9147	0	0
T22	24860	0	0	0
T35	0	222	0	0
T38	0	87	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T93	0	272	0	0
T100	426	0	0	0
T101	424	0	0	0
T143	0	247	0	0
T145	0	320	0	0
T146	0	73	0	0
T147	404	0	0	0
T155	0	148	0	0
T156	0	39	0	0
T157	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	17	0	0
T35	18884	2	0	0
T38	0	1	0	0
T87	13596	0	0	0
T93	0	1	0	0
T127	522	0	0	0
T128	1079	0	0	0
T129	504	0	0	0
T143	0	1	0	0
T146	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	569	0	0	0
T162	43750	0	0	0
T163	432	0	0	0
T164	756	0	0	0
T165	671	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T5,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Covered	T2,T3,T13
1	1	Covered	T5,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T5,T155,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T10,T32,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T10
1	-	Covered	T10,T32,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T10
DetectSt	168	Covered	T5,T7,T10
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T5,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T10
DebounceSt->IdleSt	163	Covered	T35,T56,T145
DetectSt->IdleSt	186	Covered	T5,T155,T166
DetectSt->StableSt	191	Covered	T5,T7,T10
IdleSt->DebounceSt	148	Covered	T5,T7,T10
StableSt->IdleSt	206	Covered	T7,T10,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T10
0	1	Covered	T5,T7,T10
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T145,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T5,T155,T166
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T35
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	135	0	0
CntIncr_A	5981322	8070	0	0
CntNoWrap_A	5981322	5323430	0	0
DetectStDropOut_A	5981322	3	0	0
DetectedOut_A	5981322	10173	0	0
DetectedPulseOut_A	5981322	62	0	0
DisabledIdleSt_A	5981322	5279152	0	0
DisabledNoDetection_A	5981322	5281534	0	0
EnterDebounceSt_A	5981322	71	0	0
EnterDetectSt_A	5981322	65	0	0
EnterStableSt_A	5981322	62	0	0
PulseIsPulse_A	5981322	62	0	0
StayInStableSt	5981322	10080	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5981322	2601	0	0
gen_low_level_sva.LowLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	135	0	0
T5	661	4	0	0
T6	71572	0	0	0
T7	2108	2	0	0
T10	0	2	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	6	0	0
T35	0	7	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T120	0	2	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	8070	0	0
T5	661	36	0	0
T6	71572	0	0	0
T7	2108	14	0	0
T10	0	4217	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	201	0	0
T35	0	350	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	23	0	0
T120	0	36	0	0
T143	0	132	0	0
T144	0	190	0	0
T145	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323430	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	256	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T155	0	1	0	0
T166	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	10173	0	0
T5	661	68	0	0
T6	71572	0	0	0
T7	2108	56	0	0
T10	0	6189	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	186	0	0
T35	0	213	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	38	0	0
T142	0	164	0	0
T143	0	94	0	0
T144	0	91	0	0
T167	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	62	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	3	0	0
T35	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T167	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5279152	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	4	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5281534	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	4	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	71	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	3	0	0
T35	0	4	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T120	0	1	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	65	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	3	0	0
T35	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T167	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	62	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	3	0	0
T35	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T167	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	62	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	3	0	0
T35	0	3	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T167	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	10080	0	0
T5	661	66	0	0
T6	71572	0	0	0
T7	2108	54	0	0
T10	0	6188	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	182	0	0
T35	0	208	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	36	0	0
T142	0	161	0	0
T143	0	91	0	0
T144	0	88	0	0
T167	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	2601	0	0
T4	39627	0	0	0
T5	661	2	0	0
T6	71572	34	0	0
T7	0	6	0	0
T13	421	1	0	0
T14	593	0	0	0
T15	5141	0	0	0
T21	499	5	0	0
T23	2625	13	0	0
T24	523	5	0	0
T25	610	0	0	0
T42	0	7	0	0
T50	0	2	0	0
T51	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	31	0	0
T10	26612	1	0	0
T22	24860	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T52	686	0	0	0
T85	450	0	0	0
T100	426	0	0	0
T101	424	0	0	0
T107	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T147	404	0	0	0
T155	0	2	0	0
T167	0	2	0	0
T168	0	1	0	0