Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T34,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T7,T34,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T34,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T34,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T34,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T32,T37
0	1	Covered	T7,T205,T197
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T32,T37
0	1	Covered	T32,T35,T169
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T32,T37
1	-	Covered	T32,T35,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T34,T32
DetectSt	168	Covered	T7,T34,T32
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T34,T32,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T34,T32
DebounceSt->IdleSt	163	Covered	T56,T38,T145
DetectSt->IdleSt	186	Covered	T7,T205,T197
DetectSt->StableSt	191	Covered	T34,T32,T37
IdleSt->DebounceSt	148	Covered	T7,T34,T32
StableSt->IdleSt	206	Covered	T32,T35,T169

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T34,T32
0	1	Covered	T7,T34,T32
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T34,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T34,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T34,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T145,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T34,T32
DetectSt	-	-	-	-	1	-	-	Covered	T7,T205,T197
DetectSt	-	-	-	-	0	1	-	Covered	T34,T32,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T35,T169
StableSt	-	-	-	-	-	-	0	Covered	T34,T32,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	173	0	0
CntIncr_A	5981322	153769	0	0
CntNoWrap_A	5981322	5323392	0	0
DetectStDropOut_A	5981322	4	0	0
DetectedOut_A	5981322	121201	0	0
DetectedPulseOut_A	5981322	77	0	0
DisabledIdleSt_A	5981322	4910701	0	0
DisabledNoDetection_A	5981322	4913072	0	0
EnterDebounceSt_A	5981322	92	0	0
EnterDetectSt_A	5981322	81	0	0
EnterStableSt_A	5981322	77	0	0
PulseIsPulse_A	5981322	77	0	0
StayInStableSt	5981322	121092	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	173	0	0
T7	2108	2	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	2	0	0
T38	0	5	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T56	0	1	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T128	0	2	0	0
T145	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	153769	0	0
T7	2108	14	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T32	0	67	0	0
T34	0	58913	0	0
T35	0	111	0	0
T37	0	21	0	0
T38	0	159	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T56	0	22	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T128	0	80	0	0
T145	0	116	0	0
T169	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323392	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T197	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	121201	0	0
T31	13387	0	0	0
T32	1016	125	0	0
T34	116074	56752	0	0
T35	0	145	0	0
T37	0	87	0	0
T38	0	90	0	0
T41	25243	0	0	0
T66	526	0	0	0
T67	790	0	0	0
T68	458	0	0	0
T69	16521	0	0	0
T93	0	40	0	0
T128	0	293	0	0
T143	0	178	0	0
T144	0	378	0	0
T169	0	170	0	0
T206	404	0	0	0
T207	7327	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	77	0	0
T31	13387	0	0	0
T32	1016	1	0	0
T34	116074	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	25243	0	0	0
T66	526	0	0	0
T67	790	0	0	0
T68	458	0	0	0
T69	16521	0	0	0
T93	0	1	0	0
T128	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T169	0	1	0	0
T206	404	0	0	0
T207	7327	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4910701	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4913072	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	92	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T56	0	1	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T128	0	1	0	0
T145	0	2	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	81	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T128	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	77	0	0
T31	13387	0	0	0
T32	1016	1	0	0
T34	116074	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	25243	0	0	0
T66	526	0	0	0
T67	790	0	0	0
T68	458	0	0	0
T69	16521	0	0	0
T93	0	1	0	0
T128	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T169	0	1	0	0
T206	404	0	0	0
T207	7327	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	77	0	0
T31	13387	0	0	0
T32	1016	1	0	0
T34	116074	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	25243	0	0	0
T66	526	0	0	0
T67	790	0	0	0
T68	458	0	0	0
T69	16521	0	0	0
T93	0	1	0	0
T128	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T169	0	1	0	0
T206	404	0	0	0
T207	7327	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	121092	0	0
T31	13387	0	0	0
T32	1016	124	0	0
T34	116074	56750	0	0
T35	0	143	0	0
T37	0	85	0	0
T38	0	87	0	0
T41	25243	0	0	0
T66	526	0	0	0
T67	790	0	0	0
T68	458	0	0	0
T69	16521	0	0	0
T93	0	38	0	0
T128	0	291	0	0
T143	0	175	0	0
T144	0	377	0	0
T169	0	169	0	0
T206	404	0	0	0
T207	7327	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	45	0	0
T29	29098	0	0	0
T32	1016	1	0	0
T35	0	2	0	0
T38	0	1	0	0
T53	1497	0	0	0
T58	489	0	0	0
T69	16521	0	0	0
T86	9151	0	0	0
T104	29786	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T155	0	1	0	0
T169	0	1	0	0
T195	0	2	0	0
T199	1415	0	0	0
T200	443	0	0	0
T201	603	0	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T22,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T5,T22,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T22,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T22,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T22,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T22,T32
0	1	Covered	T79,T196,T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T22,T32
0	1	Covered	T5,T35,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T22,T32
1	-	Covered	T5,T35,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T22,T32
DetectSt	168	Covered	T5,T22,T32
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T5,T22,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T22,T32
DebounceSt->IdleSt	163	Covered	T56,T74
DetectSt->IdleSt	186	Covered	T79,T196,T176
DetectSt->StableSt	191	Covered	T5,T22,T32
IdleSt->DebounceSt	148	Covered	T5,T22,T32
StableSt->IdleSt	206	Covered	T5,T22,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T22,T32
0	1	Covered	T5,T22,T32
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T22,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T22,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T22,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T22,T32
DetectSt	-	-	-	-	1	-	-	Covered	T79,T196,T176
DetectSt	-	-	-	-	0	1	-	Covered	T5,T22,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T35,T38
StableSt	-	-	-	-	-	-	0	Covered	T5,T22,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	100	0	0
CntIncr_A	5981322	11852	0	0
CntNoWrap_A	5981322	5323465	0	0
DetectStDropOut_A	5981322	3	0	0
DetectedOut_A	5981322	3589	0	0
DetectedPulseOut_A	5981322	46	0	0
DisabledIdleSt_A	5981322	5171880	0	0
DisabledNoDetection_A	5981322	5174263	0	0
EnterDebounceSt_A	5981322	51	0	0
EnterDetectSt_A	5981322	49	0	0
EnterStableSt_A	5981322	46	0	0
PulseIsPulse_A	5981322	46	0	0
StayInStableSt	5981322	3519	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5981322	6251	0	0
gen_low_level_sva.LowLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	100	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	8	0	0
T38	0	4	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T93	0	4	0	0
T144	0	2	0	0
T167	0	4	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	11852	0	0
T5	661	18	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	37	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	67	0	0
T35	0	291	0	0
T38	0	106	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	22	0	0
T93	0	114	0	0
T144	0	95	0	0
T167	0	66	0	0
T169	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323465	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	258	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3	0	0
T79	170533	1	0	0
T176	0	1	0	0
T196	1034	1	0	0
T209	522	0	0	0
T210	492	0	0	0
T211	709	0	0	0
T212	404	0	0	0
T213	589	0	0	0
T214	433	0	0	0
T215	4966	0	0	0
T216	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3589	0	0
T5	661	41	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	57	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	347	0	0
T35	0	214	0	0
T38	0	179	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	204	0	0
T144	0	136	0	0
T167	0	122	0	0
T169	0	46	0	0
T184	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	46	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	1	0	0
T35	0	4	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	2	0	0
T144	0	1	0	0
T167	0	2	0	0
T169	0	1	0	0
T184	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5171880	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	4	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5174263	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	4	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	51	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	1	0	0
T35	0	4	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T93	0	2	0	0
T144	0	1	0	0
T167	0	2	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	49	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	1	0	0
T35	0	4	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	2	0	0
T144	0	1	0	0
T167	0	2	0	0
T169	0	1	0	0
T184	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	46	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	1	0	0
T35	0	4	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	2	0	0
T144	0	1	0	0
T167	0	2	0	0
T169	0	1	0	0
T184	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	46	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	1	0	0
T35	0	4	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	2	0	0
T144	0	1	0	0
T167	0	2	0	0
T169	0	1	0	0
T184	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3519	0	0
T5	661	40	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	55	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	345	0	0
T35	0	207	0	0
T38	0	177	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	202	0	0
T144	0	134	0	0
T167	0	119	0	0
T169	0	44	0	0
T184	0	75	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	6251	0	0
T1	509	1	0	0
T2	30305	29	0	0
T3	12443	13	0	0
T4	39627	0	0	0
T5	661	1	0	0
T6	0	69	0	0
T11	695	0	0	0
T12	18017	29	0	0
T13	421	1	0	0
T14	593	0	0	0
T15	5141	29	0	0
T23	0	15	0	0
T24	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	22	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	2	0	0
T167	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T195	0	2	0	0
T217	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T22,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T7,T22,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T22,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T22,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T22,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T22,T36
0	1	Covered	T32,T218,T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T22,T36
0	1	Covered	T22,T36,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T22,T36
1	-	Covered	T22,T36,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T22,T36
DetectSt	168	Covered	T7,T22,T36
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T7,T22,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T22,T36
DebounceSt->IdleSt	163	Covered	T56,T145,T144
DetectSt->IdleSt	186	Covered	T32,T218,T176
DetectSt->StableSt	191	Covered	T7,T22,T36
IdleSt->DebounceSt	148	Covered	T7,T22,T36
StableSt->IdleSt	206	Covered	T7,T22,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T22,T36
0	1	Covered	T7,T22,T36
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T22,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T22,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T22,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T145,T144,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T22,T36
DetectSt	-	-	-	-	1	-	-	Covered	T32,T218,T176
DetectSt	-	-	-	-	0	1	-	Covered	T7,T22,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T36,T32
StableSt	-	-	-	-	-	-	0	Covered	T7,T22,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	154	0	0
CntIncr_A	5981322	111096	0	0
CntNoWrap_A	5981322	5323411	0	0
DetectStDropOut_A	5981322	4	0	0
DetectedOut_A	5981322	5409	0	0
DetectedPulseOut_A	5981322	70	0	0
DisabledIdleSt_A	5981322	4996583	0	0
DisabledNoDetection_A	5981322	4998956	0	0
EnterDebounceSt_A	5981322	81	0	0
EnterDetectSt_A	5981322	74	0	0
EnterStableSt_A	5981322	70	0	0
PulseIsPulse_A	5981322	70	0	0
StayInStableSt	5981322	5307	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	154	0	0
T7	2108	2	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	2	0	0
T32	0	4	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T56	0	1	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	111096	0	0
T7	2108	14	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	27	0	0
T32	0	134	0	0
T35	0	170	0	0
T36	0	72	0	0
T37	0	21	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T56	0	22	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T144	0	190	0	0
T145	0	58	0	0
T169	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323411	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4	0	0
T29	29098	0	0	0
T32	1016	1	0	0
T53	1497	0	0	0
T58	489	0	0	0
T69	16521	0	0	0
T86	9151	0	0	0
T104	29786	0	0	0
T176	0	1	0	0
T199	1415	0	0	0
T200	443	0	0	0
T201	603	0	0	0
T218	0	1	0	0
T219	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5409	0	0
T7	2108	41	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	2	0	0
T32	0	125	0	0
T35	0	85	0	0
T36	0	108	0	0
T37	0	47	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T93	0	221	0	0
T146	0	116	0	0
T167	0	63	0	0
T169	0	111	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	70	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T93	0	3	0	0
T146	0	2	0	0
T167	0	2	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4996583	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4998956	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	81	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	1	0	0
T32	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T56	0	1	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	74	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	1	0	0
T32	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T93	0	3	0	0
T146	0	2	0	0
T167	0	2	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	70	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T93	0	3	0	0
T146	0	2	0	0
T167	0	2	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	70	0	0
T7	2108	1	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T93	0	3	0	0
T146	0	2	0	0
T167	0	2	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5307	0	0
T7	2108	39	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T22	0	1	0	0
T32	0	124	0	0
T35	0	82	0	0
T36	0	105	0	0
T37	0	45	0	0
T43	7262	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T93	0	217	0	0
T146	0	114	0	0
T167	0	61	0	0
T169	0	110	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	38	0	0
T22	24860	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	657	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T47	682	0	0	0
T48	25906	0	0	0
T57	496	0	0	0
T93	0	2	0	0
T102	3525	0	0	0
T107	0	1	0	0
T146	0	2	0	0
T147	404	0	0	0
T167	0	2	0	0
T169	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T5,T10,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T10,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T22
0	1	Covered	T32,T128,T146
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T22
1	-	Covered	T32,T128,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T10,T22
DetectSt	168	Covered	T5,T10,T22
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T5,T10,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T22
DebounceSt->IdleSt	163	Covered	T56,T74,T220
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T10,T22
IdleSt->DebounceSt	148	Covered	T5,T10,T22
StableSt->IdleSt	206	Covered	T22,T32,T128

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T10,T22
0	1	Covered	T5,T10,T22
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T10,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T10,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T128,T146
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	86	0	0
CntIncr_A	5981322	59690	0	0
CntNoWrap_A	5981322	5323479	0	0
DetectStDropOut_A	5981322	0	0	0
DetectedOut_A	5981322	22741	0	0
DetectedPulseOut_A	5981322	42	0	0
DisabledIdleSt_A	5981322	4827853	0	0
DisabledNoDetection_A	5981322	4830229	0	0
EnterDebounceSt_A	5981322	45	0	0
EnterDetectSt_A	5981322	42	0	0
EnterStableSt_A	5981322	42	0	0
PulseIsPulse_A	5981322	42	0	0
StayInStableSt	5981322	22675	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5981322	6116	0	0
gen_low_level_sva.LowLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	86	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	2	0	0
T21	499	0	0	0
T22	0	4	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T67	0	2	0	0
T128	0	2	0	0
T145	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	59690	0	0
T5	661	18	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	4217	0	0
T21	499	0	0	0
T22	0	56	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	134	0	0
T33	0	26	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	23	0	0
T67	0	43	0	0
T128	0	80	0	0
T145	0	58	0	0
T169	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323479	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	258	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	22741	0	0
T5	661	39	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	15296	0	0
T21	499	0	0	0
T22	0	224	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	210	0	0
T33	0	42	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T67	0	88	0	0
T72	0	63	0	0
T128	0	173	0	0
T145	0	196	0	0
T169	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	42	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T67	0	1	0	0
T72	0	1	0	0
T128	0	1	0	0
T145	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4827853	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	4	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4830229	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	4	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	45	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T67	0	1	0	0
T128	0	1	0	0
T145	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	42	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T67	0	1	0	0
T72	0	1	0	0
T128	0	1	0	0
T145	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	42	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T67	0	1	0	0
T72	0	1	0	0
T128	0	1	0	0
T145	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	42	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T67	0	1	0	0
T72	0	1	0	0
T128	0	1	0	0
T145	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	22675	0	0
T5	661	37	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T10	0	15294	0	0
T21	499	0	0	0
T22	0	220	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	207	0	0
T33	0	40	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T67	0	86	0	0
T72	0	61	0	0
T128	0	172	0	0
T145	0	194	0	0
T169	0	104	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	6116	0	0
T1	509	1	0	0
T2	30305	28	0	0
T3	12443	10	0	0
T4	39627	0	0	0
T5	661	1	0	0
T6	0	68	0	0
T11	695	0	0	0
T12	18017	21	0	0
T13	421	2	0	0
T14	593	0	0	0
T15	5141	27	0	0
T23	0	12	0	0
T24	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	18	0	0
T29	29098	0	0	0
T32	1016	1	0	0
T53	1497	0	0	0
T58	489	0	0	0
T69	16521	0	0	0
T86	9151	0	0	0
T104	29786	0	0	0
T107	0	1	0	0
T128	0	1	0	0
T146	0	1	0	0
T156	0	1	0	0
T185	0	2	0	0
T195	0	1	0	0
T199	1415	0	0	0
T200	443	0	0	0
T201	603	0	0	0
T202	0	1	0	0
T204	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T2,T3,T11

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T5,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T11
1	1	Covered	T5,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T197
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T10
0	1	Covered	T5,T32,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T10
1	-	Covered	T5,T32,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T7
DetectSt	168	Covered	T5,T7,T10
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T5,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T10
DebounceSt->IdleSt	163	Covered	T6,T22,T56
DetectSt->IdleSt	186	Covered	T197
DetectSt->StableSt	191	Covered	T5,T7,T10
IdleSt->DebounceSt	148	Covered	T5,T6,T7
StableSt->IdleSt	206	Covered	T5,T7,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T10
0	1	Covered	T5,T6,T7
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T196,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T197
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T32,T35
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	129	0	0
CntIncr_A	5981322	49462	0	0
CntNoWrap_A	5981322	5323436	0	0
DetectStDropOut_A	5981322	1	0	0
DetectedOut_A	5981322	46655	0	0
DetectedPulseOut_A	5981322	60	0	0
DisabledIdleSt_A	5981322	5161757	0	0
DisabledNoDetection_A	5981322	5164141	0	0
EnterDebounceSt_A	5981322	69	0	0
EnterDetectSt_A	5981322	61	0	0
EnterStableSt_A	5981322	60	0	0
PulseIsPulse_A	5981322	60	0	0
StayInStableSt	5981322	46567	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	129	0	0
T5	661	4	0	0
T6	71572	0	0	0
T7	2108	2	0	0
T10	0	2	0	0
T21	499	0	0	0
T22	0	3	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	4	0	0
T35	0	2	0	0
T37	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T120	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	49462	0	0
T5	661	36	0	0
T6	71572	6130	0	0
T7	2108	14	0	0
T10	0	4217	0	0
T21	499	0	0	0
T22	0	64	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	134	0	0
T35	0	90	0	0
T37	0	21	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	36	0	0
T169	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323436	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	256	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1	0	0
T113	4924	0	0	0
T159	54728	0	0	0
T187	426	0	0	0
T188	1561	0	0	0
T189	422	0	0	0
T190	5316	0	0	0
T191	545	0	0	0
T192	23646	0	0	0
T197	6237	1	0	0
T222	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	46655	0	0
T5	661	169	0	0
T6	71572	0	0	0
T7	2108	55	0	0
T10	0	4890	0	0
T21	499	0	0	0
T22	0	60	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	126	0	0
T35	0	39	0	0
T37	0	88	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	52	0	0
T120	0	54	0	0
T169	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	60	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	1	0	0
T120	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5161757	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	4	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5164141	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	4	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	69	0	0
T5	661	2	0	0
T6	71572	1	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T120	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	61	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	1	0	0
T120	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	60	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	1	0	0
T120	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	60	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	1	0	0
T10	0	1	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	1	0	0
T120	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	46567	0	0
T5	661	166	0	0
T6	71572	0	0	0
T7	2108	53	0	0
T10	0	4888	0	0
T21	499	0	0	0
T22	0	58	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	124	0	0
T35	0	38	0	0
T37	0	86	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	51	0	0
T120	0	52	0	0
T169	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	32	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T72	0	1	0	0
T93	0	1	0	0
T107	0	1	0	0
T141	0	1	0	0
T144	0	1	0	0
T155	0	4	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T22,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T5,T22,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T22,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T11
1	1	Covered	T5,T22,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T32,T33
0	1	Covered	T5,T202,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T32,T33
0	1	Covered	T32,T33,T143
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T32,T33
1	-	Covered	T32,T33,T143

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T22,T32
DetectSt	168	Covered	T5,T22,T32
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T22,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T22,T32
DebounceSt->IdleSt	163	Covered	T56,T93,T74
DetectSt->IdleSt	186	Covered	T5,T202,T166
DetectSt->StableSt	191	Covered	T22,T32,T33
IdleSt->DebounceSt	148	Covered	T5,T22,T32
StableSt->IdleSt	206	Covered	T22,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T22,T32
0	1	Covered	T5,T22,T32
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T22,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T22,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T22,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T93
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T22,T32
DetectSt	-	-	-	-	1	-	-	Covered	T5,T202,T166
DetectSt	-	-	-	-	0	1	-	Covered	T22,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T143
StableSt	-	-	-	-	-	-	0	Covered	T22,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	105	0	0
CntIncr_A	5981322	56508	0	0
CntNoWrap_A	5981322	5323460	0	0
DetectStDropOut_A	5981322	3	0	0
DetectedOut_A	5981322	3775	0	0
DetectedPulseOut_A	5981322	48	0	0
DisabledIdleSt_A	5981322	4994254	0	0
DisabledNoDetection_A	5981322	4996623	0	0
EnterDebounceSt_A	5981322	54	0	0
EnterDetectSt_A	5981322	51	0	0
EnterStableSt_A	5981322	48	0	0
PulseIsPulse_A	5981322	48	0	0
StayInStableSt	5981322	3701	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5981322	6892	0	0
gen_low_level_sva.LowLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	105	0	0
T5	661	2	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T38	0	2	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T93	0	5	0	0
T143	0	2	0	0
T144	0	2	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	56508	0	0
T5	661	18	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	37	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	134	0	0
T33	0	26	0	0
T38	0	53	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	21	0	0
T93	0	206	0	0
T143	0	66	0	0
T144	0	95	0	0
T167	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5323460	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	258	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T166	0	1	0	0
T202	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3775	0	0
T22	24860	58	0	0
T32	0	210	0	0
T33	0	195	0	0
T36	657	0	0	0
T38	0	148	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T47	682	0	0	0
T48	25906	0	0	0
T57	496	0	0	0
T93	0	86	0	0
T102	3525	0	0	0
T107	0	68	0	0
T143	0	44	0	0
T144	0	137	0	0
T146	0	137	0	0
T147	404	0	0	0
T167	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	48	0	0
T22	24860	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	657	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T47	682	0	0	0
T48	25906	0	0	0
T57	496	0	0	0
T93	0	2	0	0
T102	3525	0	0	0
T107	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	404	0	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4994254	0	0
T1	509	108	0	0
T2	30305	29832	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	4	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4996623	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	4	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	54	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T56	0	1	0	0
T93	0	3	0	0
T143	0	1	0	0
T144	0	1	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	51	0	0
T5	661	1	0	0
T6	71572	0	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	1	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0
T42	2306	0	0	0
T49	402	0	0	0
T50	414	0	0	0
T93	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T146	0	3	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	48	0	0
T22	24860	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	657	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T47	682	0	0	0
T48	25906	0	0	0
T57	496	0	0	0
T93	0	2	0	0
T102	3525	0	0	0
T107	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	404	0	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	48	0	0
T22	24860	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	657	0	0	0
T38	0	1	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T47	682	0	0	0
T48	25906	0	0	0
T57	496	0	0	0
T93	0	2	0	0
T102	3525	0	0	0
T107	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	404	0	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3701	0	0
T22	24860	56	0	0
T32	0	207	0	0
T33	0	194	0	0
T36	657	0	0	0
T38	0	146	0	0
T44	678	0	0	0
T45	820	0	0	0
T46	619	0	0	0
T47	682	0	0	0
T48	25906	0	0	0
T57	496	0	0	0
T93	0	83	0	0
T102	3525	0	0	0
T107	0	67	0	0
T143	0	43	0	0
T144	0	135	0	0
T146	0	133	0	0
T147	404	0	0	0
T167	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	6892	0	0
T2	30305	32	0	0
T3	12443	11	0	0
T4	39627	6	0	0
T5	661	1	0	0
T6	71572	71	0	0
T11	695	3	0	0
T12	18017	26	0	0
T13	421	2	0	0
T14	593	0	0	0
T15	5141	29	0	0
T23	0	18	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	22	0	0
T29	29098	0	0	0
T32	1016	1	0	0
T33	0	1	0	0
T53	1497	0	0	0
T58	489	0	0	0
T69	16521	0	0	0
T86	9151	0	0	0
T93	0	1	0	0
T104	29786	0	0	0
T107	0	1	0	0
T143	0	1	0	0
T146	0	2	0	0
T155	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T183	0	1	0	0
T199	1415	0	0	0
T200	443	0	0	0
T201	603	0	0	0