Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T15
1	0	Covered	T2,T39,T31
1	1	Covered	T1,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T12,T15,T70
1	0	Covered	T122,T88,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T39
0	1	Covered	T2,T39,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T39
1	-	Covered	T2,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T12
DetectSt	168	Covered	T1,T2,T12
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T2,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T12
DebounceSt->IdleSt	163	Covered	T40,T56,T74
DetectSt->IdleSt	186	Covered	T12,T15,T70
DetectSt->StableSt	191	Covered	T1,T2,T39
IdleSt->DebounceSt	148	Covered	T1,T2,T12
StableSt->IdleSt	206	Covered	T2,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T56,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T15,T70
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T39
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	1	Covered	T2,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	3015	0	0
CntIncr_A	5981322	117444	0	0
CntNoWrap_A	5981322	5320550	0	0
DetectStDropOut_A	5981322	494	0	0
DetectedOut_A	5981322	77916	0	0
DetectedPulseOut_A	5981322	826	0	0
DisabledIdleSt_A	5981322	4818723	0	0
DisabledNoDetection_A	5981322	4820939	0	0
EnterDebounceSt_A	5981322	1523	0	0
EnterDetectSt_A	5981322	1494	0	0
EnterStableSt_A	5981322	826	0	0
PulseIsPulse_A	5981322	826	0	0
StayInStableSt	5981322	76958	0	0
gen_high_event_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	694	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3015	0	0
T1	509	2	0	0
T2	30305	48	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	52	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	38	0	0
T31	0	28	0	0
T39	0	40	0	0
T40	0	15	0	0
T41	0	64	0	0
T68	0	2	0	0
T69	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	117444	0	0
T1	509	21	0	0
T2	30305	1392	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	8007	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	929	0	0
T31	0	406	0	0
T39	0	1280	0	0
T40	0	2465	0	0
T41	0	1088	0	0
T68	0	21	0	0
T69	0	1080	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5320550	0	0
T1	509	106	0	0
T2	30305	29784	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17564	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4702	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	494	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T12	18017	26	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	19	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T56	0	1	0	0
T70	0	12	0	0
T88	0	4	0	0
T89	0	11	0	0
T90	0	8	0	0
T179	0	11	0	0
T223	0	21	0	0
T224	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	77916	0	0
T1	509	84	0	0
T2	30305	1748	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	1043	0	0
T31	0	730	0	0
T39	0	1902	0	0
T40	0	978	0	0
T41	0	1738	0	0
T68	0	33	0	0
T69	0	1171	0	0
T118	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	826	0	0
T1	509	1	0	0
T2	30305	24	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	18	0	0
T31	0	14	0	0
T39	0	20	0	0
T40	0	5	0	0
T41	0	32	0	0
T68	0	1	0	0
T69	0	18	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4818723	0	0
T1	509	3	0	0
T2	30305	24769	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	2015	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4820939	0	0
T1	509	3	0	0
T2	30305	24770	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	2015	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1523	0	0
T1	509	1	0	0
T2	30305	24	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	26	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	19	0	0
T31	0	14	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	0	32	0	0
T68	0	1	0	0
T69	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1494	0	0
T1	509	1	0	0
T2	30305	24	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	26	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	19	0	0
T31	0	14	0	0
T39	0	20	0	0
T40	0	5	0	0
T41	0	32	0	0
T68	0	1	0	0
T69	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	826	0	0
T1	509	1	0	0
T2	30305	24	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	18	0	0
T31	0	14	0	0
T39	0	20	0	0
T40	0	5	0	0
T41	0	32	0	0
T68	0	1	0	0
T69	0	18	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	826	0	0
T1	509	1	0	0
T2	30305	24	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	18	0	0
T31	0	14	0	0
T39	0	20	0	0
T40	0	5	0	0
T41	0	32	0	0
T68	0	1	0	0
T69	0	18	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	76958	0	0
T1	509	82	0	0
T2	30305	1714	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	1020	0	0
T31	0	715	0	0
T39	0	1880	0	0
T40	0	973	0	0
T41	0	1699	0	0
T68	0	31	0	0
T69	0	1151	0	0
T118	0	78	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	694	0	0
T2	30305	14	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	13	0	0
T31	0	13	0	0
T39	0	18	0	0
T40	0	5	0	0
T41	0	25	0	0
T56	0	5	0	0
T69	0	16	0	0
T123	0	3	0	0
T225	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T86,T87
1	0	Covered	T56,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T3,T6,T22
DetectSt->IdleSt	186	Covered	T43,T86,T87
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T6,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T43,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	1041	0	0
CntIncr_A	5981322	52775	0	0
CntNoWrap_A	5981322	5322524	0	0
DetectStDropOut_A	5981322	70	0	0
DetectedOut_A	5981322	18777	0	0
DetectedPulseOut_A	5981322	416	0	0
DisabledIdleSt_A	5981322	4931707	0	0
DisabledNoDetection_A	5981322	4933378	0	0
EnterDebounceSt_A	5981322	552	0	0
EnterDetectSt_A	5981322	490	0	0
EnterStableSt_A	5981322	416	0	0
PulseIsPulse_A	5981322	416	0	0
StayInStableSt	5981322	18327	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	380	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1041	0	0
T1	509	2	0	0
T2	30305	18	0	0
T3	12443	7	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	11	0	0
T8	0	2	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	11	0	0
T28	0	10	0	0
T39	0	4	0	0
T43	0	2	0	0
T48	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	52775	0	0
T1	509	25	0	0
T2	30305	432	0	0
T3	12443	366	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	703	0	0
T8	0	25	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	394	0	0
T28	0	780	0	0
T39	0	122	0	0
T43	0	80	0	0
T48	0	719	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5322524	0	0
T1	509	106	0	0
T2	30305	29814	0	0
T3	12443	12014	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	70	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T38	0	3	0	0
T43	7262	1	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T85	450	0	0	0
T86	0	5	0	0
T87	0	4	0	0
T92	0	4	0	0
T93	0	4	0	0
T94	0	4	0	0
T97	0	2	0	0
T98	0	6	0	0
T99	0	2	0	0
T100	426	0	0	0
T101	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	18777	0	0
T1	509	3	0	0
T2	30305	407	0	0
T3	12443	157	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	35	0	0
T8	0	4	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	325	0	0
T28	0	265	0	0
T31	0	274	0	0
T39	0	171	0	0
T48	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	416	0	0
T1	509	1	0	0
T2	30305	9	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	5	0	0
T8	0	1	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	5	0	0
T31	0	1	0	0
T39	0	2	0	0
T48	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4931707	0	0
T1	509	25	0	0
T2	30305	28094	0	0
T3	12443	8057	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4933378	0	0
T1	509	25	0	0
T2	30305	28096	0	0
T3	12443	8057	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	552	0	0
T1	509	1	0	0
T2	30305	9	0	0
T3	12443	4	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	6	0	0
T8	0	1	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	6	0	0
T28	0	5	0	0
T39	0	2	0	0
T43	0	1	0	0
T48	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	490	0	0
T1	509	1	0	0
T2	30305	9	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	5	0	0
T8	0	1	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	5	0	0
T39	0	2	0	0
T43	0	1	0	0
T48	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	416	0	0
T1	509	1	0	0
T2	30305	9	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	5	0	0
T8	0	1	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	5	0	0
T31	0	1	0	0
T39	0	2	0	0
T48	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	416	0	0
T1	509	1	0	0
T2	30305	9	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	5	0	0
T8	0	1	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	5	0	0
T31	0	1	0	0
T39	0	2	0	0
T48	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	18327	0	0
T1	509	2	0	0
T2	30305	398	0	0
T3	12443	154	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	30	0	0
T8	0	3	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	320	0	0
T28	0	260	0	0
T31	0	273	0	0
T39	0	167	0	0
T48	0	17	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	380	0	0
T1	509	1	0	0
T2	30305	9	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	0	5	0	0
T8	0	1	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	5	0	0
T31	0	1	0	0
T41	0	7	0	0
T48	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T15
1	0	Covered	T2,T39,T31
1	1	Covered	T2,T12,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T15
0	1	Covered	T12,T15,T41
1	0	Covered	T39,T41,T122

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T31
0	1	Covered	T2,T40,T31
1	0	Covered	T56,T226

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T31
1	-	Covered	T2,T40,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T15
DetectSt	168	Covered	T2,T12,T15
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T40,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T15
DebounceSt->IdleSt	163	Covered	T40,T56,T74
DetectSt->IdleSt	186	Covered	T12,T15,T39
DetectSt->StableSt	191	Covered	T2,T40,T31
IdleSt->DebounceSt	148	Covered	T2,T12,T15
StableSt->IdleSt	206	Covered	T2,T40,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T12,T15
0	1	Covered	T2,T12,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T15
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T56,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T15
DetectSt	-	-	-	-	1	-	-	Covered	T12,T15,T39
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T31
DetectSt	-	-	-	-	0	0	-	Covered	T2,T12,T15
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T31
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T31
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	2742	0	0
CntIncr_A	5981322	115808	0	0
CntNoWrap_A	5981322	5320823	0	0
DetectStDropOut_A	5981322	423	0	0
DetectedOut_A	5981322	75723	0	0
DetectedPulseOut_A	5981322	751	0	0
DisabledIdleSt_A	5981322	4816189	0	0
DisabledNoDetection_A	5981322	4818419	0	0
EnterDebounceSt_A	5981322	1388	0	0
EnterDetectSt_A	5981322	1356	0	0
EnterStableSt_A	5981322	751	0	0
PulseIsPulse_A	5981322	751	0	0
StayInStableSt	5981322	74853	0	0
gen_high_event_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	626	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	2742	0	0
T2	30305	12	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	52	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	14	0	0
T30	0	48	0	0
T31	0	52	0	0
T39	0	24	0	0
T40	0	27	0	0
T41	0	40	0	0
T69	0	10	0	0
T70	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	115808	0	0
T2	30305	234	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	8005	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	337	0	0
T30	0	1152	0	0
T31	0	884	0	0
T39	0	805	0	0
T40	0	4217	0	0
T41	0	995	0	0
T69	0	315	0	0
T70	0	1271	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5320823	0	0
T1	509	108	0	0
T2	30305	29820	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17564	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4726	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	423	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T12	18017	26	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	7	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T41	0	4	0	0
T56	0	1	0	0
T70	0	24	0	0
T89	0	22	0	0
T90	0	2	0	0
T179	0	13	0	0
T223	0	24	0	0
T227	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	75723	0	0
T2	30305	275	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	2365	0	0
T31	0	4145	0	0
T40	0	1948	0	0
T56	0	298	0	0
T69	0	351	0	0
T88	0	4987	0	0
T123	0	2843	0	0
T228	0	903	0	0
T229	0	6819	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	751	0	0
T2	30305	6	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	24	0	0
T31	0	26	0	0
T40	0	10	0	0
T56	0	5	0	0
T69	0	5	0	0
T88	0	12	0	0
T123	0	22	0	0
T228	0	15	0	0
T229	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4816189	0	0
T1	509	108	0	0
T2	30305	26218	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	2015	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	2016	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4818419	0	0
T1	509	109	0	0
T2	30305	26228	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	2015	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	2016	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1388	0	0
T2	30305	6	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	26	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	7	0	0
T30	0	24	0	0
T31	0	26	0	0
T39	0	12	0	0
T40	0	17	0	0
T41	0	20	0	0
T69	0	5	0	0
T70	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1356	0	0
T2	30305	6	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	26	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	7	0	0
T30	0	24	0	0
T31	0	26	0	0
T39	0	12	0	0
T40	0	10	0	0
T41	0	20	0	0
T69	0	5	0	0
T70	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	751	0	0
T2	30305	6	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	24	0	0
T31	0	26	0	0
T40	0	10	0	0
T56	0	5	0	0
T69	0	5	0	0
T88	0	12	0	0
T123	0	22	0	0
T228	0	15	0	0
T229	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	751	0	0
T2	30305	6	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	24	0	0
T31	0	26	0	0
T40	0	10	0	0
T56	0	5	0	0
T69	0	5	0	0
T88	0	12	0	0
T123	0	22	0	0
T228	0	15	0	0
T229	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	74853	0	0
T2	30305	268	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	2338	0	0
T31	0	4118	0	0
T40	0	1938	0	0
T56	0	293	0	0
T69	0	344	0	0
T88	0	4966	0	0
T123	0	2814	0	0
T228	0	885	0	0
T229	0	6785	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	626	0	0
T2	30305	5	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	21	0	0
T31	0	25	0	0
T40	0	10	0	0
T56	0	4	0	0
T69	0	3	0	0
T88	0	3	0	0
T123	0	15	0	0
T228	0	12	0	0
T229	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T48,T230,T92
1	0	Covered	T56,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T2,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T3,T6,T48
DetectSt->IdleSt	186	Covered	T48,T56,T230
DetectSt->StableSt	191	Covered	T2,T3,T6
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T6,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T48,T56,T230
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	890	0	0
CntIncr_A	5981322	50029	0	0
CntNoWrap_A	5981322	5322675	0	0
DetectStDropOut_A	5981322	47	0	0
DetectedOut_A	5981322	17057	0	0
DetectedPulseOut_A	5981322	368	0	0
DisabledIdleSt_A	5981322	4917108	0	0
DisabledNoDetection_A	5981322	4918789	0	0
EnterDebounceSt_A	5981322	473	0	0
EnterDetectSt_A	5981322	418	0	0
EnterStableSt_A	5981322	368	0	0
PulseIsPulse_A	5981322	368	0	0
StayInStableSt	5981322	16652	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	890	0	0
T2	30305	2	0	0
T3	12443	7	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	15	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	10	0	0
T28	0	6	0	0
T31	0	4	0	0
T48	0	7	0	0
T69	0	4	0	0
T86	0	6	0	0
T104	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	50029	0	0
T2	30305	64	0	0
T3	12443	504	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	886	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	645	0	0
T28	0	360	0	0
T31	0	72	0	0
T48	0	573	0	0
T69	0	122	0	0
T86	0	368	0	0
T104	0	139	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5322675	0	0
T1	509	108	0	0
T2	30305	29830	0	0
T3	12443	12014	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	47	0	0
T28	20221	0	0	0
T31	13387	0	0	0
T34	116074	0	0	0
T39	11819	0	0	0
T40	13719	0	0	0
T48	25906	3	0	0
T66	526	0	0	0
T68	458	0	0	0
T92	0	11	0	0
T98	0	4	0	0
T102	3525	0	0	0
T103	424	0	0	0
T139	0	1	0	0
T146	0	5	0	0
T153	0	2	0	0
T195	0	4	0	0
T230	0	3	0	0
T231	0	2	0	0
T232	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	17057	0	0
T2	30305	30	0	0
T3	12443	20	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	533	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	25	0	0
T28	0	267	0	0
T29	0	429	0	0
T31	0	562	0	0
T69	0	169	0	0
T86	0	8	0	0
T104	0	15	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	368	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	7	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T29	0	8	0	0
T31	0	2	0	0
T69	0	2	0	0
T86	0	2	0	0
T104	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4917108	0	0
T1	509	108	0	0
T2	30305	29558	0	0
T3	12443	8057	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4918789	0	0
T1	509	109	0	0
T2	30305	29569	0	0
T3	12443	8057	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	473	0	0
T2	30305	1	0	0
T3	12443	4	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	8	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T31	0	2	0	0
T48	0	4	0	0
T69	0	2	0	0
T86	0	4	0	0
T104	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	418	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	7	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T31	0	2	0	0
T48	0	3	0	0
T69	0	2	0	0
T86	0	2	0	0
T104	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	368	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	7	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T29	0	8	0	0
T31	0	2	0	0
T69	0	2	0	0
T86	0	2	0	0
T104	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	368	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	7	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T29	0	8	0	0
T31	0	2	0	0
T69	0	2	0	0
T86	0	2	0	0
T104	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	16652	0	0
T2	30305	29	0	0
T3	12443	17	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	526	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	20	0	0
T28	0	264	0	0
T29	0	421	0	0
T31	0	560	0	0
T69	0	165	0	0
T86	0	6	0	0
T104	0	14	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	329	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	7	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T29	0	8	0	0
T31	0	2	0	0
T86	0	2	0	0
T87	0	4	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T15
1	0	Covered	T2,T39,T31
1	1	Covered	T2,T12,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T15
0	1	Covered	T12,T15,T69
1	0	Covered	T39,T69,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T31
0	1	Covered	T2,T40,T31
1	0	Covered	T233

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T31
1	-	Covered	T2,T40,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T15
DetectSt	168	Covered	T2,T12,T15
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T40,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T15
DebounceSt->IdleSt	163	Covered	T40,T56,T74
DetectSt->IdleSt	186	Covered	T12,T15,T39
DetectSt->StableSt	191	Covered	T2,T40,T31
IdleSt->DebounceSt	148	Covered	T2,T12,T15
StableSt->IdleSt	206	Covered	T2,T40,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T12,T15
0	1	Covered	T2,T12,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T15
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T56,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T15
DetectSt	-	-	-	-	1	-	-	Covered	T12,T15,T39
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T31
DetectSt	-	-	-	-	0	0	-	Covered	T2,T12,T15
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T31
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T31
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	2994	0	0
CntIncr_A	5981322	119067	0	0
CntNoWrap_A	5981322	5320571	0	0
DetectStDropOut_A	5981322	404	0	0
DetectedOut_A	5981322	94335	0	0
DetectedPulseOut_A	5981322	923	0	0
DisabledIdleSt_A	5981322	4809854	0	0
DisabledNoDetection_A	5981322	4812083	0	0
EnterDebounceSt_A	5981322	1516	0	0
EnterDetectSt_A	5981322	1479	0	0
EnterStableSt_A	5981322	923	0	0
PulseIsPulse_A	5981322	923	0	0
StayInStableSt	5981322	93291	0	0
gen_high_event_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	787	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	2994	0	0
T2	30305	26	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	24	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	38	0	0
T30	0	16	0	0
T31	0	20	0	0
T39	0	40	0	0
T40	0	13	0	0
T41	0	52	0	0
T69	0	62	0	0
T70	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	119067	0	0
T2	30305	533	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	3687	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	929	0	0
T30	0	432	0	0
T31	0	420	0	0
T39	0	1339	0	0
T40	0	2749	0	0
T41	0	780	0	0
T69	0	2251	0	0
T70	0	687	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5320571	0	0
T1	509	108	0	0
T2	30305	29806	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17592	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4702	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	404	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T12	18017	12	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	19	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T56	0	1	0	0
T69	0	13	0	0
T70	0	13	0	0
T88	0	8	0	0
T89	0	6	0	0
T179	0	25	0	0
T180	0	3	0	0
T223	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	94335	0	0
T2	30305	1233	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	332	0	0
T31	0	810	0	0
T40	0	315	0	0
T41	0	2007	0	0
T56	0	350	0	0
T122	0	1836	0	0
T123	0	736	0	0
T225	0	1593	0	0
T228	0	2199	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	923	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	8	0	0
T31	0	10	0	0
T40	0	2	0	0
T41	0	26	0	0
T56	0	5	0	0
T122	0	28	0	0
T123	0	9	0	0
T225	0	17	0	0
T228	0	31	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4809854	0	0
T1	509	108	0	0
T2	30305	25423	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	2015	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	2017	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4812083	0	0
T1	509	109	0	0
T2	30305	25429	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	2015	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	2017	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1516	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	12	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	19	0	0
T30	0	8	0	0
T31	0	10	0	0
T39	0	20	0	0
T40	0	11	0	0
T41	0	26	0	0
T69	0	31	0	0
T70	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1479	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	12	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	19	0	0
T30	0	8	0	0
T31	0	10	0	0
T39	0	20	0	0
T40	0	2	0	0
T41	0	26	0	0
T69	0	31	0	0
T70	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	923	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	8	0	0
T31	0	10	0	0
T40	0	2	0	0
T41	0	26	0	0
T56	0	5	0	0
T122	0	28	0	0
T123	0	9	0	0
T225	0	17	0	0
T228	0	31	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	923	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	8	0	0
T31	0	10	0	0
T40	0	2	0	0
T41	0	26	0	0
T56	0	5	0	0
T122	0	28	0	0
T123	0	9	0	0
T225	0	17	0	0
T228	0	31	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	93291	0	0
T2	30305	1215	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	323	0	0
T31	0	798	0	0
T40	0	313	0	0
T41	0	1975	0	0
T56	0	345	0	0
T122	0	1807	0	0
T123	0	724	0	0
T225	0	1575	0	0
T228	0	2164	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	787	0	0
T2	30305	8	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	7	0	0
T31	0	8	0	0
T40	0	2	0	0
T41	0	20	0	0
T56	0	5	0	0
T122	0	27	0	0
T123	0	6	0	0
T225	0	16	0	0
T228	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T3,T43,T28
1	0	Covered	T56,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T22
0	1	Covered	T6,T22,T48
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T22
1	-	Covered	T6,T22,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T6,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T6,T22,T104
DetectSt->IdleSt	186	Covered	T3,T43,T28
DetectSt->StableSt	191	Covered	T2,T6,T22
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T6,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T22,T104
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T3,T43,T28
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T22
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T6,T22,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	944	0	0
CntIncr_A	5981322	52477	0	0
CntNoWrap_A	5981322	5322621	0	0
DetectStDropOut_A	5981322	102	0	0
DetectedOut_A	5981322	17698	0	0
DetectedPulseOut_A	5981322	342	0	0
DisabledIdleSt_A	5981322	4910430	0	0
DisabledNoDetection_A	5981322	4912126	0	0
EnterDebounceSt_A	5981322	498	0	0
EnterDetectSt_A	5981322	447	0	0
EnterStableSt_A	5981322	342	0	0
PulseIsPulse_A	5981322	342	0	0
StayInStableSt	5981322	17313	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	944	0	0
T2	30305	2	0	0
T3	12443	6	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	35	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	5	0	0
T28	0	8	0	0
T31	0	4	0	0
T41	0	10	0	0
T43	0	4	0	0
T48	0	6	0	0
T104	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	52477	0	0
T2	30305	59	0	0
T3	12443	439	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	2221	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	194	0	0
T28	0	836	0	0
T31	0	60	0	0
T41	0	125	0	0
T43	0	162	0	0
T48	0	387	0	0
T104	0	748	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5322621	0	0
T1	509	108	0	0
T2	30305	29830	0	0
T3	12443	12015	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	102	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T23	2625	0	0	0
T28	0	4	0	0
T38	0	12	0	0
T43	0	2	0	0
T87	0	13	0	0
T93	0	2	0	0
T94	0	7	0	0
T146	0	1	0	0
T230	0	1	0	0
T234	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	17698	0	0
T2	30305	33	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	938	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	126	0	0
T30	0	37	0	0
T31	0	575	0	0
T41	0	322	0	0
T48	0	111	0	0
T86	0	51	0	0
T104	0	342	0	0
T235	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	342	0	0
T2	30305	1	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	16	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	2	0	0
T30	0	1	0	0
T31	0	2	0	0
T41	0	5	0	0
T48	0	3	0	0
T86	0	8	0	0
T104	0	9	0	0
T235	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4910430	0	0
T1	509	108	0	0
T2	30305	28604	0	0
T3	12443	8057	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4912126	0	0
T1	509	109	0	0
T2	30305	28611	0	0
T3	12443	8057	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	498	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	19	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	3	0	0
T28	0	4	0	0
T31	0	2	0	0
T41	0	5	0	0
T43	0	2	0	0
T48	0	3	0	0
T104	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	447	0	0
T2	30305	1	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	16	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	2	0	0
T28	0	4	0	0
T31	0	2	0	0
T41	0	5	0	0
T43	0	2	0	0
T48	0	3	0	0
T104	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	342	0	0
T2	30305	1	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	16	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	2	0	0
T30	0	1	0	0
T31	0	2	0	0
T41	0	5	0	0
T48	0	3	0	0
T86	0	8	0	0
T104	0	9	0	0
T235	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	342	0	0
T2	30305	1	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	16	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	2	0	0
T30	0	1	0	0
T31	0	2	0	0
T41	0	5	0	0
T48	0	3	0	0
T86	0	8	0	0
T104	0	9	0	0
T235	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	17313	0	0
T2	30305	31	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	922	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	124	0	0
T30	0	36	0	0
T31	0	573	0	0
T41	0	317	0	0
T48	0	108	0	0
T86	0	43	0	0
T104	0	333	0	0
T235	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	297	0	0
T6	71572	16	0	0
T7	2108	0	0	0
T21	499	0	0	0
T22	0	2	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T41	0	5	0	0
T42	2306	0	0	0
T48	0	3	0	0
T49	402	0	0	0
T50	414	0	0	0
T51	439	0	0	0
T86	0	8	0	0
T104	0	9	0	0
T122	0	1	0	0
T235	0	1	0	0