Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T15
1	0	Covered	T2,T39,T31
1	1	Covered	T2,T12,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T15
0	1	Covered	T12,T15,T39
1	0	Covered	T39,T31,T122

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T41
0	1	Covered	T2,T40,T41
1	0	Covered	T76,T77,T236

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T41
1	-	Covered	T2,T40,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T15
DetectSt	168	Covered	T2,T12,T15
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T15
DebounceSt->IdleSt	163	Covered	T40,T56,T74
DetectSt->IdleSt	186	Covered	T12,T15,T39
DetectSt->StableSt	191	Covered	T2,T40,T41
IdleSt->DebounceSt	148	Covered	T2,T12,T15
StableSt->IdleSt	206	Covered	T2,T40,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T12,T15
0	1	Covered	T2,T12,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T15
IdleSt	0	-	-	-	-	-	-	Covered	T2,T12,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T56,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T15
DetectSt	-	-	-	-	1	-	-	Covered	T12,T15,T39
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T41
DetectSt	-	-	-	-	0	0	-	Covered	T2,T12,T15
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T41
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	3010	0	0
CntIncr_A	5981322	114218	0	0
CntNoWrap_A	5981322	5320555	0	0
DetectStDropOut_A	5981322	527	0	0
DetectedOut_A	5981322	61953	0	0
DetectedPulseOut_A	5981322	652	0	0
DisabledIdleSt_A	5981322	4831001	0	0
DisabledNoDetection_A	5981322	4833266	0	0
EnterDebounceSt_A	5981322	1521	0	0
EnterDetectSt_A	5981322	1491	0	0
EnterStableSt_A	5981322	652	0	0
PulseIsPulse_A	5981322	652	0	0
StayInStableSt	5981322	61218	0	0
gen_high_event_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	543	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	3010	0	0
T2	30305	26	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	32	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	58	0	0
T30	0	16	0	0
T31	0	38	0	0
T39	0	60	0	0
T40	0	13	0	0
T41	0	14	0	0
T69	0	60	0	0
T70	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	114218	0	0
T2	30305	806	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	4921	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	1419	0	0
T30	0	552	0	0
T31	0	1064	0	0
T39	0	1993	0	0
T40	0	2357	0	0
T41	0	189	0	0
T69	0	2130	0	0
T70	0	1384	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5320555	0	0
T1	509	108	0	0
T2	30305	29806	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17584	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4682	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	527	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T12	18017	16	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	29	0	0
T23	2625	0	0	0
T24	523	0	0	0
T25	610	0	0	0
T39	0	17	0	0
T56	0	1	0	0
T70	0	26	0	0
T88	0	3	0	0
T89	0	5	0	0
T122	0	7	0	0
T223	0	28	0	0
T225	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	61953	0	0
T2	30305	472	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	212	0	0
T40	0	640	0	0
T41	0	555	0	0
T56	0	367	0	0
T69	0	2220	0	0
T228	0	1438	0	0
T229	0	468	0	0
T237	0	2209	0	0
T238	0	1400	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	652	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	8	0	0
T40	0	4	0	0
T41	0	7	0	0
T56	0	5	0	0
T69	0	30	0	0
T228	0	22	0	0
T229	0	2	0	0
T237	0	21	0	0
T238	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4831001	0	0
T1	509	108	0	0
T2	30305	25914	0	0
T3	12443	12021	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	2015	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	2018	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4833266	0	0
T1	509	109	0	0
T2	30305	25923	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	2015	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	2018	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1521	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	16	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	29	0	0
T30	0	8	0	0
T31	0	19	0	0
T39	0	30	0	0
T40	0	9	0	0
T41	0	7	0	0
T69	0	30	0	0
T70	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	1491	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	16	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	29	0	0
T30	0	8	0	0
T31	0	19	0	0
T39	0	30	0	0
T40	0	4	0	0
T41	0	7	0	0
T69	0	30	0	0
T70	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	652	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	8	0	0
T40	0	4	0	0
T41	0	7	0	0
T56	0	5	0	0
T69	0	30	0	0
T228	0	22	0	0
T229	0	2	0	0
T237	0	21	0	0
T238	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	652	0	0
T2	30305	13	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	8	0	0
T40	0	4	0	0
T41	0	7	0	0
T56	0	5	0	0
T69	0	30	0	0
T228	0	22	0	0
T229	0	2	0	0
T237	0	21	0	0
T238	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	61218	0	0
T2	30305	457	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	203	0	0
T40	0	636	0	0
T41	0	546	0	0
T56	0	362	0	0
T69	0	2186	0	0
T228	0	1410	0	0
T229	0	466	0	0
T237	0	2187	0	0
T238	0	1371	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	543	0	0
T2	30305	11	0	0
T3	12443	0	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	0	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T30	0	7	0	0
T40	0	4	0	0
T41	0	5	0	0
T56	0	5	0	0
T69	0	26	0	0
T228	0	16	0	0
T229	0	2	0	0
T237	0	20	0	0
T238	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T43,T207,T239
1	0	Covered	T56,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T2,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T3,T6,T28
DetectSt->IdleSt	186	Covered	T43,T207,T56
DetectSt->StableSt	191	Covered	T2,T3,T6
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T6,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T43,T207,T56
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5981322	839	0	0
CntIncr_A	5981322	47170	0	0
CntNoWrap_A	5981322	5322726	0	0
DetectStDropOut_A	5981322	42	0	0
DetectedOut_A	5981322	15883	0	0
DetectedPulseOut_A	5981322	357	0	0
DisabledIdleSt_A	5981322	4940124	0	0
DisabledNoDetection_A	5981322	4941855	0	0
EnterDebounceSt_A	5981322	437	0	0
EnterDetectSt_A	5981322	403	0	0
EnterStableSt_A	5981322	357	0	0
PulseIsPulse_A	5981322	357	0	0
StayInStableSt	5981322	15494	0	0
gen_high_level_sva.HighLevelEvent_A	5981322	5326004	0	0
gen_not_sticky_sva.StableStDropOut_A	5981322	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	839	0	0
T2	30305	4	0	0
T3	12443	5	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	9	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	24	0	0
T28	0	17	0	0
T41	0	4	0	0
T43	0	8	0	0
T48	0	6	0	0
T69	0	4	0	0
T207	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	47170	0	0
T2	30305	110	0	0
T3	12443	288	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	611	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	912	0	0
T28	0	1657	0	0
T41	0	66	0	0
T43	0	323	0	0
T48	0	285	0	0
T69	0	186	0	0
T207	0	380	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5322726	0	0
T1	509	108	0	0
T2	30305	29828	0	0
T3	12443	12016	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	42	0	0
T8	484	0	0	0
T9	1490	0	0	0
T10	26612	0	0	0
T38	0	1	0	0
T43	7262	4	0	0
T63	505	0	0	0
T64	524	0	0	0
T65	505	0	0	0
T79	0	1	0	0
T85	450	0	0	0
T93	0	12	0	0
T100	426	0	0	0
T101	424	0	0	0
T153	0	5	0	0
T158	0	1	0	0
T207	0	3	0	0
T239	0	3	0	0
T240	0	1	0	0
T241	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	15883	0	0
T2	30305	77	0	0
T3	12443	88	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	174	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	697	0	0
T28	0	115	0	0
T29	0	207	0	0
T35	0	114	0	0
T41	0	114	0	0
T48	0	214	0	0
T69	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	357	0	0
T2	30305	2	0	0
T3	12443	2	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	4	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	12	0	0
T28	0	8	0	0
T29	0	3	0	0
T35	0	3	0	0
T41	0	2	0	0
T48	0	3	0	0
T69	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4940124	0	0
T1	509	108	0	0
T2	30305	29362	0	0
T3	12443	8057	0	0
T4	39627	39226	0	0
T5	661	260	0	0
T11	695	294	0	0
T12	18017	17616	0	0
T13	421	20	0	0
T14	593	192	0	0
T15	5141	4740	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	4941855	0	0
T1	509	109	0	0
T2	30305	29372	0	0
T3	12443	8057	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	437	0	0
T2	30305	2	0	0
T3	12443	3	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	5	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	12	0	0
T28	0	9	0	0
T41	0	2	0	0
T43	0	4	0	0
T48	0	3	0	0
T69	0	2	0	0
T207	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	403	0	0
T2	30305	2	0	0
T3	12443	2	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	4	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	12	0	0
T28	0	8	0	0
T41	0	2	0	0
T43	0	4	0	0
T48	0	3	0	0
T69	0	2	0	0
T207	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	357	0	0
T2	30305	2	0	0
T3	12443	2	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	4	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	12	0	0
T28	0	8	0	0
T29	0	3	0	0
T35	0	3	0	0
T41	0	2	0	0
T48	0	3	0	0
T69	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	357	0	0
T2	30305	2	0	0
T3	12443	2	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	4	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	12	0	0
T28	0	8	0	0
T29	0	3	0	0
T35	0	3	0	0
T41	0	2	0	0
T48	0	3	0	0
T69	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	15494	0	0
T2	30305	75	0	0
T3	12443	86	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	170	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	685	0	0
T28	0	107	0	0
T29	0	204	0	0
T35	0	111	0	0
T41	0	112	0	0
T48	0	211	0	0
T69	0	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	5326004	0	0
T1	509	109	0	0
T2	30305	29844	0	0
T3	12443	12025	0	0
T4	39627	39227	0	0
T5	661	261	0	0
T11	695	295	0	0
T12	18017	17617	0	0
T13	421	21	0	0
T14	593	193	0	0
T15	5141	4741	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5981322	320	0	0
T2	30305	2	0	0
T3	12443	2	0	0
T4	39627	0	0	0
T5	661	0	0	0
T6	71572	4	0	0
T11	695	0	0	0
T12	18017	0	0	0
T13	421	0	0	0
T14	593	0	0	0
T15	5141	0	0	0
T22	0	12	0	0
T28	0	8	0	0
T29	0	3	0	0
T35	0	3	0	0
T41	0	2	0	0
T48	0	3	0	0
T69	0	2	0	0