Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1422980777	8479	0	0
auto_block_debounce_ctl_rd_A	1422980777	1272	0	0
auto_block_out_ctl_rd_A	1422980777	1619	0	0
com_det_ctl_0_rd_A	1422980777	3413	0	0
com_det_ctl_1_rd_A	1422980777	3196	0	0
com_det_ctl_2_rd_A	1422980777	3281	0	0
com_det_ctl_3_rd_A	1422980777	3107	0	0
com_out_ctl_0_rd_A	1422980777	3672	0	0
com_out_ctl_1_rd_A	1422980777	3824	0	0
com_out_ctl_2_rd_A	1422980777	3775	0	0
com_out_ctl_3_rd_A	1422980777	3904	0	0
com_pre_det_ctl_0_rd_A	1422980777	958	0	0
com_pre_det_ctl_1_rd_A	1422980777	971	0	0
com_pre_det_ctl_2_rd_A	1422980777	986	0	0
com_pre_det_ctl_3_rd_A	1422980777	942	0	0
com_pre_sel_ctl_0_rd_A	1422980777	3812	0	0
com_pre_sel_ctl_1_rd_A	1422980777	3703	0	0
com_pre_sel_ctl_2_rd_A	1422980777	3939	0	0
com_pre_sel_ctl_3_rd_A	1422980777	3655	0	0
com_sel_ctl_0_rd_A	1422980777	3848	0	0
com_sel_ctl_1_rd_A	1422980777	3707	0	0
com_sel_ctl_2_rd_A	1422980777	3853	0	0
com_sel_ctl_3_rd_A	1422980777	3695	0	0
ec_rst_ctl_rd_A	1422980777	1984	0	0
intr_enable_rd_A	1422980777	1715	0	0
key_intr_ctl_rd_A	1422980777	1842	0	0
key_intr_debounce_ctl_rd_A	1422980777	933	0	0
key_invert_ctl_rd_A	1422980777	3145	0	0
pin_allowed_ctl_rd_A	1422980777	3564	0	0
pin_out_ctl_rd_A	1422980777	2715	0	0
pin_out_value_rd_A	1422980777	3182	0	0
regwen_rd_A	1422980777	1325	0	0
ulp_ac_debounce_ctl_rd_A	1422980777	1180	0	0
ulp_ctl_rd_A	1422980777	1017	0	0
ulp_lid_debounce_ctl_rd_A	1422980777	1111	0	0
ulp_pwrb_debounce_ctl_rd_A	1422980777	1185	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	8479	0	0
T6	880212	7	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T22	0	5	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T35	0	12	0	0
T38	0	6	0	0
T42	933976	5	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T72	0	4	0	0
T93	0	25	0	0
T102	0	6	0	0
T105	0	1	0	0
T120	0	11	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1272	0	0
T6	880212	26	0	0
T7	253051	5	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T95	0	16	0	0
T102	0	25	0	0
T149	0	9	0	0
T165	0	3	0	0
T271	0	5	0	0
T273	0	3	0	0
T274	0	12	0	0
T275	0	10	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1619	0	0
T6	880212	32	0	0
T7	253051	6	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T48	0	13	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T95	0	11	0	0
T102	0	3	0	0
T149	0	3	0	0
T165	0	10	0	0
T271	0	8	0	0
T273	0	13	0	0
T274	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3413	0	0
T3	622156	57	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	153	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	36	0	0
T29	0	41	0	0
T43	0	74	0	0
T48	0	61	0	0
T102	0	1	0	0
T122	0	24	0	0
T228	0	49	0	0
T239	0	34	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3196	0	0
T3	622156	78	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	134	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	53	0	0
T29	0	45	0	0
T43	0	50	0	0
T48	0	26	0	0
T102	0	8	0	0
T122	0	36	0	0
T228	0	66	0	0
T239	0	30	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3281	0	0
T3	622156	79	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	188	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	35	0	0
T29	0	23	0	0
T43	0	62	0	0
T48	0	27	0	0
T102	0	17	0	0
T122	0	47	0	0
T228	0	76	0	0
T239	0	29	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3107	0	0
T3	622156	60	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	150	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	25	0	0
T29	0	35	0	0
T43	0	64	0	0
T48	0	23	0	0
T102	0	23	0	0
T122	0	36	0	0
T228	0	56	0	0
T239	0	30	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3672	0	0
T3	622156	82	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	186	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	19	0	0
T29	0	48	0	0
T43	0	74	0	0
T48	0	54	0	0
T102	0	18	0	0
T122	0	31	0	0
T228	0	50	0	0
T239	0	50	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3824	0	0
T3	622156	82	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	211	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	65	0	0
T29	0	53	0	0
T43	0	66	0	0
T48	0	26	0	0
T102	0	10	0	0
T122	0	38	0	0
T228	0	85	0	0
T239	0	32	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3775	0	0
T3	622156	77	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	191	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	50	0	0
T29	0	36	0	0
T43	0	77	0	0
T48	0	72	0	0
T102	0	3	0	0
T122	0	40	0	0
T228	0	64	0	0
T239	0	43	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3904	0	0
T3	622156	61	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	149	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	43	0	0
T29	0	37	0	0
T43	0	76	0	0
T48	0	27	0	0
T102	0	14	0	0
T122	0	43	0	0
T228	0	78	0	0
T239	0	33	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	958	0	0
T6	880212	35	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T79	0	3	0	0
T80	0	28	0	0
T102	0	16	0	0
T156	0	16	0	0
T158	0	11	0	0
T166	0	42	0	0
T195	0	11	0	0
T276	0	1	0	0
T277	0	7	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	971	0	0
T6	880212	30	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T80	0	20	0	0
T102	0	17	0	0
T156	0	17	0	0
T158	0	14	0	0
T166	0	37	0	0
T195	0	15	0	0
T197	0	3	0	0
T276	0	10	0	0
T277	0	4	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	986	0	0
T6	880212	28	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T79	0	5	0	0
T80	0	18	0	0
T102	0	9	0	0
T156	0	22	0	0
T158	0	14	0	0
T166	0	30	0	0
T195	0	17	0	0
T276	0	18	0	0
T277	0	16	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	942	0	0
T6	880212	37	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T79	0	1	0	0
T80	0	23	0	0
T102	0	15	0	0
T156	0	17	0	0
T158	0	14	0	0
T166	0	43	0	0
T195	0	18	0	0
T276	0	3	0	0
T277	0	12	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3812	0	0
T3	622156	90	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	168	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	21	0	0
T29	0	27	0	0
T43	0	69	0	0
T48	0	33	0	0
T102	0	10	0	0
T122	0	27	0	0
T228	0	87	0	0
T239	0	42	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3703	0	0
T3	622156	80	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	148	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	35	0	0
T29	0	38	0	0
T43	0	60	0	0
T48	0	45	0	0
T102	0	5	0	0
T122	0	30	0	0
T228	0	55	0	0
T239	0	48	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3939	0	0
T3	622156	82	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	161	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	41	0	0
T29	0	45	0	0
T43	0	54	0	0
T48	0	45	0	0
T102	0	25	0	0
T122	0	31	0	0
T228	0	76	0	0
T239	0	40	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3655	0	0
T3	622156	52	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	144	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	28	0	0
T29	0	63	0	0
T43	0	58	0	0
T48	0	29	0	0
T102	0	22	0	0
T122	0	23	0	0
T228	0	51	0	0
T239	0	42	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3848	0	0
T3	622156	53	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	157	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	46	0	0
T29	0	30	0	0
T43	0	65	0	0
T48	0	26	0	0
T102	0	8	0	0
T122	0	40	0	0
T228	0	63	0	0
T239	0	48	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3707	0	0
T3	622156	58	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	158	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	28	0	0
T29	0	41	0	0
T43	0	70	0	0
T48	0	52	0	0
T102	0	18	0	0
T122	0	41	0	0
T228	0	75	0	0
T239	0	52	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3853	0	0
T3	622156	81	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	164	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	15	0	0
T29	0	30	0	0
T43	0	75	0	0
T48	0	27	0	0
T102	0	8	0	0
T122	0	30	0	0
T228	0	78	0	0
T239	0	49	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3695	0	0
T3	622156	63	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	173	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	43	0	0
T29	0	56	0	0
T43	0	46	0	0
T48	0	36	0	0
T102	0	17	0	0
T122	0	24	0	0
T228	0	67	0	0
T239	0	39	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1984	0	0
T3	622156	11	0	0
T4	57709	0	0	0
T5	303112	0	0	0
T6	880212	129	0	0
T11	90422	0	0	0
T12	441429	0	0	0
T13	100972	0	0	0
T14	154407	0	0	0
T15	179944	0	0	0
T23	446400	0	0	0
T28	0	2	0	0
T29	0	25	0	0
T43	0	9	0	0
T48	0	13	0	0
T102	0	19	0	0
T117	0	4	0	0
T122	0	8	0	0
T278	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1715	0	0
T6	880212	12	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T43	0	23	0	0
T48	0	13	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T102	0	11	0	0
T156	0	21	0	0
T158	0	5	0	0
T195	0	90	0	0
T276	0	11	0	0
T277	0	6	0	0
T279	0	22	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1842	0	0
T6	880212	22	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T33	0	2	0	0
T36	0	9	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T102	0	5	0	0
T128	0	4	0	0
T156	0	33	0	0
T168	0	1	0	0
T195	0	21	0	0
T276	0	9	0	0
T280	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	933	0	0
T6	880212	27	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T79	0	5	0	0
T80	0	16	0	0
T102	0	11	0	0
T156	0	21	0	0
T158	0	13	0	0
T166	0	45	0	0
T195	0	11	0	0
T276	0	11	0	0
T277	0	14	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3145	0	0
T6	880212	146	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T62	0	38	0	0
T102	0	5	0	0
T178	0	64	0	0
T195	0	11	0	0
T276	0	11	0	0
T279	0	31	0	0
T281	0	85	0	0
T282	0	74	0	0
T283	0	80	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3564	0	0
T6	880212	98	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T102	0	4	0	0
T156	0	18	0	0
T195	0	77	0	0
T276	0	5	0	0
T284	0	72	0	0
T285	0	64	0	0
T286	0	37	0	0
T287	0	68	0	0
T288	0	87	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	2715	0	0
T6	880212	78	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T102	0	9	0	0
T156	0	18	0	0
T195	0	68	0	0
T276	0	6	0	0
T284	0	72	0	0
T285	0	54	0	0
T286	0	34	0	0
T287	0	78	0	0
T288	0	52	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	3182	0	0
T6	880212	103	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T102	0	8	0	0
T156	0	13	0	0
T195	0	88	0	0
T276	0	15	0	0
T284	0	103	0	0
T285	0	63	0	0
T286	0	47	0	0
T287	0	79	0	0
T288	0	77	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1325	0	0
T6	880212	38	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T79	0	13	0	0
T80	0	21	0	0
T102	0	10	0	0
T156	0	28	0	0
T158	0	25	0	0
T166	0	39	0	0
T195	0	6	0	0
T276	0	10	0	0
T277	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1180	0	0
T6	880212	33	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T53	0	12	0	0
T73	0	8	0	0
T78	0	9	0	0
T81	0	5	0	0
T102	0	14	0	0
T108	0	2	0	0
T156	0	32	0	0
T195	0	20	0	0
T276	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1017	0	0
T6	880212	27	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T53	0	8	0	0
T73	0	9	0	0
T78	0	12	0	0
T81	0	7	0	0
T102	0	1	0	0
T156	0	28	0	0
T158	0	13	0	0
T195	0	22	0	0
T276	0	15	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1111	0	0
T6	880212	28	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T53	0	14	0	0
T73	0	8	0	0
T78	0	12	0	0
T102	0	20	0	0
T156	0	29	0	0
T158	0	34	0	0
T195	0	12	0	0
T276	0	18	0	0
T289	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1422980777	1185	0	0
T6	880212	38	0	0
T7	253051	0	0	0
T21	62414	0	0	0
T23	446400	0	0	0
T24	130921	0	0	0
T25	152701	0	0	0
T42	933976	0	0	0
T49	104822	0	0	0
T50	103503	0	0	0
T51	52749	0	0	0
T53	0	6	0	0
T73	0	11	0	0
T78	0	13	0	0
T81	0	2	0	0
T102	0	4	0	0
T108	0	8	0	0
T156	0	29	0	0
T195	0	21	0	0
T276	0	13	0	0