Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1981

1

T2

6

T3

6

T6

30

auto[1]

588

1

T2

2

T3

2

T6

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1934

1

T2

6

T3

8

T6

32

auto[1]

635

1

T2

2

T17

1

T10

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1867

1

T2

8

T3

2

T6

32

auto[1]

702

1

T3

6

T8

13

T10

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1892

1

T2

2

T3

6

T6

27

auto[1]

677

1

T2

6

T3

2

T6

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T2

8

T3

8

T6

32

auto[1]

227

1

T7

4

T10

1

T64

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2388

1

T2

8

T3

8

T6

25

auto[1]

181

1

T6

7

T7

5

T64

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2400

1

T2

8

T3

8

T6

25

auto[1]

169

1

T6

7

T17

1

T42

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T2

8

T3

8

T6

25

auto[1]

188

1

T6

7

T7

1

T10

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2370

1

T2

8

T3

8

T6

32

auto[1]

199

1

T10

1

T65

7

T142

18

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1898

1

T6

27

T7

19

T17

3

auto[1]

671

1

T2

8

T3

8

T6

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1018	1			T2	8		T3	8		T8	13
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	84	1			T64	3		T263	5		T355	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	75	1			T142	18		T272	11		T355	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	31	1			T10	1		T243	5		T226	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	74	1			T27	4		T263	6		T369	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	17	1			T370	2		T371	2		T372	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	25	1			T65	6		T370	1		T373	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T374	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	51	1			T42	1		T262	3		T375	16
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	13	1			T354	3		T376	2		T365	8
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T373	3		T377	3		T371	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T378	2		T365	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	10	1			T6	5		T370	2		T379	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T359	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T83	4		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	4	1			T380	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	53	1			T6	5		T261	1		T263	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	29	1			T272	5		T71	1		T373	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	13	1			T376	1		T381	5		T382	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	12	1			T7	1		T142	1		T264	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T365	5		T383	5		T384	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T385	1		T374	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	19	1			T64	6		T27	1		T260	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T359	3		T386	1		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T65	1		T272	2		T387	1
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T6	2		T388	2		T383	2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

103

1

T6

2

T65

1

T238

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

135

1

T6

5

T7

1

T11

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T105

6

T369

1

T268

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

108

1

T6

5

T144

2

T272

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

65

1

T262

3

T355

1

T375

16

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

86

1

T2

6

T42

1

T266

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T3

2

T64

6

T143

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

114

1

T8

13

T65

6

T272

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

58

1

T105

8

T355

1

T135

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T3

6

T142

1

T118

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T261

1

T143

2

T268

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

68

1

T11

4

T375

10

T376

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T11

2

T161

3

T125

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T103

5

T263

3

T370

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T29

3

T238

2

T389

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T10

1

T27

4

T105

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

60

1

T83

4

T370

2

T352

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T103

9

T263

11

T355

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T2

2

T145

3

T313

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T147

3

T266

5

T313

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T238

3

T390

1

T264

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T357

2

T251

1

T371

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T352

1

T135

1

T88

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

114

1

T11

5

T29

8

T103

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T369

2

T354

3

T120

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T147

7

T107

2

T161

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T105

1

T238

2

T84

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T145

2

T147

1

T354

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T142

9

T148

1

T356

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T64

3

T145

1

T309

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T91

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded