Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T5

12

T15

10

T48

8

auto[1]

1101

1

T5

8

T15

10

T48

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T5

4

T15

4

T48

3

from_0to1

525

1

T5

5

T15

5

T48

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T5

11

T15

9

T48

10

auto[1]

1110

1

T5

9

T15

11

T48

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T5

9

T15

10

T48

11

auto[1]

1074

1

T5

11

T15

10

T48

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T5

1

T48

1

T183

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T5

2

T350

1

T23

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T183

2

T280

2

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T15

1

T48

1

T23

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T5

1

T23

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T15

2

T350

1

T309

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T15

2

T48

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T5

2

T280

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T63

1

T350

1

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T5

1

T15

3

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T60

1

T350

2

T183

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T63

2

T350

1

T23

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T5

1

T15

1

T63

2

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T63

1

T350

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T48

3

T60

1

T350

1

auto[1]

from_0to1

auto[1]

auto[1]

83

1

T60

1

T23

2

T280

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T5

8

T15

10

T48

10

auto[1]

1042

1

T5

12

T15

10

T48

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T5

7

T15

5

T48

6

from_0to1

544

1

T5

6

T15

5

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T5

11

T15

11

T48

12

auto[1]

1097

1

T5

9

T15

9

T48

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T5

9

T15

11

T48

13

auto[1]

1121

1

T5

11

T15

9

T48

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T60

3

T350

1

T183

2

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T15

2

T48

1

T350

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T63

1

T350

1

T23

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T5

2

T60

1

T183

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T5

2

T15

1

T350

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T15

2

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T48

1

T38

1

T159

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T5

1

T48

1

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T5

3

T48

1

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T15

1

T48

1

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T5

2

T15

2

T48

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T48

1

T63

1

T280

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T15

1

T48

2

T183

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T5

2

T63

1

T350

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T15

1

T60

1

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T60

3

T350

1

T23

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T5

10

T15

8

T48

11

auto[1]

1102

1

T5

10

T15

12

T48

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T5

5

T15

5

T48

5

from_0to1

536

1

T5

4

T15

6

T48

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T5

14

T15

12

T48

11

auto[1]

1073

1

T5

6

T15

8

T48

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T5

9

T15

10

T48

7

auto[1]

1104

1

T5

11

T15

10

T48

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T5

2

T48

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T5

1

T15

1

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T63

2

T23

1

T38

2

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T48

2

T60

1

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T5

1

T15

1

T183

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T15

2

T48

2

T350

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T48

1

T60

1

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T5

1

T350

1

T183

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T5

1

T15

3

T350

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T5

1

T48

1

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T15

1

T60

2

T159

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T60

1

T183

1

T23

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T60

4

T63

1

T350

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T5

2

T15

1

T48

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T15

1

T183

1

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T15

1

T63

1

T23

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T5

8

T15

11

T48

8

auto[1]

1094

1

T5

12

T15

9

T48

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T5

2

T15

5

T48

4

from_0to1

511

1

T5

1

T15

4

T48

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T5

9

T15

14

T48

11

auto[1]

1092

1

T5

11

T15

6

T48

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T5

9

T15

7

T48

10

auto[1]

1099

1

T5

11

T15

13

T48

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T5

1

T350

1

T183

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T15

2

T60

2

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T15

1

T23

1

T280

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T5

1

T15

1

T63

2

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T48

1

T60

1

T350

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T48

1

T63

1

T350

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T48

2

T350

1

T183

2

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T5

1

T15

3

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T48

1

T60

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

84

1

T15

1

T48

1

T280

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T48

2

T63

1

T183

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T60

1

T350

1

T183

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T60

1

T350

1

T183

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T15

1

T60

1

T350

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T60

1

T63

2

T280

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T60

2

T63

2

T350

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T5

13

T15

8

T48

10

auto[1]

1053

1

T5

7

T15

12

T48

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T5

5

T15

4

T48

5

from_0to1

525

1

T5

4

T15

5

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T5

10

T15

8

T48

11

auto[1]

1144

1

T5

10

T15

12

T48

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T5

10

T15

13

T48

10

auto[1]

1131

1

T5

10

T15

7

T48

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T48

1

T60

1

T280

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T5

2

T183

1

T401

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T5

1

T15

1

T350

2

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T48

2

T60

1

T183

2

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T5

2

T48

1

T350

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T15

2

T48

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T15

1

T48

1

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T5

1

T48

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T15

1

T60

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T15

1

T63

1

T350

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T48

2

T63

1

T280

2

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T5

2

T15

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T5

1

T48

1

T350

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T60

2

T350

1

T183

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T15

1

T60

2

T350

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T15

1

T60

1

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T5

9

T15

11

T48

12

auto[1]

1077

1

T5

11

T15

9

T48

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T5

3

T15

5

T48

3

from_0to1

523

1

T5

4

T15

6

T48

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T5

13

T15

9

T48

8

auto[1]

1080

1

T5

7

T15

11

T48

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T5

7

T15

11

T48

8

auto[1]

1110

1

T5

13

T15

9

T48

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T15

1

T48

1

T350

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T15

1

T48

1

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T15

1

T183

3

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T48

1

T60

1

T63

2

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T15

1

T63

1

T38

3

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T5

1

T15

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T63

1

T350

1

T183

2

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T5

1

T60

2

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T5

1

T15

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T60

1

T63

2

T350

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T5

1

T15

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T5

1

T60

2

T350

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T5

1

T60

2

T350

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T5

1

T48

1

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T15

1

T48

1

T183

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T15

3

T60

1

T23

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T5

9

T15

7

T48

8

auto[1]

1086

1

T5

11

T15

13

T48

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T5

4

T15

5

T48

7

from_0to1

513

1

T5

4

T15

5

T48

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T5

9

T15

11

T48

10

auto[1]

1081

1

T5

11

T15

9

T48

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T5

9

T15

12

T48

10

auto[1]

1115

1

T5

11

T15

8

T48

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T15

1

T48

2

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T5

2

T48

1

T60

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T5

1

T15

1

T48

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T63

1

T38

1

T159

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T350

1

T183

1

T23

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T5

1

T15

1

T60

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T15

1

T48

2

T280

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T350

1

T159

1

T136

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T15

2

T350

1

T183

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T5

1

T48

2

T350

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T15

1

T60

1

T350

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T48

1

T60

1

T183

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T15

1

T48

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T5

1

T48

2

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T5

1

T60

1

T280

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T5

1

T15

2

T48

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T5

14

T15

14

T48

12

auto[1]

1032

1

T5

6

T15

6

T48

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T5

5

T15

6

T48

5

from_0to1

508

1

T5

6

T15

5

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T5

8

T15

10

T48

12

auto[1]

1121

1

T5

12

T15

10

T48

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T5

12

T15

14

T48

10

auto[1]

1033

1

T5

8

T15

6

T48

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T5

1

T15

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T15

2

T60

3

T23

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T5

1

T15

2

T48

3

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T23

1

T280

2

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T15

1

T350

1

T183

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T60

2

T63

2

T350

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T5

3

T15

1

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T5

1

T48

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T5

1

T48

1

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T5

1

T60

1

T63

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T63

1

T183

1

T23

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T5

1

T15

1

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T5

2

T15

1

T48

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T48

2

T60

1

T63

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T15

1

T60

1

T183

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T15

1

T60

1

T63

1