Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113248

1

T4

27

T5

51

T1

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134923	1			T4	33		T5	62		T1	18
values[0x0]	63241	1			T4	11		T5	30		T1	3
values[0x1]	63855	1			T4	15		T5	30		T1	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141657

1

T4

41

T5

66

T1

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	711	1			T2	2		T6	4		T7	5
valid_sources[0x01]	1000	1			T3	1		T14	1		T6	6
valid_sources[0x02]	795	1			T15	1		T6	5		T7	5
valid_sources[0x03]	720	1			T4	1		T2	12		T15	1
valid_sources[0x04]	769	1			T15	1		T6	4		T7	3
valid_sources[0x05]	1956	1			T4	1		T6	7		T7	2
valid_sources[0x06]	797	1			T4	1		T3	2		T15	1
valid_sources[0x07]	729	1			T4	1		T3	2		T6	2
valid_sources[0x08]	1837	1			T5	8		T6	4		T7	7
valid_sources[0x09]	1774	1			T5	2		T15	2		T6	3
valid_sources[0x0a]	854	1			T6	6		T42	4		T60	4
valid_sources[0x0b]	882	1			T5	1		T3	4		T15	2
valid_sources[0x0c]	843	1			T2	16		T3	12		T15	1
valid_sources[0x0d]	973	1			T2	5		T15	2		T6	5
valid_sources[0x0e]	703	1			T15	1		T6	7		T17	4
valid_sources[0x0f]	1754	1			T2	3		T14	1		T6	4
valid_sources[0x10]	779	1			T2	9		T6	6		T52	3
valid_sources[0x11]	826	1			T2	2		T6	1		T17	1
valid_sources[0x12]	907	1			T5	2		T15	2		T6	9
valid_sources[0x13]	843	1			T14	2		T6	2		T7	11
valid_sources[0x14]	747	1			T1	1		T15	3		T6	9
valid_sources[0x15]	786	1			T1	1		T6	5		T17	3
valid_sources[0x16]	875	1			T6	5		T17	6		T53	1
valid_sources[0x17]	792	1			T2	5		T3	1		T6	6
valid_sources[0x18]	911	1			T4	1		T15	1		T6	5
valid_sources[0x19]	869	1			T5	1		T3	6		T15	1
valid_sources[0x1a]	755	1			T2	5		T3	3		T14	1
valid_sources[0x1b]	966	1			T14	3		T6	2		T17	2
valid_sources[0x1c]	964	1			T4	1		T5	6		T2	3
valid_sources[0x1d]	1927	1			T3	3		T6	7		T7	3
valid_sources[0x1e]	811	1			T2	3		T6	5		T7	9
valid_sources[0x1f]	766	1			T1	1		T15	1		T7	3
valid_sources[0x20]	909	1			T2	7		T3	10		T14	2
valid_sources[0x21]	1217	1			T5	1		T2	13		T15	2
valid_sources[0x22]	1157	1			T2	4		T6	7		T7	2
valid_sources[0x23]	962	1			T2	3		T6	7		T17	2
valid_sources[0x24]	921	1			T2	1		T3	7		T15	3
valid_sources[0x25]	923	1			T2	5		T3	8		T6	3
valid_sources[0x26]	1412	1			T2	8		T3	3		T15	1
valid_sources[0x27]	814	1			T2	1		T3	3		T6	2
valid_sources[0x28]	879	1			T4	2		T1	1		T15	2
valid_sources[0x29]	983	1			T4	1		T3	6		T15	1
valid_sources[0x2a]	1055	1			T3	22		T6	7		T17	3
valid_sources[0x2b]	951	1			T2	12		T15	3		T6	3
valid_sources[0x2c]	735	1			T4	1		T5	1		T2	6
valid_sources[0x2d]	722	1			T15	1		T6	4		T7	8
valid_sources[0x2e]	884	1			T14	10		T6	3		T7	1
valid_sources[0x2f]	970	1			T6	8		T17	1		T21	3
valid_sources[0x30]	1374	1			T3	3		T15	1		T6	4
valid_sources[0x31]	1761	1			T15	1		T6	6		T7	3
valid_sources[0x32]	832	1			T2	16		T15	2		T6	2
valid_sources[0x33]	806	1			T4	2		T3	8		T15	2
valid_sources[0x34]	871	1			T6	3		T17	7		T21	1
valid_sources[0x35]	1310	1			T4	2		T5	4		T3	10
valid_sources[0x36]	2003	1			T2	7		T3	6		T15	1
valid_sources[0x37]	812	1			T2	3		T15	1		T6	4
valid_sources[0x38]	1848	1			T3	8		T6	5		T7	1
valid_sources[0x39]	866	1			T2	4		T3	9		T15	1
valid_sources[0x3a]	776	1			T15	2		T6	5		T17	4
valid_sources[0x3b]	947	1			T2	6		T6	5		T7	2
valid_sources[0x3c]	852	1			T6	8		T17	2		T21	1
valid_sources[0x3d]	884	1			T3	1		T15	1		T6	3
valid_sources[0x3e]	889	1			T6	4		T17	2		T21	4
valid_sources[0x3f]	769	1			T15	1		T6	4		T7	3
valid_sources[0x40]	1053	1			T4	1		T6	6		T7	9
valid_sources[0x41]	714	1			T6	2		T17	2		T21	1
valid_sources[0x42]	857	1			T2	1		T3	6		T15	1
valid_sources[0x43]	881	1			T6	3		T7	12		T17	1
valid_sources[0x44]	1430	1			T15	1		T6	5		T7	1
valid_sources[0x45]	961	1			T2	1		T3	1		T15	1
valid_sources[0x46]	828	1			T2	6		T6	3		T17	3
valid_sources[0x47]	948	1			T4	1		T14	1		T7	1
valid_sources[0x48]	967	1			T6	4		T7	5		T17	10
valid_sources[0x49]	879	1			T2	5		T15	1		T6	4
valid_sources[0x4a]	860	1			T5	2		T3	2		T15	1
valid_sources[0x4b]	1742	1			T2	6		T15	3		T6	1
valid_sources[0x4c]	1396	1			T4	1		T6	3		T17	4
valid_sources[0x4d]	987	1			T3	1		T6	4		T7	2
valid_sources[0x4e]	763	1			T6	3		T7	3		T17	3
valid_sources[0x4f]	984	1			T15	1		T6	10		T7	1
valid_sources[0x50]	957	1			T2	7		T6	1		T7	2
valid_sources[0x51]	765	1			T2	15		T6	7		T7	3
valid_sources[0x52]	590	1			T5	1		T15	1		T6	6
valid_sources[0x53]	1105	1			T4	1		T6	7		T7	12
valid_sources[0x54]	828	1			T3	7		T6	4		T17	1
valid_sources[0x55]	868	1			T1	1		T2	2		T3	7
valid_sources[0x56]	882	1			T6	2		T7	2		T17	1
valid_sources[0x57]	1546	1			T1	1		T6	3		T7	7
valid_sources[0x58]	696	1			T3	1		T15	1		T6	7
valid_sources[0x59]	895	1			T2	4		T14	4		T15	1
valid_sources[0x5a]	843	1			T6	6		T7	5		T17	4
valid_sources[0x5b]	956	1			T4	1		T1	1		T3	5
valid_sources[0x5c]	820	1			T3	3		T6	2		T7	10
valid_sources[0x5d]	991	1			T15	1		T6	3		T17	3
valid_sources[0x5e]	761	1			T5	8		T2	7		T15	2
valid_sources[0x5f]	2151	1			T14	2		T15	2		T6	4
valid_sources[0x60]	833	1			T1	2		T15	1		T17	3
valid_sources[0x61]	681	1			T4	2		T5	3		T3	2
valid_sources[0x62]	928	1			T2	2		T15	3		T6	7
valid_sources[0x63]	955	1			T3	7		T6	3		T17	2
valid_sources[0x64]	841	1			T6	3		T7	5		T49	1
valid_sources[0x65]	1035	1			T3	10		T6	2		T7	2
valid_sources[0x66]	884	1			T4	1		T5	1		T15	2
valid_sources[0x67]	877	1			T1	1		T2	6		T6	2
valid_sources[0x68]	1000	1			T3	2		T15	1		T6	2
valid_sources[0x69]	923	1			T5	11		T3	3		T15	1
valid_sources[0x6a]	1307	1			T3	12		T6	2		T7	11
valid_sources[0x6b]	1939	1			T5	2		T6	5		T17	4
valid_sources[0x6c]	1073	1			T4	2		T5	1		T6	6
valid_sources[0x6d]	762	1			T2	1		T6	3		T7	2
valid_sources[0x6e]	1022	1			T2	9		T3	16		T6	5
valid_sources[0x6f]	1419	1			T5	1		T15	1		T6	3
valid_sources[0x70]	1096	1			T5	1		T15	1		T6	6
valid_sources[0x71]	963	1			T2	11		T6	4		T7	2
valid_sources[0x72]	899	1			T5	5		T6	3		T42	3
valid_sources[0x73]	785	1			T5	1		T15	2		T6	8
valid_sources[0x74]	816	1			T15	3		T6	4		T7	10
valid_sources[0x75]	1906	1			T4	3		T6	6		T7	3
valid_sources[0x76]	921	1			T6	5		T17	5		T21	1
valid_sources[0x77]	808	1			T1	1		T15	3		T6	3
valid_sources[0x78]	602	1			T6	4		T7	6		T21	1
valid_sources[0x79]	1052	1			T15	1		T6	2		T7	5
valid_sources[0x7a]	1060	1			T6	4		T7	4		T17	7
valid_sources[0x7b]	756	1			T4	1		T2	6		T6	4
valid_sources[0x7c]	1138	1			T6	5		T17	4		T21	2
valid_sources[0x7d]	1039	1			T4	1		T2	2		T15	2
valid_sources[0x7e]	961	1			T5	1		T6	4		T7	2
valid_sources[0x7f]	742	1			T15	1		T6	4		T7	4
valid_sources[0x80]	1428	1			T2	1		T15	1		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61508

1

T4

17

T5

33

T1

6

values[0x0]

all_enables

biggest_size

30359

1

T4

7

T5

11

T1

1

values[0x1]

all_enables

biggest_size

21381

1

T4

3

T5

7

T2

12