Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

119 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137

1

T283

2

T286

3

T298

1

auto[1]

376

1

T16

3

T38

4

T44

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210

1

T25

1

T289

4

T283

3

auto[1]

765

1

T16

3

T23

3

T38

4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126

1

T283

4

T286

3

T298

1

auto[1]

500

1

T16

3

T38

3

T44

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116

1

T283

3

T286

1

T391

1

auto[1]

399

1

T16

3

T38

2

T44

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110

1

T283

2

T286

1

T298

1

auto[1]

506

1

T16

3

T23

3

T38

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115

1

T24

1

T283

2

T286

2

auto[1]

408

1

T16

2

T23

1

T38

4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116

1

T283

3

T286

1

T298

1

auto[1]

509

1

T16

1

T23

2

T38

4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110

1

T283

3

T286

1

T295

1

auto[1]

527

1

T16

1

T38

3

T44

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197

1

T24

2

T289

3

T283

6

auto[1]

3086

1

T2

20

T3

20

T6

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229

1

T24

2

T25

8

T289

3

auto[1]

3026

1

T2

20

T3

20

T6

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231

1

T24

4

T25

9

T289

1

auto[1]

3074

1

T2

20

T3

20

T6

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212

1

T24

2

T25

12

T289

2

auto[1]

3081

1

T2

20

T3

20

T6

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119

1

T24

1

T289

5

T283

2

auto[1]

1548

1

T3

20

T7

11

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113

1

T24

1

T328

1

T283

2

auto[1]

1693

1

T6

20

T7

11

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116

1

T24

1

T25

4

T328

1

auto[1]

1619

1

T3

20

T6

20

T7

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97

1

T25

4

T283

1

T286

2

auto[1]

1751

1

T2

20

T6

20

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130

1

T24

2

T25

3

T289

3

auto[1]

1640

1

T2

20

T6

20

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105

1

T24

1

T25

3

T283

1

auto[1]

1503

1

T2

20

T3

20

T6

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129

1

T24

1

T25

3

T286

2

auto[1]

1692

1

T2

20

T6

20

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124

1

T24

1

T283

1

T286

1

auto[1]

1506

1

T2

20

T6

20

T42

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181

1

T24

1

T25

15

T289

4

auto[1]

1503

1

T6

20

T7

11

T11

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

188

1

T24

1

T25

15

T335

41

auto[1]

1663

1

T3

20

T6

20

T7

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167

1

T24

1

T335

43

T283

2

auto[1]

1334

1

T3

20

T6

20

T7

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

190

1

T24

1

T25

15

T335

41

auto[1]

1512

1

T2

20

T6

20

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152

1

T24

1

T289

4

T336

1

auto[1]

1563

1

T3

20

T6

20

T42

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152

1

T24

1

T283

1

T286

3

auto[1]

1678

1

T7

11

T17

11

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157

1

T24

1

T336

1

T283

1

auto[1]

1627

1

T2

20

T6

20

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120

1

T24

1

T336

1

T283

2

auto[1]

1574

1

T3

20

T6

20

T11

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159

1

T24

2

T25

10

T289

3

auto[1]

456

1

T24

8

T25

69

T349

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200

1

T24

2

T25

16

T289

4

auto[1]

425

1

T24

8

T25

43

T349

9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216

1

T24

3

T289

1

T335

47

auto[1]

438

1

T24

7

T25

60

T349

28

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243

1

T24

4

T25

13

T289

3

auto[1]

401

1

T24

6

T25

62

T349

26

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143

1

T24

1

T289

4

T335

37

auto[1]

726

1

T7

11

T10

12

T261

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170

1

T24

2

T289

4

T335

45

auto[1]

776

1

T6

20

T17

11

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147

1

T24

2

T335

43

T336

1

auto[1]

568

1

T6

20

T7

11

T64

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167

1

T24

2

T335

41

T336

1

auto[1]

541

1

T6

20

T27

11

T83

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157

1

T24

1

T335

39

T336

1

auto[1]

661

1

T7

11

T42

12

T65

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117

1

T24

2

T283

2

T286

1

auto[1]

814

1

T7

11

T17

11

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140

1

T24

1

T289

3

T283

1

auto[1]

689

1

T6

20

T7

11

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101

1

T24

2

T283

2

T286

2

auto[1]

687

1

T42

12

T64

11

T27

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98

1

T283

1

T286

1

T298

1

auto[1]

619

1

T65

19

T262

14

T83

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105

1

T24

2

T283

1

T286

1

auto[1]

577

1

T10

12

T261

14

T262

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127

1

T24

1

T283

2

T286

2

auto[1]

559

1

T64

11

T65

19

T262

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152

1

T24

1

T335

41

T283

1

auto[1]

546

1

T7

11

T42

12

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173

1

T24

2

T335

40

T283

4

auto[1]

542

1

T6

20

T17

11

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

142

1

T24

3

T335

40

T283

4

auto[1]

673

1

T6

20

T7

11

T27

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T24

2

T335

38

T283

2

auto[1]

598

1

T65

19

T262

14

T144

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95

1

T25

2

T336

1

T283

3

auto[1]

616

1

T6

20

T7

11

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173

1

T25

2

T289

2

T283

3

auto[1]

698

1

T6

20

T7

11

T42

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141

1

T25

2

T286

2

T298

3

auto[1]

577

1

T6

20

T7

11

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120

1

T24

1

T25

2

T283

2

auto[1]

818

1

T6

20

T42

12

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T24

1

T25

2

T283

2

auto[1]

643

1

T42

12

T64

11

T65

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124

1

T24

1

T25

18

T283

5

auto[1]

1355

1

T2

20

T6

20

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122

1

T24

1

T25

18

T283

3

auto[1]

1199

1

T2

20

T8

20

T27

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139

1

T25

18

T283

1

T286

4

auto[1]

1377

1

T3

20

T17

11

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123

1

T24

1

T25

18

T283

5

auto[1]

1448

1

T7

11

T8

20

T11

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141

1

T24

1

T25

18

T283

1

auto[1]

1383

1

T2

20

T17

11

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112

1

T283

1

T286

3

T298

1

auto[1]

1243

1

T8

20

T64

11

T262

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134

1

T24

1

T289

2

T336

1

auto[1]

1563

1

T2

20

T3

20

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109

1

T24

1

T283

3

T286

1

auto[1]

1533

1

T17

11

T29

20

T81

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134

1

T328

1

T336

1

T283

1

auto[1]

1507

1

T3

20

T6

20

T7

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96

1

T24

1

T328

1

T283

1

auto[1]

1329

1

T2

20

T3

20

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103

1

T328

1

T283

3

T286

2

auto[1]

1572

1

T2

20

T17

11

T8

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130

1

T24

1

T289

1

T283

4

auto[1]

1548

1

T17

11

T8

20

T64

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111

1

T24

1

T283

3

T286

2

auto[1]

1355

1

T3

20

T42

12

T11

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105

1

T24

2

T328

1

T283

2

auto[1]

1553

1

T11

20

T64

11

T29

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141

1

T24

1

T25

11

T283

3

auto[1]

1400

1

T3

20

T6

20

T7

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100

1

T24

1

T283

2

T286

1

auto[1]

1574

1

T3

20

T42

12

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106

1

T24

1

T289

2

T283

1

auto[1]

1379

1

T17

11

T11

20

T64

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133

1

T24

1

T283

1

T298

1

auto[1]

1550

1

T8

20

T42

12

T10

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131

1

T24

1

T283

2

T286

2

auto[1]

1449

1

T2

20

T3

20

T17

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126

1

T24

1

T286

2

T391

1

auto[1]

1474

1

T2

20

T3

20

T6

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193

1

T24

2

T25

6

T289

2

auto[1]

553

1

T53

1

T175

1

T60

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136

1

T328

1

T283

2

T286

1

auto[1]

428

1

T21

11

T30

1

T38

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79

1

T283

1

T286

3

T298

1

auto[1]

323

1

T21

9

T9

1

T30

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132

1

T24

1

T289

3

T328

1

auto[1]

356

1

T21

7

T30

1

T38

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118

1

T24

1

T328

1

T283

1

auto[1]

235

1

T21

5

T9

1

T30

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114

1

T24

1

T283

2

T286

3

auto[1]

283

1

T21

3

T38

1

T32

3