Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_auto_block_debounce_ctl_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_auto_block_debounce_ctl_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_auto_block_debounce_ctl_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_auto_block_debounce_ctl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_block_debounce_ctl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00


Variables for Group Instance sysrst_ctrl_auto_block_debounce_ctl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_auto_block_enable 2 0 2 100.00 100 1 1 2
cp_debounce_timer 3 0 3 100.00 100 1 1 0


Summary for Variable cp_auto_block_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_auto_block_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 968 1 T21 2 T60 6 T23 16
auto[1] 1028 1 T16 14 T21 2 T60 4



Summary for Variable cp_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_debounce_timer

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max_range 1184 1 T16 8 T60 10 T292 6
mid_range 444 1 T16 4 T23 2 T38 8
min_range 368 1 T16 2 T21 4 T23 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%