Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T21,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T16,T21,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T21,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T21,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T16,T21,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T21,T38
0	1	Covered	T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T21,T38
0	1	Covered	T16,T38,T44
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T21,T38
1	-	Covered	T16,T38,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T21,T38
DetectSt	168	Covered	T16,T21,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T16,T21,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T21,T38
DebounceSt->IdleSt	163	Covered	T32,T111,T112
DetectSt->IdleSt	186	Covered	T70
DetectSt->StableSt	191	Covered	T16,T21,T38
IdleSt->DebounceSt	148	Covered	T16,T21,T38
StableSt->IdleSt	206	Covered	T16,T21,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T21,T38
0	1	Covered	T16,T21,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T21,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T21,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T21,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T111,T69,T113
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T21,T38
DetectSt	-	-	-	-	1	-	-	Covered	T70
DetectSt	-	-	-	-	0	1	-	Covered	T16,T21,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T21,T38
StableSt	-	-	-	-	-	-	0	Covered	T16,T21,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	296	0	0
CntIncr_A	9022276	321606	0	0
CntNoWrap_A	9022276	8367647	0	0
DetectStDropOut_A	9022276	1	0	0
DetectedOut_A	9022276	907	0	0
DetectedPulseOut_A	9022276	137	0	0
DisabledIdleSt_A	9022276	8039579	0	0
DisabledNoDetection_A	9022276	8041924	0	0
EnterDebounceSt_A	9022276	160	0	0
EnterDetectSt_A	9022276	138	0	0
EnterStableSt_A	9022276	137	0	0
PulseIsPulse_A	9022276	137	0	0
StayInStableSt	9022276	770	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	7227	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	136	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	296	0	0
T8	6469	0	0	0
T16	739	6	0	0
T17	7208	0	0	0
T21	7034	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T38	0	8	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	4	0	0
T47	0	4	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	321606	0	0
T8	6469	0	0	0
T16	739	190	0	0
T17	7208	0	0	0
T21	7034	16	0	0
T32	0	32	0	0
T33	0	86	0	0
T38	0	203	0	0
T44	0	49	0	0
T45	0	59	0	0
T46	0	99	0	0
T47	0	31	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	246	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367647	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1	0	0
T70	794	1	0	0
T94	22155	0	0	0
T95	707	0	0	0
T96	5301	0	0	0
T97	423	0	0	0
T98	7453	0	0	0
T99	426	0	0	0
T100	796	0	0	0
T101	522	0	0	0
T102	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	907	0	0
T8	6469	0	0	0
T16	739	20	0	0
T17	7208	0	0	0
T21	7034	2	0	0
T33	0	10	0	0
T38	0	20	0	0
T44	0	6	0	0
T45	0	4	0	0
T46	0	11	0	0
T47	0	16	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	18	0	0
T104	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	137	0	0
T8	6469	0	0	0
T16	739	3	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T33	0	1	0	0
T38	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	3	0	0
T104	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8039579	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8041924	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	160	0	0
T8	6469	0	0	0
T16	739	3	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	138	0	0
T8	6469	0	0	0
T16	739	3	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T33	0	1	0	0
T38	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	3	0	0
T104	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	137	0	0
T8	6469	0	0	0
T16	739	3	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T33	0	1	0	0
T38	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	3	0	0
T104	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	137	0	0
T8	6469	0	0	0
T16	739	3	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T33	0	1	0	0
T38	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	3	0	0
T104	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	770	0	0
T8	6469	0	0	0
T16	739	17	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T33	0	9	0	0
T38	0	16	0	0
T44	0	5	0	0
T45	0	3	0	0
T46	0	9	0	0
T47	0	14	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	15	0	0
T104	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7227	0	0
T1	916	4	0	0
T2	8651	11	0	0
T3	8682	11	0	0
T4	35375	12	0	0
T5	502	5	0	0
T6	25051	29	0	0
T7	9559	30	0	0
T13	522	3	0	0
T14	495	7	0	0
T15	2649	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	136	0	0
T8	6469	0	0	0
T16	739	3	0	0
T17	7208	0	0	0
T21	7034	0	0	0
T33	0	1	0	0
T38	0	4	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T79	0	3	0	0
T104	0	1	0	0
T106	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T22,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T26
0	1	Covered	T75,T76,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T26
0	1	Unreachable
1	0	Covered	T1,T22,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T21,T22
DetectSt	168	Covered	T1,T22,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T22,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T22,T26
DebounceSt->IdleSt	163	Covered	T21,T55,T32
DetectSt->IdleSt	186	Covered	T75,T76,T77
DetectSt->StableSt	191	Covered	T1,T22,T26
IdleSt->DebounceSt	148	Covered	T1,T21,T22
StableSt->IdleSt	206	Covered	T1,T22,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T21,T22
0	1	Covered	T1,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T22,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T75,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T75,T76,T77
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T26
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	170	0	0
CntIncr_A	9022276	662641	0	0
CntNoWrap_A	9022276	8367773	0	0
DetectStDropOut_A	9022276	15	0	0
DetectedOut_A	9022276	117833	0	0
DetectedPulseOut_A	9022276	44	0	0
DisabledIdleSt_A	9022276	5670667	0	0
DisabledNoDetection_A	9022276	5673066	0	0
EnterDebounceSt_A	9022276	112	0	0
EnterDetectSt_A	9022276	59	0	0
EnterStableSt_A	9022276	44	0	0
PulseIsPulse_A	9022276	44	0	0
StayInStableSt	9022276	117789	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	7227	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_sticky_sva.StableStDropOut_A	9022276	1329387	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	170	0	0
T1	916	2	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	0	4	0	0
T32	0	2	0	0
T38	0	2	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	2	0	0
T66	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	662641	0	0
T1	916	21	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	26	0	0
T22	0	83	0	0
T26	0	64	0	0
T32	0	39	0	0
T38	0	40	0	0
T54	0	25	0	0
T55	0	392	0	0
T56	0	54	0	0
T66	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367773	0	0
T1	916	513	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	15	0	0
T73	561	0	0	0
T75	8177	2	0	0
T76	0	2	0	0
T77	0	4	0	0
T109	1736	0	0	0
T114	0	2	0	0
T115	0	4	0	0
T116	0	1	0	0
T117	403	0	0	0
T118	23077	0	0	0
T119	522	0	0	0
T120	31351	0	0	0
T121	300352	0	0	0
T122	686	0	0	0
T123	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	117833	0	0
T1	916	62	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	295	0	0
T26	0	124	0	0
T38	0	8	0	0
T54	0	49	0	0
T56	0	71	0	0
T66	0	421	0	0
T78	0	3	0	0
T107	0	188	0	0
T108	0	619	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	5670667	0	0
T1	916	148	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	5673066	0	0
T1	916	149	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	112	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T26	0	2	0	0
T32	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	4	0	0
T56	0	1	0	0
T66	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	59	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	117789	0	0
T1	916	61	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	294	0	0
T26	0	122	0	0
T38	0	7	0	0
T54	0	48	0	0
T56	0	70	0	0
T66	0	420	0	0
T78	0	2	0	0
T107	0	187	0	0
T108	0	617	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7227	0	0
T1	916	4	0	0
T2	8651	11	0	0
T3	8682	11	0	0
T4	35375	12	0	0
T5	502	5	0	0
T6	25051	29	0	0
T7	9559	30	0	0
T13	522	3	0	0
T14	495	7	0	0
T15	2649	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1329387	0	0
T1	916	263	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	56	0	0
T26	0	392801	0	0
T38	0	70	0	0
T54	0	258	0	0
T56	0	146	0	0
T66	0	98512	0	0
T78	0	58	0	0
T107	0	121	0	0
T108	0	424	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T22,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T26
0	1	Covered	T1,T72,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T26
0	1	Unreachable
1	0	Covered	T1,T22,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T21,T22
DetectSt	168	Covered	T1,T22,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T22,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T22,T26
DebounceSt->IdleSt	163	Covered	T1,T21,T54
DetectSt->IdleSt	186	Covered	T1,T72,T74
DetectSt->StableSt	191	Covered	T1,T22,T26
IdleSt->DebounceSt	148	Covered	T1,T21,T22
StableSt->IdleSt	206	Covered	T1,T22,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T21,T22
0	1	Covered	T1,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T22,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T54,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T1,T72,T74
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T26
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	154	0	0
CntIncr_A	9022276	533700	0	0
CntNoWrap_A	9022276	8367789	0	0
DetectStDropOut_A	9022276	10	0	0
DetectedOut_A	9022276	659308	0	0
DetectedPulseOut_A	9022276	43	0	0
DisabledIdleSt_A	9022276	5670667	0	0
DisabledNoDetection_A	9022276	5673066	0	0
EnterDebounceSt_A	9022276	102	0	0
EnterDetectSt_A	9022276	53	0	0
EnterStableSt_A	9022276	43	0	0
PulseIsPulse_A	9022276	43	0	0
StayInStableSt	9022276	659265	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_sticky_sva.StableStDropOut_A	9022276	1074764	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	154	0	0
T1	916	5	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	0	4	0	0
T32	0	2	0	0
T38	0	1	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	2	0	0
T66	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	533700	0	0
T1	916	270	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	27	0	0
T22	0	51	0	0
T26	0	84	0	0
T32	0	39	0	0
T38	0	17	0	0
T54	0	120	0	0
T55	0	60920	0	0
T56	0	72	0	0
T66	0	450	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367789	0	0
T1	916	510	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	10	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T72	0	1	0	0
T74	0	5	0	0
T124	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	659308	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	147	0	0
T26	0	182	0	0
T55	0	112756	0	0
T56	0	153	0	0
T75	0	213	0	0
T76	0	114	0	0
T108	0	257	0	0
T109	0	150	0	0
T110	0	23	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	43	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	5670667	0	0
T1	916	148	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	5673066	0	0
T1	916	149	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	102	0	0
T1	916	3	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T26	0	2	0	0
T32	0	2	0	0
T38	0	1	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T66	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	53	0	0
T1	916	2	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	43	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	43	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	659265	0	0
T22	1328	146	0	0
T26	393479	180	0	0
T29	36782	0	0	0
T55	0	112754	0	0
T56	0	152	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T75	0	212	0	0
T76	0	113	0	0
T108	0	255	0	0
T109	0	149	0	0
T110	0	22	0	0
T125	0	1171	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T129	405	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1074764	0	0
T1	916	24	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	246	0	0
T26	0	392721	0	0
T55	0	403	0	0
T56	0	49	0	0
T75	0	225	0	0
T76	0	101	0	0
T108	0	859	0	0
T109	0	475	0	0
T110	0	186	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T22,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T26
0	1	Covered	T22,T66,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T26
0	1	Unreachable
1	0	Covered	T1,T22,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T21,T22
DetectSt	168	Covered	T1,T22,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T22,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T22,T26
DebounceSt->IdleSt	163	Covered	T21,T32,T78
DetectSt->IdleSt	186	Covered	T22,T66,T72
DetectSt->StableSt	191	Covered	T1,T22,T26
IdleSt->DebounceSt	148	Covered	T1,T21,T22
StableSt->IdleSt	206	Covered	T1,T22,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T21,T22
0	1	Covered	T1,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T22,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T108,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T66,T72
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T26
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	145	0	0
CntIncr_A	9022276	214326	0	0
CntNoWrap_A	9022276	8367798	0	0
DetectStDropOut_A	9022276	8	0	0
DetectedOut_A	9022276	525217	0	0
DetectedPulseOut_A	9022276	42	0	0
DisabledIdleSt_A	9022276	5670667	0	0
DisabledNoDetection_A	9022276	5673066	0	0
EnterDebounceSt_A	9022276	96	0	0
EnterDetectSt_A	9022276	50	0	0
EnterStableSt_A	9022276	42	0	0
PulseIsPulse_A	9022276	42	0	0
StayInStableSt	9022276	525175	0	0
gen_high_event_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_sticky_sva.StableStDropOut_A	9022276	1353957	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	145	0	0
T1	916	2	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T26	0	4	0	0
T32	0	2	0	0
T38	0	2	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	2	0	0
T66	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	214326	0	0
T1	916	17	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	26	0	0
T22	0	44	0	0
T26	0	122848	0	0
T32	0	43	0	0
T38	0	53	0	0
T54	0	85	0	0
T55	0	106	0	0
T56	0	71	0	0
T66	0	39422	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367798	0	0
T1	916	513	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8	0	0
T22	1328	1	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T66	0	1	0	0
T72	0	1	0	0
T74	0	4	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T129	405	0	0	0
T130	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	525217	0	0
T1	916	76	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	23	0	0
T26	0	270087	0	0
T38	0	52	0	0
T54	0	126	0	0
T55	0	261	0	0
T56	0	171	0	0
T66	0	59137	0	0
T75	0	398	0	0
T107	0	152	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	42	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T66	0	1	0	0
T75	0	1	0	0
T107	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	5670667	0	0
T1	916	148	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	5673066	0	0
T1	916	149	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	96	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T26	0	2	0	0
T32	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T66	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	50	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	2	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T66	0	2	0	0
T75	0	1	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	42	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T66	0	1	0	0
T75	0	1	0	0
T107	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	42	0	0
T1	916	1	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	1	0	0
T26	0	2	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T66	0	1	0	0
T75	0	1	0	0
T107	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	525175	0	0
T1	916	75	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	22	0	0
T26	0	270085	0	0
T38	0	51	0	0
T54	0	125	0	0
T55	0	259	0	0
T56	0	170	0	0
T66	0	59136	0	0
T75	0	397	0	0
T107	0	151	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1353957	0	0
T1	916	267	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T22	0	258	0	0
T26	0	71	0	0
T38	0	26	0	0
T54	0	128	0	0
T55	0	173732	0	0
T56	0	47	0	0
T66	0	360	0	0
T75	0	42	0	0
T107	0	190	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T38,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T38,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T34,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T12,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T38,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T34,T32
0	1	Covered	T39,T131
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T34,T32
0	1	Covered	T34,T33,T75
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T34,T32
1	-	Covered	T34,T33,T75

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T38,T34
DetectSt	168	Covered	T38,T34,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T38,T34,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T34,T32
DebounceSt->IdleSt	163	Covered	T21,T132,T133
DetectSt->IdleSt	186	Covered	T39,T131
DetectSt->StableSt	191	Covered	T38,T34,T32
IdleSt->DebounceSt	148	Covered	T21,T38,T34
StableSt->IdleSt	206	Covered	T38,T34,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T38,T34
0	1	Covered	T21,T38,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T34,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T38,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T34,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T132,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T38,T34
DetectSt	-	-	-	-	1	-	-	Covered	T39,T131
DetectSt	-	-	-	-	0	1	-	Covered	T38,T34,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T38,T34,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	69	0	0
CntIncr_A	9022276	1633	0	0
CntNoWrap_A	9022276	8367874	0	0
DetectStDropOut_A	9022276	2	0	0
DetectedOut_A	9022276	2928	0	0
DetectedPulseOut_A	9022276	31	0	0
DisabledIdleSt_A	9022276	8263117	0	0
DisabledNoDetection_A	9022276	8265473	0	0
EnterDebounceSt_A	9022276	36	0	0
EnterDetectSt_A	9022276	33	0	0
EnterStableSt_A	9022276	31	0	0
PulseIsPulse_A	9022276	31	0	0
StayInStableSt	9022276	2881	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	69	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	0	4	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	4	0	0
T120	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1633	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	27	0	0
T32	0	29	0	0
T33	0	100	0	0
T34	0	22	0	0
T38	0	29	0	0
T39	0	74	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	56	0	0
T120	0	83	0	0
T134	0	46	0	0
T135	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367874	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2	0	0
T36	1663	0	0	0
T39	775	1	0	0
T40	939	0	0	0
T47	650	0	0	0
T66	148860	0	0	0
T131	0	1	0	0
T136	502	0	0	0
T137	522	0	0	0
T138	405	0	0	0
T139	522	0	0	0
T140	716	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2928	0	0
T32	0	10	0	0
T33	0	85	0	0
T34	0	63	0	0
T35	502	0	0	0
T38	18515	39	0	0
T39	0	78	0	0
T59	492	0	0	0
T75	0	118	0	0
T105	27357	0	0	0
T120	0	45	0	0
T134	0	40	0	0
T135	0	48	0	0
T141	0	39	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	31	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	502	0	0	0
T38	18515	1	0	0
T39	0	1	0	0
T59	492	0	0	0
T75	0	2	0	0
T105	27357	0	0	0
T120	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8263117	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8265473	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	36	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	2	0	0
T120	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	33	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	502	0	0	0
T38	18515	1	0	0
T39	0	2	0	0
T59	492	0	0	0
T75	0	2	0	0
T105	27357	0	0	0
T120	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	31	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	502	0	0	0
T38	18515	1	0	0
T39	0	1	0	0
T59	492	0	0	0
T75	0	2	0	0
T105	27357	0	0	0
T120	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	31	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	502	0	0	0
T38	18515	1	0	0
T39	0	1	0	0
T59	492	0	0	0
T75	0	2	0	0
T105	27357	0	0	0
T120	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2881	0	0
T32	0	9	0	0
T33	0	82	0	0
T34	0	62	0	0
T35	502	0	0	0
T38	18515	37	0	0
T39	0	76	0	0
T59	492	0	0	0
T75	0	115	0	0
T105	27357	0	0	0
T120	0	43	0	0
T134	0	38	0	0
T135	0	46	0	0
T141	0	37	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	14	0	0
T31	706	0	0	0
T33	0	1	0	0
T34	674	1	0	0
T56	1412	0	0	0
T75	0	1	0	0
T82	5016	0	0	0
T125	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T38,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T38,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T32,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T38,T32
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T38,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T32,T40
0	1	Covered	T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T32,T40
0	1	Covered	T38,T37,T161
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T32,T40
1	-	Covered	T38,T37,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T38,T32
DetectSt	168	Covered	T38,T32,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T38,T32,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T32,T40
DebounceSt->IdleSt	163	Covered	T21,T141,T153
DetectSt->IdleSt	186	Covered	T160
DetectSt->StableSt	191	Covered	T38,T32,T40
IdleSt->DebounceSt	148	Covered	T21,T38,T32
StableSt->IdleSt	206	Covered	T38,T32,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T38,T32
0	1	Covered	T21,T38,T32
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T32,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T38,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T32,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T153
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T38,T32
DetectSt	-	-	-	-	1	-	-	Covered	T160
DetectSt	-	-	-	-	0	1	-	Covered	T38,T32,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T32,T37
StableSt	-	-	-	-	-	-	0	Covered	T38,T32,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	121	0	0
CntIncr_A	9022276	72343	0	0
CntNoWrap_A	9022276	8367822	0	0
DetectStDropOut_A	9022276	1	0	0
DetectedOut_A	9022276	68826	0	0
DetectedPulseOut_A	9022276	58	0	0
DisabledIdleSt_A	9022276	8083268	0	0
DisabledNoDetection_A	9022276	8085623	0	0
EnterDebounceSt_A	9022276	62	0	0
EnterDetectSt_A	9022276	59	0	0
EnterStableSt_A	9022276	58	0	0
PulseIsPulse_A	9022276	58	0	0
StayInStableSt	9022276	68744	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	2696	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	121	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T134	0	2	0	0
T135	0	2	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	72343	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	26	0	0
T32	0	29	0	0
T37	0	55	0	0
T38	0	29	0	0
T40	0	80	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T134	0	46	0	0
T135	0	11	0	0
T161	0	225	0	0
T162	0	44846	0	0
T163	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367822	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1	0	0
T93	6597	0	0	0
T160	12801	1	0	0
T164	713	0	0	0
T165	671	0	0	0
T166	738	0	0	0
T167	800	0	0	0
T168	19861	0	0	0
T169	8247	0	0	0
T170	524	0	0	0
T171	510	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	68826	0	0
T32	0	10	0	0
T35	502	0	0	0
T37	0	22	0	0
T38	18515	91	0	0
T40	0	61	0	0
T59	492	0	0	0
T105	27357	0	0	0
T134	0	28	0	0
T135	0	61	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	310	0	0
T161	0	90	0	0
T162	0	44891	0	0
T163	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	58	0	0
T32	0	1	0	0
T35	502	0	0	0
T37	0	1	0	0
T38	18515	1	0	0
T40	0	1	0	0
T59	492	0	0	0
T105	27357	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	3	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8083268	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8085623	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	62	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	59	0	0
T32	0	1	0	0
T35	502	0	0	0
T37	0	1	0	0
T38	18515	1	0	0
T40	0	1	0	0
T59	492	0	0	0
T105	27357	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	3	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	58	0	0
T32	0	1	0	0
T35	502	0	0	0
T37	0	1	0	0
T38	18515	1	0	0
T40	0	1	0	0
T59	492	0	0	0
T105	27357	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	3	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	58	0	0
T32	0	1	0	0
T35	502	0	0	0
T37	0	1	0	0
T38	18515	1	0	0
T40	0	1	0	0
T59	492	0	0	0
T105	27357	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	3	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	68744	0	0
T32	0	9	0	0
T35	502	0	0	0
T37	0	21	0	0
T38	18515	90	0	0
T40	0	59	0	0
T59	492	0	0	0
T105	27357	0	0	0
T134	0	27	0	0
T135	0	60	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	306	0	0
T161	0	86	0	0
T162	0	44889	0	0
T163	0	106	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2696	0	0
T1	916	0	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T4	35375	5	0	0
T5	502	5	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	7	0	0
T14	495	5	0	0
T15	2649	10	0	0
T21	0	3	0	0
T48	0	4	0	0
T50	0	1	0	0
T51	0	9	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	33	0	0
T35	502	0	0	0
T37	0	1	0	0
T38	18515	1	0	0
T59	492	0	0	0
T69	0	1	0	0
T105	27357	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T161	0	2	0	0
T163	0	2	0	0