Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T9,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T9,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T30
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T9,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T30,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T30,T31
0	1	Covered	T30,T31,T39
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T30,T31
1	-	Covered	T30,T31,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T9,T30
DetectSt	168	Covered	T9,T30,T31
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T30,T31
DebounceSt->IdleSt	163	Covered	T21
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T30,T31
IdleSt->DebounceSt	148	Covered	T21,T9,T30
StableSt->IdleSt	206	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T9,T30
0	1	Covered	T21,T9,T30
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T30,T31
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T9,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T30,T31
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T9,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T9,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	93	0	0
CntIncr_A	9022276	44998	0	0
CntNoWrap_A	9022276	8367850	0	0
DetectStDropOut_A	9022276	0	0	0
DetectedOut_A	9022276	13493	0	0
DetectedPulseOut_A	9022276	46	0	0
DisabledIdleSt_A	9022276	8080595	0	0
DisabledNoDetection_A	9022276	8082945	0	0
EnterDebounceSt_A	9022276	47	0	0
EnterDetectSt_A	9022276	46	0	0
EnterStableSt_A	9022276	46	0	0
PulseIsPulse_A	9022276	46	0	0
StayInStableSt	9022276	13420	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	93	0	0
T8	6469	0	0	0
T9	482	2	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T39	0	4	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T73	0	2	0	0
T75	0	4	0	0
T172	0	2	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44998	0	0
T8	6469	0	0	0
T9	482	14	0	0
T21	7034	27	0	0
T30	0	42848	0	0
T31	0	23	0	0
T32	0	29	0	0
T39	0	74	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T73	0	16	0	0
T75	0	40	0	0
T172	0	56	0	0
T173	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367850	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	13493	0	0
T9	482	39	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	11018	0	0
T31	0	119	0	0
T32	0	9	0	0
T39	0	121	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T69	0	41	0	0
T73	0	43	0	0
T75	0	187	0	0
T172	0	41	0	0
T173	0	88	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T75	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8080595	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8082945	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	47	0	0
T8	6469	0	0	0
T9	482	1	0	0
T21	7034	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T39	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T73	0	1	0	0
T75	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T75	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T75	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T75	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	13420	0	0
T9	482	37	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	11017	0	0
T31	0	118	0	0
T32	0	8	0	0
T39	0	118	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T69	0	39	0	0
T73	0	42	0	0
T75	0	183	0	0
T172	0	39	0	0
T173	0	85	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	18	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T39	0	1	0	0
T73	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T30,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T30,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T30,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T30,T38
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T30,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T69,T160,T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T30,T31,T39
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T32
1	-	Covered	T30,T31,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T30,T38
DetectSt	168	Covered	T30,T31,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T30,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T32
DebounceSt->IdleSt	163	Covered	T21,T38,T173
DetectSt->IdleSt	186	Covered	T69,T160,T189
DetectSt->StableSt	191	Covered	T30,T31,T32
IdleSt->DebounceSt	148	Covered	T21,T30,T38
StableSt->IdleSt	206	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T30,T38
0	1	Covered	T21,T30,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T30,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T173,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T30,T38
DetectSt	-	-	-	-	1	-	-	Covered	T69,T160,T189
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	147	0	0
CntIncr_A	9022276	162047	0	0
CntNoWrap_A	9022276	8367796	0	0
DetectStDropOut_A	9022276	3	0	0
DetectedOut_A	9022276	66889	0	0
DetectedPulseOut_A	9022276	68	0	0
DisabledIdleSt_A	9022276	7988054	0	0
DisabledNoDetection_A	9022276	7990400	0	0
EnterDebounceSt_A	9022276	76	0	0
EnterDetectSt_A	9022276	71	0	0
EnterStableSt_A	9022276	68	0	0
PulseIsPulse_A	9022276	68	0	0
StayInStableSt	9022276	66796	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	3067	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	147	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	4	0	0
T31	0	4	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	4	0	0
T41	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T172	0	2	0	0
T173	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	162047	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	25	0	0
T30	0	85696	0	0
T31	0	46	0	0
T32	0	29	0	0
T37	0	55	0	0
T38	0	29	0	0
T39	0	74	0	0
T41	0	100	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T172	0	56	0	0
T173	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367796	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	3	0	0
T69	3015	1	0	0
T150	2165	0	0	0
T160	0	1	0	0
T189	0	1	0	0
T190	426	0	0	0
T191	429	0	0	0
T192	718	0	0	0
T193	9392	0	0	0
T194	447	0	0	0
T195	522	0	0	0
T196	705	0	0	0
T197	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	66889	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	42933	0	0
T31	0	83	0	0
T32	0	9	0	0
T37	0	120	0	0
T39	0	93	0	0
T41	0	42	0	0
T73	0	58	0	0
T75	0	114	0	0
T172	0	13	0	0
T173	0	36	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	68	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7988054	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7990400	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	76	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T172	0	1	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	71	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	68	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	68	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	66796	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	42930	0	0
T31	0	80	0	0
T32	0	8	0	0
T37	0	119	0	0
T39	0	91	0	0
T41	0	40	0	0
T73	0	55	0	0
T75	0	113	0	0
T172	0	12	0	0
T173	0	35	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	3067	0	0
T1	916	0	0	0
T2	8651	0	0	0
T3	8682	0	0	0
T4	35375	5	0	0
T5	502	5	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	6	0	0
T14	495	3	0	0
T15	2649	13	0	0
T21	0	7	0	0
T48	0	4	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	12	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	42	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T148	0	3	0	0
T149	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T9,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T9,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T30,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T30
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T9,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T30,T38
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T30,T38
0	1	Covered	T30,T38,T31
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T30,T38
1	-	Covered	T30,T38,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T9,T30
DetectSt	168	Covered	T9,T30,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T30,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T30,T38
DebounceSt->IdleSt	163	Covered	T21,T198,T199
DetectSt->IdleSt	186	Covered	T189
DetectSt->StableSt	191	Covered	T9,T30,T38
IdleSt->DebounceSt	148	Covered	T21,T9,T30
StableSt->IdleSt	206	Covered	T30,T38,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T9,T30
0	1	Covered	T21,T9,T30
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T30,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T9,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T30,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T198,T199,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T9,T30
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T9,T30,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T38,T31
StableSt	-	-	-	-	-	-	0	Covered	T9,T30,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	134	0	0
CntIncr_A	9022276	70833	0	0
CntNoWrap_A	9022276	8367809	0	0
DetectStDropOut_A	9022276	1	0	0
DetectedOut_A	9022276	15928	0	0
DetectedPulseOut_A	9022276	64	0	0
DisabledIdleSt_A	9022276	7991412	0	0
DisabledNoDetection_A	9022276	7993764	0	0
EnterDebounceSt_A	9022276	69	0	0
EnterDetectSt_A	9022276	65	0	0
EnterStableSt_A	9022276	64	0	0
PulseIsPulse_A	9022276	64	0	0
StayInStableSt	9022276	15832	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	134	0	0
T8	6469	0	0	0
T9	482	2	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T36	0	4	0	0
T38	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T134	0	2	0	0
T163	0	4	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	70833	0	0
T8	6469	0	0	0
T9	482	14	0	0
T21	7034	26	0	0
T30	0	42848	0	0
T31	0	23	0	0
T32	0	29	0	0
T36	0	143	0	0
T38	0	29	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T134	0	46	0	0
T163	0	30	0	0
T173	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367809	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1	0	0
T189	6120	1	0	0
T201	797	0	0	0
T202	427	0	0	0
T203	523	0	0	0
T204	1106	0	0	0
T205	11997	0	0	0
T206	19874	0	0	0
T207	14595	0	0	0
T208	91046	0	0	0
T209	65585	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	15928	0	0
T9	482	38	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	11019	0	0
T31	0	119	0	0
T32	0	9	0	0
T36	0	239	0	0
T38	0	107	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	6	0	0
T134	0	115	0	0
T163	0	13	0	0
T173	0	100	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	64	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T134	0	1	0	0
T163	0	2	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7991412	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7993764	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	69	0	0
T8	6469	0	0	0
T9	482	1	0	0
T21	7034	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T134	0	1	0	0
T163	0	2	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	65	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T134	0	1	0	0
T163	0	2	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	64	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T134	0	1	0	0
T163	0	2	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	64	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T134	0	1	0	0
T163	0	2	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	15832	0	0
T9	482	36	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T30	0	11018	0	0
T31	0	118	0	0
T32	0	8	0	0
T36	0	235	0	0
T38	0	106	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	5	0	0
T134	0	113	0	0
T163	0	11	0	0
T173	0	98	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	31	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T125	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T163	0	2	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0
T210	0	1	0	0
T211	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T30,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T30,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T30,T38,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T30,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T30,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T38,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T38,T34
0	1	Covered	T34,T33,T37
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T38,T34
1	-	Covered	T34,T33,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T30,T38
DetectSt	168	Covered	T30,T38,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T30,T38,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T38,T34
DebounceSt->IdleSt	163	Covered	T21,T181
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T30,T38,T34
IdleSt->DebounceSt	148	Covered	T21,T30,T38
StableSt->IdleSt	206	Covered	T38,T34,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T30,T38
0	1	Covered	T21,T30,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T38,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T30,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T38,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T181
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T30,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T30,T38,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T30,T38,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	70	0	0
CntIncr_A	9022276	44494	0	0
CntNoWrap_A	9022276	8367873	0	0
DetectStDropOut_A	9022276	0	0	0
DetectedOut_A	9022276	2988	0	0
DetectedPulseOut_A	9022276	34	0	0
DisabledIdleSt_A	9022276	7901483	0	0
DisabledNoDetection_A	9022276	7903831	0	0
EnterDebounceSt_A	9022276	36	0	0
EnterDetectSt_A	9022276	34	0	0
EnterStableSt_A	9022276	34	0	0
PulseIsPulse_A	9022276	34	0	0
StayInStableSt	9022276	2936	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	6755	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	70	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44494	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	26	0	0
T30	0	42848	0	0
T31	0	23	0	0
T32	0	29	0	0
T33	0	50	0	0
T34	0	22	0	0
T37	0	55	0	0
T38	0	29	0	0
T39	0	37	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T172	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367873	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2988	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	41	0	0
T31	0	40	0	0
T32	0	10	0	0
T33	0	181	0	0
T34	0	91	0	0
T37	0	20	0	0
T38	0	40	0	0
T39	0	159	0	0
T163	0	84	0	0
T172	0	111	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	34	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7901483	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7903831	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	36	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	34	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	34	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	34	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2936	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	39	0	0
T31	0	38	0	0
T32	0	9	0	0
T33	0	180	0	0
T34	0	90	0	0
T37	0	19	0	0
T38	0	38	0	0
T39	0	157	0	0
T163	0	81	0	0
T172	0	109	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	6755	0	0
T1	916	4	0	0
T2	8651	12	0	0
T3	8682	12	0	0
T4	35375	10	0	0
T5	502	4	0	0
T6	25051	33	0	0
T7	9559	26	0	0
T13	522	5	0	0
T14	495	5	0	0
T15	2649	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	15	0	0
T31	706	0	0	0
T33	0	1	0	0
T34	674	1	0	0
T37	0	1	0	0
T56	1412	0	0	0
T82	5016	0	0	0
T135	0	1	0	0
T150	0	2	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T163	0	1	0	0
T181	0	1	0	0
T198	0	1	0	0
T212	0	1	0	0
T213	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T35,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T35,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T31,T32,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T35
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T35,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T39
0	1	Covered	T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T39
0	1	Covered	T31,T39,T84
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T39
1	-	Covered	T31,T39,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T35,T31
DetectSt	168	Covered	T31,T32,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T31,T32,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T39
DebounceSt->IdleSt	163	Covered	T21,T35,T36
DetectSt->IdleSt	186	Covered	T73
DetectSt->StableSt	191	Covered	T31,T32,T39
IdleSt->DebounceSt	148	Covered	T21,T35,T31
StableSt->IdleSt	206	Covered	T31,T32,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T35,T31
0	1	Covered	T21,T35,T31
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T35,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T36,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T35,T31
DetectSt	-	-	-	-	1	-	-	Covered	T73
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T39
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	119	0	0
CntIncr_A	9022276	51314	0	0
CntNoWrap_A	9022276	8367824	0	0
DetectStDropOut_A	9022276	1	0	0
DetectedOut_A	9022276	43555	0	0
DetectedPulseOut_A	9022276	55	0	0
DisabledIdleSt_A	9022276	8174706	0	0
DisabledNoDetection_A	9022276	8177057	0	0
EnterDebounceSt_A	9022276	63	0	0
EnterDetectSt_A	9022276	56	0	0
EnterStableSt_A	9022276	55	0	0
PulseIsPulse_A	9022276	55	0	0
StayInStableSt	9022276	43476	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	119	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T31	0	4	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	4	0	0
T41	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	2	0	0
T161	0	4	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	51314	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	26	0	0
T31	0	46	0	0
T32	0	29	0	0
T35	0	26	0	0
T36	0	143	0	0
T39	0	74	0	0
T41	0	100	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	51	0	0
T161	0	150	0	0
T172	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367824	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1	0	0
T72	2290	0	0	0
T73	561	1	0	0
T109	1736	0	0	0
T119	522	0	0	0
T120	31351	0	0	0
T121	300352	0	0	0
T122	686	0	0	0
T123	524	0	0	0
T214	5219	0	0	0
T215	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	43555	0	0
T31	706	191	0	0
T32	0	9	0	0
T36	0	202	0	0
T39	0	250	0	0
T41	0	41	0	0
T56	1412	0	0	0
T84	0	239	0	0
T134	0	28	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	236	0	0
T163	0	171	0	0
T172	0	124	0	0
T216	524	0	0	0
T217	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	55	0	0
T31	706	2	0	0
T32	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T56	1412	0	0	0
T84	0	1	0	0
T134	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	2	0	0
T216	524	0	0	0
T217	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8174706	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8177057	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	63	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	1	0	0
T161	0	2	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	56	0	0
T31	706	2	0	0
T32	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T56	1412	0	0	0
T84	0	1	0	0
T134	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	2	0	0
T216	524	0	0	0
T217	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	55	0	0
T31	706	2	0	0
T32	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T56	1412	0	0	0
T84	0	1	0	0
T134	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	2	0	0
T216	524	0	0	0
T217	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	55	0	0
T31	706	2	0	0
T32	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T56	1412	0	0	0
T84	0	1	0	0
T134	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	2	0	0
T216	524	0	0	0
T217	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	43476	0	0
T31	706	188	0	0
T32	0	8	0	0
T36	0	200	0	0
T39	0	247	0	0
T41	0	39	0	0
T56	1412	0	0	0
T84	0	238	0	0
T134	0	27	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	233	0	0
T163	0	168	0	0
T172	0	121	0	0
T216	524	0	0	0
T217	421	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	30	0	0
T31	706	1	0	0
T39	0	1	0	0
T56	1412	0	0	0
T75	0	2	0	0
T84	0	1	0	0
T120	0	1	0	0
T134	0	1	0	0
T148	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	1	0	0
T163	0	1	0	0
T172	0	1	0	0
T216	524	0	0	0
T217	421	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T34,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T34,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T34,T32,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T34,T32
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T34,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T32,T36
0	1	Covered	T179,T218
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T32,T36
0	1	Covered	T34,T172,T125
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T32,T36
1	-	Covered	T34,T172,T125

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T34,T32
DetectSt	168	Covered	T34,T32,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T34,T32,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T32,T36
DebounceSt->IdleSt	163	Covered	T21,T219,T181
DetectSt->IdleSt	186	Covered	T179,T218
DetectSt->StableSt	191	Covered	T34,T32,T36
IdleSt->DebounceSt	148	Covered	T21,T34,T32
StableSt->IdleSt	206	Covered	T34,T32,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T34,T32
0	1	Covered	T21,T34,T32
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T32,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T34,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T32,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T219,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T34,T32
DetectSt	-	-	-	-	1	-	-	Covered	T179,T218
DetectSt	-	-	-	-	0	1	-	Covered	T34,T32,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T32,T172
StableSt	-	-	-	-	-	-	0	Covered	T34,T32,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	77	0	0
CntIncr_A	9022276	95210	0	0
CntNoWrap_A	9022276	8367866	0	0
DetectStDropOut_A	9022276	2	0	0
DetectedOut_A	9022276	2704	0	0
DetectedPulseOut_A	9022276	35	0	0
DisabledIdleSt_A	9022276	8083565	0	0
DisabledNoDetection_A	9022276	8085920	0	0
EnterDebounceSt_A	9022276	40	0	0
EnterDetectSt_A	9022276	37	0	0
EnterStableSt_A	9022276	35	0	0
PulseIsPulse_A	9022276	35	0	0
StayInStableSt	9022276	2649	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	6362	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	77	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	2	0	0
T34	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	2	0	0
T84	0	2	0	0
T162	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	95210	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	26	0	0
T32	0	29	0	0
T34	0	44	0	0
T36	0	60	0	0
T37	0	55	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	12	0	0
T84	0	51	0	0
T162	0	44846	0	0
T172	0	56	0	0
T173	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367866	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2	0	0
T179	692	1	0	0
T218	0	1	0	0
T219	2572	0	0	0
T220	505	0	0	0
T221	522	0	0	0
T222	442	0	0	0
T223	5518	0	0	0
T224	21721	0	0	0
T225	636	0	0	0
T226	21993	0	0	0
T227	820	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2704	0	0
T31	706	0	0	0
T32	0	11	0	0
T34	674	44	0	0
T36	0	39	0	0
T37	0	123	0	0
T56	1412	0	0	0
T75	0	71	0	0
T82	5016	0	0	0
T84	0	125	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T162	0	44	0	0
T172	0	43	0	0
T173	0	99	0	0
T228	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	35	0	0
T31	706	0	0	0
T32	0	1	0	0
T34	674	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T56	1412	0	0	0
T75	0	1	0	0
T82	5016	0	0	0
T84	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T162	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T228	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8083565	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8085920	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	40	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T162	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	37	0	0
T31	706	0	0	0
T32	0	1	0	0
T34	674	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T56	1412	0	0	0
T75	0	1	0	0
T82	5016	0	0	0
T84	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T162	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T228	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	35	0	0
T31	706	0	0	0
T32	0	1	0	0
T34	674	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T56	1412	0	0	0
T75	0	1	0	0
T82	5016	0	0	0
T84	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T162	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T228	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	35	0	0
T31	706	0	0	0
T32	0	1	0	0
T34	674	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T56	1412	0	0	0
T75	0	1	0	0
T82	5016	0	0	0
T84	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T162	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T228	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2649	0	0
T31	706	0	0	0
T32	0	10	0	0
T34	674	42	0	0
T36	0	37	0	0
T37	0	121	0	0
T56	1412	0	0	0
T75	0	69	0	0
T82	5016	0	0	0
T84	0	123	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T162	0	42	0	0
T172	0	42	0	0
T173	0	97	0	0
T228	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	6362	0	0
T1	916	0	0	0
T2	8651	11	0	0
T3	8682	7	0	0
T4	35375	4	0	0
T5	502	6	0	0
T6	25051	31	0	0
T7	9559	36	0	0
T13	522	3	0	0
T14	495	6	0	0
T15	2649	15	0	0
T17	0	24	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	14	0	0
T31	706	0	0	0
T34	674	2	0	0
T56	1412	0	0	0
T82	5016	0	0	0
T125	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T172	0	1	0	0
T211	0	1	0	0
T213	0	1	0	0
T229	0	2	0	0
T230	0	1	0	0
T231	0	1	0	0
T232	0	1	0	0
T233	0	1	0	0