Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T35,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T35,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T35,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T35,T32
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T35,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T37
0	1	Covered	T35,T218,T234
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T41
0	1	Covered	T33,T37,T134
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T33,T41
1	-	Covered	T33,T37,T134

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T35,T32
DetectSt	168	Covered	T35,T32,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T32,T33,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T32,T33
DebounceSt->IdleSt	163	Covered	T21,T235,T231
DetectSt->IdleSt	186	Covered	T35,T218,T234
DetectSt->StableSt	191	Covered	T32,T33,T37
IdleSt->DebounceSt	148	Covered	T21,T35,T32
StableSt->IdleSt	206	Covered	T32,T33,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T35,T32
0	1	Covered	T21,T35,T32
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T32,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T35,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T235,T231,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T35,T32
DetectSt	-	-	-	-	1	-	-	Covered	T35,T218,T234
DetectSt	-	-	-	-	0	1	-	Covered	T32,T33,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T37
StableSt	-	-	-	-	-	-	0	Covered	T32,T33,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	135	0	0
CntIncr_A	9022276	48550	0	0
CntNoWrap_A	9022276	8367808	0	0
DetectStDropOut_A	9022276	3	0	0
DetectedOut_A	9022276	50970	0	0
DetectedPulseOut_A	9022276	61	0	0
DisabledIdleSt_A	9022276	8259438	0	0
DisabledNoDetection_A	9022276	8261788	0	0
EnterDebounceSt_A	9022276	71	0	0
EnterDetectSt_A	9022276	64	0	0
EnterStableSt_A	9022276	61	0	0
PulseIsPulse_A	9022276	61	0	0
StayInStableSt	9022276	50885	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	135	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	2	0	0
T33	0	4	0	0
T35	0	2	0	0
T37	0	2	0	0
T41	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T73	0	2	0	0
T75	0	4	0	0
T134	0	2	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	48550	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	26	0	0
T32	0	29	0	0
T33	0	100	0	0
T35	0	26	0	0
T37	0	55	0	0
T41	0	100	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T73	0	16	0	0
T75	0	24	0	0
T134	0	46	0	0
T162	0	44846	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367808	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	3	0	0
T35	502	1	0	0
T59	492	0	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T218	0	1	0	0
T234	0	1	0	0
T236	492	0	0	0
T237	4413	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	50970	0	0
T32	7677	10	0	0
T33	2909	146	0	0
T36	1663	0	0	0
T37	0	1	0	0
T39	775	0	0	0
T40	939	0	0	0
T41	0	143	0	0
T45	4074	0	0	0
T46	703	0	0	0
T73	0	117	0	0
T75	0	16	0	0
T134	0	27	0	0
T135	0	9	0	0
T148	0	264	0	0
T162	0	44892	0	0
T238	27060	0	0	0
T239	527	0	0	0
T240	10354	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	61	0	0
T32	7677	1	0	0
T33	2909	2	0	0
T36	1663	0	0	0
T37	0	1	0	0
T39	775	0	0	0
T40	939	0	0	0
T41	0	1	0	0
T45	4074	0	0	0
T46	703	0	0	0
T73	0	1	0	0
T75	0	2	0	0
T134	0	1	0	0
T135	0	2	0	0
T148	0	2	0	0
T162	0	1	0	0
T238	27060	0	0	0
T239	527	0	0	0
T240	10354	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8259438	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8261788	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	71	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T73	0	1	0	0
T75	0	2	0	0
T134	0	1	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	64	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	502	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T59	492	0	0	0
T73	0	1	0	0
T75	0	2	0	0
T134	0	1	0	0
T135	0	2	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T162	0	1	0	0
T236	492	0	0	0
T237	4413	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	61	0	0
T32	7677	1	0	0
T33	2909	2	0	0
T36	1663	0	0	0
T37	0	1	0	0
T39	775	0	0	0
T40	939	0	0	0
T41	0	1	0	0
T45	4074	0	0	0
T46	703	0	0	0
T73	0	1	0	0
T75	0	2	0	0
T134	0	1	0	0
T135	0	2	0	0
T148	0	2	0	0
T162	0	1	0	0
T238	27060	0	0	0
T239	527	0	0	0
T240	10354	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	61	0	0
T32	7677	1	0	0
T33	2909	2	0	0
T36	1663	0	0	0
T37	0	1	0	0
T39	775	0	0	0
T40	939	0	0	0
T41	0	1	0	0
T45	4074	0	0	0
T46	703	0	0	0
T73	0	1	0	0
T75	0	2	0	0
T134	0	1	0	0
T135	0	2	0	0
T148	0	2	0	0
T162	0	1	0	0
T238	27060	0	0	0
T239	527	0	0	0
T240	10354	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	50885	0	0
T32	7677	9	0	0
T33	2909	143	0	0
T36	1663	0	0	0
T39	775	0	0	0
T40	939	0	0	0
T41	0	141	0	0
T45	4074	0	0	0
T46	703	0	0	0
T73	0	115	0	0
T75	0	14	0	0
T134	0	26	0	0
T135	0	7	0	0
T148	0	261	0	0
T149	0	28	0	0
T162	0	44890	0	0
T238	27060	0	0	0
T239	527	0	0	0
T240	10354	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	36	0	0
T33	2909	1	0	0
T36	1663	0	0	0
T37	0	1	0	0
T39	775	0	0	0
T40	939	0	0	0
T46	703	0	0	0
T47	650	0	0	0
T75	0	2	0	0
T125	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	502	0	0	0
T137	522	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T210	0	1	0	0
T239	527	0	0	0
T240	10354	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T35,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T35,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T35,T34,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T35,T34
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T35,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T34,T31
0	1	Covered	T39
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T34,T31
0	1	Covered	T31,T33,T39
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T34,T31
1	-	Covered	T31,T33,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T35,T34
DetectSt	168	Covered	T35,T34,T31
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T35,T34,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T34,T31
DebounceSt->IdleSt	163	Covered	T21,T125,T241
DetectSt->IdleSt	186	Covered	T39
DetectSt->StableSt	191	Covered	T35,T34,T31
IdleSt->DebounceSt	148	Covered	T21,T35,T34
StableSt->IdleSt	206	Covered	T31,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T35,T34
0	1	Covered	T21,T35,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T34,T31
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T35,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T34,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T125,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T35,T34
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T35,T34,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T35,T34,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	83	0	0
CntIncr_A	9022276	26286	0	0
CntNoWrap_A	9022276	8367860	0	0
DetectStDropOut_A	9022276	1	0	0
DetectedOut_A	9022276	3005	0	0
DetectedPulseOut_A	9022276	39	0	0
DisabledIdleSt_A	9022276	8172448	0	0
DisabledNoDetection_A	9022276	8174803	0	0
EnterDebounceSt_A	9022276	43	0	0
EnterDetectSt_A	9022276	40	0	0
EnterStableSt_A	9022276	39	0	0
PulseIsPulse_A	9022276	39	0	0
StayInStableSt	9022276	2947	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	6418	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	83	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T31	0	4	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T39	0	4	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	2	0	0
T161	0	4	0	0
T239	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	26286	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	27	0	0
T31	0	46	0	0
T32	0	29	0	0
T33	0	50	0	0
T34	0	22	0	0
T35	0	26	0	0
T39	0	74	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	51	0	0
T161	0	150	0	0
T239	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367860	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1	0	0
T36	1663	0	0	0
T39	775	1	0	0
T40	939	0	0	0
T47	650	0	0	0
T66	148860	0	0	0
T136	502	0	0	0
T137	522	0	0	0
T138	405	0	0	0
T139	522	0	0	0
T140	716	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	3005	0	0
T31	0	114	0	0
T32	0	10	0	0
T33	0	119	0	0
T34	0	71	0	0
T35	502	39	0	0
T39	0	43	0	0
T59	492	0	0	0
T75	0	91	0	0
T84	0	96	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T161	0	345	0	0
T236	492	0	0	0
T237	4413	0	0	0
T239	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	39	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	502	1	0	0
T39	0	1	0	0
T59	492	0	0	0
T75	0	2	0	0
T84	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T161	0	2	0	0
T236	492	0	0	0
T237	4413	0	0	0
T239	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8172448	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8174803	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	43	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	1	0	0
T161	0	2	0	0
T239	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	40	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	502	1	0	0
T39	0	2	0	0
T59	492	0	0	0
T75	0	2	0	0
T84	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T161	0	2	0	0
T236	492	0	0	0
T237	4413	0	0	0
T239	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	39	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	502	1	0	0
T39	0	1	0	0
T59	492	0	0	0
T75	0	2	0	0
T84	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T161	0	2	0	0
T236	492	0	0	0
T237	4413	0	0	0
T239	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	39	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	502	1	0	0
T39	0	1	0	0
T59	492	0	0	0
T75	0	2	0	0
T84	0	1	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T161	0	2	0	0
T236	492	0	0	0
T237	4413	0	0	0
T239	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2947	0	0
T31	0	111	0	0
T32	0	9	0	0
T33	0	118	0	0
T34	0	69	0	0
T35	502	37	0	0
T39	0	42	0	0
T59	492	0	0	0
T75	0	88	0	0
T84	0	95	0	0
T142	30277	0	0	0
T143	33792	0	0	0
T144	9687	0	0	0
T145	15508	0	0	0
T146	521	0	0	0
T147	25629	0	0	0
T161	0	342	0	0
T236	492	0	0	0
T237	4413	0	0	0
T239	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	6418	0	0
T1	916	0	0	0
T2	8651	12	0	0
T3	8682	13	0	0
T4	35375	7	0	0
T5	502	5	0	0
T6	25051	34	0	0
T7	9559	27	0	0
T13	522	5	0	0
T14	495	5	0	0
T15	2649	13	0	0
T17	0	24	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	19	0	0
T31	706	1	0	0
T33	0	1	0	0
T39	0	1	0	0
T56	1412	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	1	0	0
T210	0	1	0	0
T216	524	0	0	0
T217	421	0	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T9,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T9,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T34,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T34
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T9,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T32
0	1	Covered	T125,T218
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T32
0	1	Covered	T34,T39,T84
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T34,T32
1	-	Covered	T34,T39,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T9,T34
DetectSt	168	Covered	T9,T34,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T34,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T34,T32
DebounceSt->IdleSt	163	Covered	T21,T235,T242
DetectSt->IdleSt	186	Covered	T125,T218
DetectSt->StableSt	191	Covered	T9,T34,T32
IdleSt->DebounceSt	148	Covered	T21,T9,T34
StableSt->IdleSt	206	Covered	T34,T32,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T9,T34
0	1	Covered	T21,T9,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T34,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T9,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T34,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T235,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T9,T34
DetectSt	-	-	-	-	1	-	-	Covered	T125,T218
DetectSt	-	-	-	-	0	1	-	Covered	T9,T34,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T32,T39
StableSt	-	-	-	-	-	-	0	Covered	T9,T34,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	111	0	0
CntIncr_A	9022276	50922	0	0
CntNoWrap_A	9022276	8367832	0	0
DetectStDropOut_A	9022276	2	0	0
DetectedOut_A	9022276	46985	0	0
DetectedPulseOut_A	9022276	52	0	0
DisabledIdleSt_A	9022276	8175282	0	0
DisabledNoDetection_A	9022276	8177636	0	0
EnterDebounceSt_A	9022276	57	0	0
EnterDetectSt_A	9022276	54	0	0
EnterStableSt_A	9022276	52	0	0
PulseIsPulse_A	9022276	52	0	0
StayInStableSt	9022276	46914	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	111	0	0
T8	6469	0	0	0
T9	482	2	0	0
T21	7034	1	0	0
T32	0	2	0	0
T34	0	4	0	0
T39	0	4	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	2	0	0
T84	0	2	0	0
T163	0	4	0	0
T172	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	50922	0	0
T8	6469	0	0	0
T9	482	14	0	0
T21	7034	25	0	0
T32	0	29	0	0
T34	0	44	0	0
T39	0	74	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	12	0	0
T84	0	51	0	0
T163	0	30	0	0
T172	0	56	0	0
T173	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367832	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2	0	0
T125	258207	1	0	0
T218	0	1	0	0
T229	1256	0	0	0
T243	18765	0	0	0
T244	404	0	0	0
T245	808	0	0	0
T246	665	0	0	0
T247	446	0	0	0
T248	522	0	0	0
T249	503	0	0	0
T250	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46985	0	0
T9	482	39	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T32	0	9	0	0
T34	0	108	0	0
T39	0	172	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	46	0	0
T84	0	40	0	0
T120	0	257	0	0
T163	0	107	0	0
T172	0	114	0	0
T173	0	97	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	52	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T120	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8175282	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8177636	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	57	0	0
T8	6469	0	0	0
T9	482	1	0	0
T21	7034	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T39	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	54	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T120	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	52	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T120	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	52	0	0
T9	482	1	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T39	0	2	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T120	0	1	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46914	0	0
T9	482	37	0	0
T10	9365	0	0	0
T11	40083	0	0	0
T12	497	0	0	0
T32	0	8	0	0
T34	0	106	0	0
T39	0	169	0	0
T43	5267	0	0	0
T60	3289	0	0	0
T61	522	0	0	0
T75	0	44	0	0
T84	0	39	0	0
T120	0	255	0	0
T163	0	105	0	0
T172	0	113	0	0
T173	0	96	0	0
T174	422	0	0	0
T175	859	0	0	0
T176	406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	32	0	0
T31	706	0	0	0
T34	674	2	0	0
T39	0	1	0	0
T56	1412	0	0	0
T82	5016	0	0	0
T84	0	1	0	0
T125	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T12,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T12,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T30,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T12,T30
1	0	Covered	T4,T5,T2
1	1	Covered	T21,T12,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T30,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T30,T34
0	1	Covered	T34,T31,T37
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T30,T34
1	-	Covered	T34,T31,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T12,T30
DetectSt	168	Covered	T12,T30,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T30,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T30,T34
DebounceSt->IdleSt	163	Covered	T21
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T30,T34
IdleSt->DebounceSt	148	Covered	T21,T12,T30
StableSt->IdleSt	206	Covered	T34,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T12,T30
0	1	Covered	T21,T12,T30
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T30,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T12,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T30,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T12,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T30,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T12,T30,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	89	0	0
CntIncr_A	9022276	93445	0	0
CntNoWrap_A	9022276	8367854	0	0
DetectStDropOut_A	9022276	0	0	0
DetectedOut_A	9022276	137411	0	0
DetectedPulseOut_A	9022276	44	0	0
DisabledIdleSt_A	9022276	7900903	0	0
DisabledNoDetection_A	9022276	7903254	0	0
EnterDebounceSt_A	9022276	45	0	0
EnterDetectSt_A	9022276	44	0	0
EnterStableSt_A	9022276	44	0	0
PulseIsPulse_A	9022276	44	0	0
StayInStableSt	9022276	137343	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	6415	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	89	0	0
T8	6469	0	0	0
T9	482	0	0	0
T12	0	2	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	0	4	0	0
T37	0	4	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T161	0	4	0	0
T172	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	93445	0	0
T8	6469	0	0	0
T9	482	0	0	0
T12	0	21	0	0
T21	7034	27	0	0
T30	0	42848	0	0
T31	0	23	0	0
T32	0	29	0	0
T34	0	44	0	0
T37	0	110	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T161	0	150	0	0
T172	0	56	0	0
T173	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367854	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	137411	0	0
T12	497	39	0	0
T22	1328	0	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T30	0	96801	0	0
T31	0	9	0	0
T32	0	10	0	0
T34	0	43	0	0
T37	0	87	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T161	0	213	0	0
T163	0	51	0	0
T172	0	40	0	0
T173	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T12	497	1	0	0
T22	1328	0	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	2	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7900903	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7903254	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	45	0	0
T8	6469	0	0	0
T9	482	0	0	0
T12	0	1	0	0
T21	7034	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T161	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T12	497	1	0	0
T22	1328	0	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	2	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T12	497	1	0	0
T22	1328	0	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	2	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T12	497	1	0	0
T22	1328	0	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	2	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T161	0	2	0	0
T163	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	137343	0	0
T12	497	37	0	0
T22	1328	0	0	0
T26	393479	0	0	0
T29	36782	0	0	0
T30	0	96799	0	0
T31	0	8	0	0
T32	0	9	0	0
T34	0	40	0	0
T37	0	84	0	0
T62	526	0	0	0
T63	506	0	0	0
T64	10893	0	0	0
T126	403	0	0	0
T127	422	0	0	0
T128	446	0	0	0
T161	0	210	0	0
T163	0	48	0	0
T172	0	38	0	0
T173	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	6415	0	0
T1	916	0	0	0
T2	8651	12	0	0
T3	8682	7	0	0
T4	35375	3	0	0
T5	502	5	0	0
T6	25051	29	0	0
T7	9559	24	0	0
T13	522	5	0	0
T14	495	7	0	0
T15	2649	16	0	0
T17	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	19	0	0
T31	706	1	0	0
T34	674	1	0	0
T37	0	1	0	0
T56	1412	0	0	0
T73	0	1	0	0
T82	5016	0	0	0
T88	0	1	0	0
T125	0	1	0	0
T148	0	2	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T161	0	1	0	0
T163	0	1	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T30,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T12,T30
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T242
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T30,T31,T39
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T32
1	-	Covered	T30,T31,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T30,T31
DetectSt	168	Covered	T30,T31,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T30,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T32
DebounceSt->IdleSt	163	Covered	T21,T40,T251
DetectSt->IdleSt	186	Covered	T242
DetectSt->StableSt	191	Covered	T30,T31,T32
IdleSt->DebounceSt	148	Covered	T21,T30,T31
StableSt->IdleSt	206	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T30,T31
0	1	Covered	T21,T30,T31
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T251,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T242
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	136	0	0
CntIncr_A	9022276	46279	0	0
CntNoWrap_A	9022276	8367807	0	0
DetectStDropOut_A	9022276	1	0	0
DetectedOut_A	9022276	59790	0	0
DetectedPulseOut_A	9022276	65	0	0
DisabledIdleSt_A	9022276	8166776	0	0
DisabledNoDetection_A	9022276	8169121	0	0
EnterDebounceSt_A	9022276	70	0	0
EnterDetectSt_A	9022276	66	0	0
EnterStableSt_A	9022276	65	0	0
PulseIsPulse_A	9022276	65	0	0
StayInStableSt	9022276	59705	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	136	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	4	0	0
T32	0	2	0	0
T37	0	2	0	0
T39	0	4	0	0
T40	0	3	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	4	0	0
T163	0	2	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46279	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	26	0	0
T30	0	42848	0	0
T31	0	46	0	0
T32	0	29	0	0
T37	0	55	0	0
T39	0	74	0	0
T40	0	160	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	102	0	0
T163	0	15	0	0
T172	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367807	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1	0	0
T199	38610	0	0	0
T242	12081	1	0	0
T252	1423	0	0	0
T253	501	0	0	0
T254	502	0	0	0
T255	723	0	0	0
T256	7042	0	0	0
T257	18166	0	0	0
T258	788	0	0	0
T259	15583	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	59790	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	53911	0	0
T31	0	95	0	0
T32	0	9	0	0
T37	0	20	0	0
T39	0	202	0	0
T40	0	184	0	0
T84	0	82	0	0
T134	0	40	0	0
T163	0	66	0	0
T172	0	52	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	65	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T84	0	2	0	0
T134	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8166776	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8169121	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	70	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	2	0	0
T163	0	1	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	66	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T84	0	2	0	0
T134	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	65	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T84	0	2	0	0
T134	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	65	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T84	0	2	0	0
T134	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	59705	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	53910	0	0
T31	0	92	0	0
T32	0	8	0	0
T37	0	19	0	0
T39	0	199	0	0
T40	0	183	0	0
T84	0	79	0	0
T134	0	38	0	0
T163	0	65	0	0
T172	0	49	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T75	0	4	0	0
T84	0	1	0	0
T135	0	1	0	0
T163	0	1	0	0
T172	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T30,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T12,T30
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T31,T33,T84
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T32
1	-	Covered	T31,T33,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T30,T31
DetectSt	168	Covered	T30,T31,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T30,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T32
DebounceSt->IdleSt	163	Covered	T21,T39
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T30,T31,T32
IdleSt->DebounceSt	148	Covered	T21,T30,T31
StableSt->IdleSt	206	Covered	T31,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T30,T31
0	1	Covered	T21,T30,T31
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T39
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T30,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	90	0	0
CntIncr_A	9022276	93074	0	0
CntNoWrap_A	9022276	8367853	0	0
DetectStDropOut_A	9022276	0	0	0
DetectedOut_A	9022276	40855	0	0
DetectedPulseOut_A	9022276	44	0	0
DisabledIdleSt_A	9022276	7900023	0	0
DisabledNoDetection_A	9022276	7902369	0	0
EnterDebounceSt_A	9022276	46	0	0
EnterDetectSt_A	9022276	44	0	0
EnterStableSt_A	9022276	44	0	0
PulseIsPulse_A	9022276	44	0	0
StayInStableSt	9022276	40786	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9022276	7227	0	0
gen_low_level_sva.LowLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	90	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	93074	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	25	0	0
T30	0	42848	0	0
T31	0	23	0	0
T32	0	29	0	0
T33	0	100	0	0
T36	0	83	0	0
T37	0	55	0	0
T39	0	37	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	51	0	0
T163	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367853	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	40855	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	41	0	0
T31	0	40	0	0
T32	0	10	0	0
T33	0	136	0	0
T36	0	47	0	0
T37	0	46	0	0
T73	0	40	0	0
T75	0	166	0	0
T84	0	31	0	0
T163	0	119	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T73	0	1	0	0
T75	0	4	0	0
T84	0	1	0	0
T163	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7900023	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7902369	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	46	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	9287	0	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T84	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T73	0	1	0	0
T75	0	4	0	0
T84	0	1	0	0
T163	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T73	0	1	0	0
T75	0	4	0	0
T84	0	1	0	0
T163	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	44	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T73	0	1	0	0
T75	0	4	0	0
T84	0	1	0	0
T163	0	1	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	40786	0	0
T27	9195	0	0	0
T28	2632	0	0	0
T30	182907	39	0	0
T31	0	39	0	0
T32	0	9	0	0
T33	0	133	0	0
T36	0	45	0	0
T37	0	44	0	0
T73	0	38	0	0
T75	0	160	0	0
T84	0	30	0	0
T163	0	117	0	0
T182	526	0	0	0
T183	502	0	0	0
T184	403	0	0	0
T185	444	0	0	0
T186	402	0	0	0
T187	2682	0	0	0
T188	424	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7227	0	0
T1	916	4	0	0
T2	8651	11	0	0
T3	8682	11	0	0
T4	35375	12	0	0
T5	502	5	0	0
T6	25051	29	0	0
T7	9559	30	0	0
T13	522	3	0	0
T14	495	7	0	0
T15	2649	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	18	0	0
T31	706	1	0	0
T33	0	1	0	0
T56	1412	0	0	0
T75	0	2	0	0
T84	0	1	0	0
T135	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	492	0	0	0
T155	2976	0	0	0
T156	497	0	0	0
T157	491	0	0	0
T158	3470	0	0	0
T159	502	0	0	0
T216	524	0	0	0
T217	421	0	0	0
T230	0	2	0	0
T231	0	1	0	0