Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T17
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T17
0	1	Covered	T17,T21,T42
1	0	Covered	T17,T21,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T21
0	1	Covered	T6,T7,T21
1	0	Covered	T21,T260

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T21
1	-	Covered	T6,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T17
DetectSt	168	Covered	T6,T7,T17
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T17
DebounceSt->IdleSt	163	Covered	T21,T32
DetectSt->IdleSt	186	Covered	T17,T21,T42
DetectSt->StableSt	191	Covered	T6,T7,T21
IdleSt->DebounceSt	148	Covered	T6,T7,T17
StableSt->IdleSt	206	Covered	T6,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T17
0	1	Covered	T6,T7,T17
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T17
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T17
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T17
DetectSt	-	-	-	-	1	-	-	Covered	T17,T21,T42
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T21
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T17
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T21
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	2972	0	0
CntIncr_A	9022276	106980	0	0
CntNoWrap_A	9022276	8364971	0	0
DetectStDropOut_A	9022276	386	0	0
DetectedOut_A	9022276	81991	0	0
DetectedPulseOut_A	9022276	972	0	0
DisabledIdleSt_A	9022276	7883933	0	0
DisabledNoDetection_A	9022276	7886128	0	0
EnterDebounceSt_A	9022276	1488	0	0
EnterDetectSt_A	9022276	1484	0	0
EnterStableSt_A	9022276	972	0	0
PulseIsPulse_A	9022276	972	0	0
StayInStableSt	9022276	80907	0	0
gen_high_event_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	856	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2972	0	0
T6	25051	22	0	0
T7	9559	10	0	0
T8	6469	0	0	0
T10	0	24	0	0
T16	739	0	0	0
T17	7208	46	0	0
T21	7034	16	0	0
T27	0	50	0	0
T42	0	46	0	0
T43	0	40	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	34	0	0
T65	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	106980	0	0
T6	25051	836	0	0
T7	9559	210	0	0
T8	6469	0	0	0
T10	0	576	0	0
T16	739	0	0	0
T17	7208	1504	0	0
T21	7034	414	0	0
T27	0	1100	0	0
T42	0	1410	0	0
T43	0	1062	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	1377	0	0
T65	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8364971	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24578	0	0
T7	9559	9138	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	386	0	0
T8	6469	0	0	0
T17	7208	13	0	0
T21	7034	1	0	0
T32	0	1	0	0
T42	9287	13	0	0
T43	0	20	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T80	0	12	0	0
T82	0	6	0	0
T83	0	20	0	0
T85	0	12	0	0
T86	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	81991	0	0
T6	25051	609	0	0
T7	9559	150	0	0
T8	6469	0	0	0
T10	0	196	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	311	0	0
T27	0	1647	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	449	0	0
T65	0	240	0	0
T261	0	79	0	0
T262	0	466	0	0
T263	0	710	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	972	0	0
T6	25051	11	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	12	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	25	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	4	0	0
T261	0	2	0	0
T262	0	8	0	0
T263	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7883933	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	18392	0	0
T7	9559	5467	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7886128	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	18398	0	0
T7	9559	5468	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1488	0	0
T6	25051	11	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	12	0	0
T16	739	0	0	0
T17	7208	23	0	0
T21	7034	9	0	0
T27	0	25	0	0
T42	0	23	0	0
T43	0	20	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1484	0	0
T6	25051	11	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	12	0	0
T16	739	0	0	0
T17	7208	23	0	0
T21	7034	7	0	0
T27	0	25	0	0
T42	0	23	0	0
T43	0	20	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	972	0	0
T6	25051	11	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	12	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	25	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	4	0	0
T261	0	2	0	0
T262	0	8	0	0
T263	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	972	0	0
T6	25051	11	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	12	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	25	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	4	0	0
T261	0	2	0	0
T262	0	8	0	0
T263	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	80907	0	0
T6	25051	597	0	0
T7	9559	145	0	0
T8	6469	0	0	0
T10	0	184	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	306	0	0
T27	0	1621	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	431	0	0
T65	0	235	0	0
T261	0	77	0	0
T262	0	458	0	0
T263	0	688	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	856	0	0
T6	25051	10	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	12	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	4	0	0
T27	0	24	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	16	0	0
T65	0	3	0	0
T261	0	2	0	0
T262	0	8	0	0
T263	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T3,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T3,T81,T84
1	0	Covered	T21,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T21
0	1	Covered	T2,T6,T11
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T21
1	-	Covered	T2,T6,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T15
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T6,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T3,T15,T21
DetectSt->IdleSt	186	Covered	T3,T21,T81
DetectSt->StableSt	191	Covered	T2,T6,T21
IdleSt->DebounceSt	148	Covered	T2,T3,T15
StableSt->IdleSt	206	Covered	T2,T6,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T15
0	1	Covered	T2,T3,T15
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T15,T29
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T15
DetectSt	-	-	-	-	1	-	-	Covered	T3,T21,T81
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T21
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T21
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	1125	0	0
CntIncr_A	9022276	59054	0	0
CntNoWrap_A	9022276	8366818	0	0
DetectStDropOut_A	9022276	79	0	0
DetectedOut_A	9022276	20613	0	0
DetectedPulseOut_A	9022276	436	0	0
DisabledIdleSt_A	9022276	7953199	0	0
DisabledNoDetection_A	9022276	7954802	0	0
EnterDebounceSt_A	9022276	607	0	0
EnterDetectSt_A	9022276	519	0	0
EnterStableSt_A	9022276	436	0	0
PulseIsPulse_A	9022276	436	0	0
StayInStableSt	9022276	20134	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	391	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1125	0	0
T2	8651	4	0	0
T3	8682	25	0	0
T6	25051	2	0	0
T7	9559	0	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	1	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	8	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	29	0	0
T64	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	59054	0	0
T2	8651	154	0	0
T3	8682	1071	0	0
T6	25051	75	0	0
T7	9559	0	0	0
T11	0	522	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	20	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	162	0	0
T27	0	72	0	0
T28	0	25	0	0
T29	0	1615	0	0
T64	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8366818	0	0
T1	916	515	0	0
T2	8651	8238	0	0
T3	8682	8235	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24598	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	79	0	0
T3	8682	12	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	0	0	0
T48	501	0	0	0
T81	0	3	0	0
T84	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	4	0	0
T92	0	3	0	0
T93	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	20613	0	0
T2	8651	12	0	0
T3	8682	0	0	0
T6	25051	60	0	0
T7	9559	0	0	0
T11	0	10	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	81	0	0
T27	0	54	0	0
T28	0	3	0	0
T29	0	96	0	0
T64	0	42	0	0
T65	0	43	0	0
T103	0	392	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	436	0	0
T2	8651	2	0	0
T3	8682	0	0	0
T6	25051	1	0	0
T7	9559	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	14	0	0
T64	0	1	0	0
T65	0	1	0	0
T103	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7953199	0	0
T1	916	515	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	23992	0	0
T7	9559	8998	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	214	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7954802	0	0
T1	916	516	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	23999	0	0
T7	9559	9000	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	218	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	607	0	0
T2	8651	2	0	0
T3	8682	13	0	0
T6	25051	1	0	0
T7	9559	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	1	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	15	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	519	0	0
T2	8651	2	0	0
T3	8682	12	0	0
T6	25051	1	0	0
T7	9559	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	3	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	14	0	0
T64	0	1	0	0
T65	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	436	0	0
T2	8651	2	0	0
T3	8682	0	0	0
T6	25051	1	0	0
T7	9559	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	14	0	0
T64	0	1	0	0
T65	0	1	0	0
T103	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	436	0	0
T2	8651	2	0	0
T3	8682	0	0	0
T6	25051	1	0	0
T7	9559	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	14	0	0
T64	0	1	0	0
T65	0	1	0	0
T103	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	20134	0	0
T2	8651	10	0	0
T3	8682	0	0	0
T6	25051	59	0	0
T7	9559	0	0	0
T11	0	8	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	80	0	0
T27	0	53	0	0
T28	0	2	0	0
T29	0	82	0	0
T64	0	40	0	0
T65	0	42	0	0
T103	0	385	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	391	0	0
T2	8651	2	0	0
T3	8682	0	0	0
T6	25051	1	0	0
T7	9559	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	14	0	0
T38	0	1	0	0
T65	0	1	0	0
T103	0	7	0	0
T105	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T17
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T17
0	1	Covered	T17,T21,T43
1	0	Covered	T17,T21,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T21
0	1	Covered	T6,T7,T21
1	0	Covered	T21,T264,T265

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T21
1	-	Covered	T6,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T17
DetectSt	168	Covered	T6,T7,T17
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T17
DebounceSt->IdleSt	163	Covered	T21,T32
DetectSt->IdleSt	186	Covered	T17,T21,T43
DetectSt->StableSt	191	Covered	T6,T7,T21
IdleSt->DebounceSt	148	Covered	T6,T7,T17
StableSt->IdleSt	206	Covered	T6,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T17
0	1	Covered	T6,T7,T17
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T17
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T17
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T17
DetectSt	-	-	-	-	1	-	-	Covered	T17,T21,T43
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T21
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T17
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T21
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	3046	0	0
CntIncr_A	9022276	103188	0	0
CntNoWrap_A	9022276	8364897	0	0
DetectStDropOut_A	9022276	384	0	0
DetectedOut_A	9022276	75524	0	0
DetectedPulseOut_A	9022276	949	0	0
DisabledIdleSt_A	9022276	7892635	0	0
DisabledNoDetection_A	9022276	7894856	0	0
EnterDebounceSt_A	9022276	1525	0	0
EnterDetectSt_A	9022276	1521	0	0
EnterStableSt_A	9022276	949	0	0
PulseIsPulse_A	9022276	949	0	0
StayInStableSt	9022276	74488	0	0
gen_high_event_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	849	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	3046	0	0
T6	25051	48	0	0
T7	9559	28	0	0
T8	6469	0	0	0
T10	0	28	0	0
T16	739	0	0	0
T17	7208	18	0	0
T21	7034	16	0	0
T27	0	24	0	0
T42	0	46	0	0
T43	0	26	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	34	0	0
T65	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	103188	0	0
T6	25051	2160	0	0
T7	9559	742	0	0
T8	6469	0	0	0
T10	0	714	0	0
T16	739	0	0	0
T17	7208	585	0	0
T21	7034	519	0	0
T27	0	432	0	0
T42	0	1219	0	0
T43	0	682	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	1292	0	0
T65	0	317	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8364897	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24552	0	0
T7	9559	9120	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	384	0	0
T8	6469	0	0	0
T17	7208	5	0	0
T21	7034	1	0	0
T32	0	1	0	0
T42	9287	0	0	0
T43	0	13	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T65	0	5	0	0
T80	0	9	0	0
T82	0	11	0	0
T85	0	9	0	0
T142	0	9	0	0
T144	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	75524	0	0
T6	25051	1953	0	0
T7	9559	1139	0	0
T8	6469	0	0	0
T10	0	335	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	351	0	0
T27	0	588	0	0
T42	0	1765	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	534	0	0
T261	0	682	0	0
T262	0	42	0	0
T263	0	1227	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	949	0	0
T6	25051	24	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T10	0	14	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	12	0	0
T42	0	23	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T261	0	16	0	0
T262	0	4	0	0
T263	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7892635	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	17241	0	0
T7	9559	4559	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7894856	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	17244	0	0
T7	9559	4560	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1525	0	0
T6	25051	24	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T10	0	14	0	0
T16	739	0	0	0
T17	7208	9	0	0
T21	7034	9	0	0
T27	0	12	0	0
T42	0	23	0	0
T43	0	13	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1521	0	0
T6	25051	24	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T10	0	14	0	0
T16	739	0	0	0
T17	7208	9	0	0
T21	7034	7	0	0
T27	0	12	0	0
T42	0	23	0	0
T43	0	13	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T65	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	949	0	0
T6	25051	24	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T10	0	14	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	12	0	0
T42	0	23	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T261	0	16	0	0
T262	0	4	0	0
T263	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	949	0	0
T6	25051	24	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T10	0	14	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T27	0	12	0	0
T42	0	23	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	17	0	0
T261	0	16	0	0
T262	0	4	0	0
T263	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	74488	0	0
T6	25051	1925	0	0
T7	9559	1125	0	0
T8	6469	0	0	0
T10	0	320	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	346	0	0
T27	0	576	0	0
T42	0	1741	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	516	0	0
T261	0	666	0	0
T262	0	38	0	0
T263	0	1199	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	849	0	0
T6	25051	20	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T10	0	13	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	4	0	0
T27	0	12	0	0
T42	0	22	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	16	0	0
T261	0	16	0	0
T262	0	4	0	0
T263	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T266,T32
1	0	Covered	T21,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T21
0	1	Covered	T6,T7,T21
1	0	Covered	T68,T267

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T21
1	-	Covered	T6,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T2,T21,T8
DetectSt->IdleSt	186	Covered	T2,T21,T266
DetectSt->StableSt	191	Covered	T6,T7,T21
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T6,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T8,T11
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T21,T266
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T21
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	974	0	0
CntIncr_A	9022276	55786	0	0
CntNoWrap_A	9022276	8366969	0	0
DetectStDropOut_A	9022276	69	0	0
DetectedOut_A	9022276	18041	0	0
DetectedPulseOut_A	9022276	389	0	0
DisabledIdleSt_A	9022276	7969808	0	0
DisabledNoDetection_A	9022276	7971504	0	0
EnterDebounceSt_A	9022276	513	0	0
EnterDetectSt_A	9022276	461	0	0
EnterStableSt_A	9022276	389	0	0
PulseIsPulse_A	9022276	389	0	0
StayInStableSt	9022276	17627	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	361	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	974	0	0
T2	8651	12	0	0
T3	8682	0	0	0
T6	25051	6	0	0
T7	9559	8	0	0
T8	0	1	0	0
T10	0	2	0	0
T11	0	27	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	8	0	0
T29	0	17	0	0
T42	0	2	0	0
T64	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	55786	0	0
T2	8651	486	0	0
T3	8682	0	0	0
T6	25051	180	0	0
T7	9559	236	0	0
T8	0	16	0	0
T10	0	55	0	0
T11	0	3521	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	205	0	0
T29	0	585	0	0
T42	0	86	0	0
T64	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8366969	0	0
T1	916	515	0	0
T2	8651	8230	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24594	0	0
T7	9559	9140	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	69	0	0
T2	8651	5	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	0	0	0
T32	0	1	0	0
T90	0	5	0	0
T93	0	3	0	0
T118	0	4	0	0
T266	0	4	0	0
T268	0	6	0	0
T269	0	8	0	0
T270	0	1	0	0
T271	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	18041	0	0
T6	25051	221	0	0
T7	9559	255	0	0
T8	6469	0	0	0
T10	0	76	0	0
T11	0	139	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	79	0	0
T27	0	49	0	0
T29	0	404	0	0
T42	0	48	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	46	0	0
T81	0	31	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	389	0	0
T6	25051	3	0	0
T7	9559	4	0	0
T8	6469	0	0	0
T10	0	1	0	0
T11	0	13	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T29	0	8	0	0
T42	0	1	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	1	0	0
T81	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7969808	0	0
T1	916	515	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	22651	0	0
T7	9559	8009	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7971504	0	0
T1	916	516	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	22655	0	0
T7	9559	8011	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	513	0	0
T2	8651	7	0	0
T3	8682	0	0	0
T6	25051	3	0	0
T7	9559	4	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	14	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T29	0	9	0	0
T42	0	1	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	461	0	0
T2	8651	5	0	0
T3	8682	0	0	0
T6	25051	3	0	0
T7	9559	4	0	0
T10	0	1	0	0
T11	0	13	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	3	0	0
T27	0	1	0	0
T29	0	8	0	0
T42	0	1	0	0
T64	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	389	0	0
T6	25051	3	0	0
T7	9559	4	0	0
T8	6469	0	0	0
T10	0	1	0	0
T11	0	13	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T29	0	8	0	0
T42	0	1	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	1	0	0
T81	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	389	0	0
T6	25051	3	0	0
T7	9559	4	0	0
T8	6469	0	0	0
T10	0	1	0	0
T11	0	13	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T29	0	8	0	0
T42	0	1	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	1	0	0
T81	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	17627	0	0
T6	25051	218	0	0
T7	9559	251	0	0
T8	6469	0	0	0
T10	0	75	0	0
T11	0	126	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	78	0	0
T27	0	48	0	0
T29	0	396	0	0
T42	0	46	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	44	0	0
T81	0	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	361	0	0
T6	25051	3	0	0
T7	9559	4	0	0
T8	6469	0	0	0
T10	0	1	0	0
T11	0	13	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T27	0	1	0	0
T29	0	8	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T81	0	4	0	0
T103	0	8	0	0
T263	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T17
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T21
1	1	Covered	T6,T7,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T17
0	1	Covered	T21,T42,T10
1	0	Covered	T21,T42,T10

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T17
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T10,T94

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T17
1	-	Covered	T6,T7,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T17
DetectSt	168	Covered	T6,T7,T17
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T17
DebounceSt->IdleSt	163	Covered	T21,T32
DetectSt->IdleSt	186	Covered	T21,T42,T10
DetectSt->StableSt	191	Covered	T6,T7,T17
IdleSt->DebounceSt	148	Covered	T6,T7,T17
StableSt->IdleSt	206	Covered	T6,T7,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T17
0	1	Covered	T6,T7,T17
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T17
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T17
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T17
DetectSt	-	-	-	-	1	-	-	Covered	T21,T42,T10
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T17
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T17
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T17
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	3278	0	0
CntIncr_A	9022276	115874	0	0
CntNoWrap_A	9022276	8364665	0	0
DetectStDropOut_A	9022276	492	0	0
DetectedOut_A	9022276	87906	0	0
DetectedPulseOut_A	9022276	927	0	0
DisabledIdleSt_A	9022276	7884765	0	0
DisabledNoDetection_A	9022276	7886966	0	0
EnterDebounceSt_A	9022276	1641	0	0
EnterDetectSt_A	9022276	1637	0	0
EnterStableSt_A	9022276	927	0	0
PulseIsPulse_A	9022276	927	0	0
StayInStableSt	9022276	86872	0	0
gen_high_event_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	810	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	3278	0	0
T6	25051	34	0	0
T7	9559	30	0	0
T8	6469	0	0	0
T10	0	22	0	0
T16	739	0	0	0
T17	7208	48	0	0
T21	7034	16	0	0
T27	0	50	0	0
T42	0	50	0	0
T43	0	30	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	60	0	0
T65	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	115874	0	0
T6	25051	1513	0	0
T7	9559	780	0	0
T8	6469	0	0	0
T10	0	685	0	0
T16	739	0	0	0
T17	7208	1536	0	0
T21	7034	569	0	0
T27	0	925	0	0
T42	0	1547	0	0
T43	0	789	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	1650	0	0
T65	0	384	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8364665	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24566	0	0
T7	9559	9118	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	492	0	0
T8	6469	0	0	0
T9	482	0	0	0
T10	0	2	0	0
T21	7034	1	0	0
T42	9287	12	0	0
T43	0	15	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T65	0	6	0	0
T80	0	15	0	0
T82	0	2	0	0
T83	0	20	0	0
T144	0	8	0	0
T262	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	87906	0	0
T6	25051	1760	0	0
T7	9559	802	0	0
T8	6469	0	0	0
T10	0	1	0	0
T16	739	0	0	0
T17	7208	1356	0	0
T21	7034	354	0	0
T27	0	1822	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	2560	0	0
T142	0	606	0	0
T261	0	2499	0	0
T263	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	927	0	0
T6	25051	17	0	0
T7	9559	15	0	0
T8	6469	0	0	0
T10	0	1	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	5	0	0
T27	0	25	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	30	0	0
T142	0	9	0	0
T261	0	21	0	0
T263	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7884765	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	17270	0	0
T7	9559	4926	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7886966	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	17273	0	0
T7	9559	4926	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1641	0	0
T6	25051	17	0	0
T7	9559	15	0	0
T8	6469	0	0	0
T10	0	11	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	9	0	0
T27	0	25	0	0
T42	0	25	0	0
T43	0	15	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	30	0	0
T65	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1637	0	0
T6	25051	17	0	0
T7	9559	15	0	0
T8	6469	0	0	0
T10	0	11	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	7	0	0
T27	0	25	0	0
T42	0	25	0	0
T43	0	15	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	30	0	0
T65	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	927	0	0
T6	25051	17	0	0
T7	9559	15	0	0
T8	6469	0	0	0
T10	0	1	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	5	0	0
T27	0	25	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	30	0	0
T142	0	9	0	0
T261	0	21	0	0
T263	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	927	0	0
T6	25051	17	0	0
T7	9559	15	0	0
T8	6469	0	0	0
T10	0	1	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	5	0	0
T27	0	25	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	30	0	0
T142	0	9	0	0
T261	0	21	0	0
T263	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	86872	0	0
T6	25051	1739	0	0
T7	9559	786	0	0
T8	6469	0	0	0
T16	739	0	0	0
T17	7208	1332	0	0
T21	7034	349	0	0
T27	0	1796	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	2529	0	0
T142	0	596	0	0
T261	0	2477	0	0
T263	0	137	0	0
T272	0	5945	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	810	0	0
T6	25051	13	0	0
T7	9559	14	0	0
T8	6469	0	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	4	0	0
T27	0	24	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	29	0	0
T142	0	8	0	0
T261	0	20	0	0
T263	0	5	0	0
T272	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T29,T103
1	0	Covered	T21,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T7
1	-	Covered	T3,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T2,T17,T21
DetectSt->IdleSt	186	Covered	T2,T21,T29
DetectSt->StableSt	191	Covered	T3,T6,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T17,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T2,T21,T29
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	869	0	0
CntIncr_A	9022276	51147	0	0
CntNoWrap_A	9022276	8367074	0	0
DetectStDropOut_A	9022276	107	0	0
DetectedOut_A	9022276	16410	0	0
DetectedPulseOut_A	9022276	303	0	0
DisabledIdleSt_A	9022276	7954304	0	0
DisabledNoDetection_A	9022276	7955981	0	0
EnterDebounceSt_A	9022276	455	0	0
EnterDetectSt_A	9022276	415	0	0
EnterStableSt_A	9022276	303	0	0
PulseIsPulse_A	9022276	303	0	0
StayInStableSt	9022276	16065	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	256	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	869	0	0
T2	8651	23	0	0
T3	8682	12	0	0
T6	25051	8	0	0
T7	9559	2	0	0
T8	0	1	0	0
T11	0	10	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	3	0	0
T21	7034	8	0	0
T29	0	16	0	0
T64	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	51147	0	0
T2	8651	959	0	0
T3	8682	450	0	0
T6	25051	252	0	0
T7	9559	66	0	0
T8	0	16	0	0
T11	0	1266	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	131	0	0
T21	7034	206	0	0
T29	0	956	0	0
T64	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367074	0	0
T1	916	515	0	0
T2	8651	8219	0	0
T3	8682	8248	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24592	0	0
T7	9559	9146	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	107	0	0
T2	8651	11	0	0
T3	8682	0	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	0	0	0
T29	0	8	0	0
T88	0	7	0	0
T92	0	1	0	0
T103	0	8	0	0
T120	0	6	0	0
T125	0	1	0	0
T270	0	6	0	0
T271	0	4	0	0
T273	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	16410	0	0
T3	8682	55	0	0
T6	25051	283	0	0
T7	9559	58	0	0
T11	0	186	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	34	0	0
T21	7034	79	0	0
T27	0	85	0	0
T48	501	0	0	0
T64	0	54	0	0
T105	0	711	0	0
T261	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	303	0	0
T3	8682	6	0	0
T6	25051	4	0	0
T7	9559	1	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	1	0	0
T21	7034	1	0	0
T27	0	1	0	0
T48	501	0	0	0
T64	0	1	0	0
T105	0	8	0	0
T261	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7954304	0	0
T1	916	515	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	22844	0	0
T7	9559	8347	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7955981	0	0
T1	916	516	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	22848	0	0
T7	9559	8348	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	455	0	0
T2	8651	12	0	0
T3	8682	6	0	0
T6	25051	4	0	0
T7	9559	1	0	0
T8	0	1	0	0
T11	0	6	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	2	0	0
T21	7034	5	0	0
T29	0	8	0	0
T64	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	415	0	0
T2	8651	11	0	0
T3	8682	6	0	0
T6	25051	4	0	0
T7	9559	1	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	1	0	0
T21	7034	3	0	0
T27	0	1	0	0
T29	0	8	0	0
T64	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	303	0	0
T3	8682	6	0	0
T6	25051	4	0	0
T7	9559	1	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	1	0	0
T21	7034	1	0	0
T27	0	1	0	0
T48	501	0	0	0
T64	0	1	0	0
T105	0	8	0	0
T261	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	303	0	0
T3	8682	6	0	0
T6	25051	4	0	0
T7	9559	1	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	1	0	0
T21	7034	1	0	0
T27	0	1	0	0
T48	501	0	0	0
T64	0	1	0	0
T105	0	8	0	0
T261	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	16065	0	0
T3	8682	49	0	0
T6	25051	279	0	0
T7	9559	57	0	0
T11	0	182	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	33	0	0
T21	7034	78	0	0
T27	0	84	0	0
T48	501	0	0	0
T64	0	52	0	0
T105	0	703	0	0
T261	0	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	256	0	0
T3	8682	6	0	0
T6	25051	4	0	0
T7	9559	1	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	1	0	0
T21	7034	1	0	0
T27	0	1	0	0
T48	501	0	0	0
T105	0	8	0	0
T142	0	1	0	0
T261	0	1	0	0