Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T17
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T17
0	1	Covered	T21,T42,T43
1	0	Covered	T17,T21,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T21
0	1	Covered	T6,T7,T21
1	0	Covered	T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T21
1	-	Covered	T6,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T17
DetectSt	168	Covered	T6,T7,T17
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T17
DebounceSt->IdleSt	163	Covered	T21,T32
DetectSt->IdleSt	186	Covered	T17,T21,T42
DetectSt->StableSt	191	Covered	T6,T7,T21
IdleSt->DebounceSt	148	Covered	T6,T7,T17
StableSt->IdleSt	206	Covered	T6,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T17
0	1	Covered	T6,T7,T17
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T17
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T17
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T17
DetectSt	-	-	-	-	1	-	-	Covered	T17,T21,T42
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T21
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T17
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T21
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	2890	0	0
CntIncr_A	9022276	97153	0	0
CntNoWrap_A	9022276	8365053	0	0
DetectStDropOut_A	9022276	389	0	0
DetectedOut_A	9022276	75919	0	0
DetectedPulseOut_A	9022276	858	0	0
DisabledIdleSt_A	9022276	7894027	0	0
DisabledNoDetection_A	9022276	7896249	0	0
EnterDebounceSt_A	9022276	1448	0	0
EnterDetectSt_A	9022276	1442	0	0
EnterStableSt_A	9022276	858	0	0
PulseIsPulse_A	9022276	858	0	0
StayInStableSt	9022276	74976	0	0
gen_high_event_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	760	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	2890	0	0
T6	25051	12	0	0
T7	9559	10	0	0
T8	6469	0	0	0
T10	0	42	0	0
T16	739	0	0	0
T17	7208	24	0	0
T21	7034	17	0	0
T27	0	18	0	0
T42	0	6	0	0
T43	0	40	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	12	0	0
T65	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	97153	0	0
T6	25051	402	0	0
T7	9559	225	0	0
T8	6469	0	0	0
T10	0	1218	0	0
T16	739	0	0	0
T17	7208	788	0	0
T21	7034	535	0	0
T27	0	549	0	0
T42	0	183	0	0
T43	0	1062	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	420	0	0
T65	0	252	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8365053	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24588	0	0
T7	9559	9138	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	389	0	0
T8	6469	0	0	0
T9	482	0	0	0
T21	7034	1	0	0
T27	0	2	0	0
T42	9287	1	0	0
T43	0	20	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T52	522	0	0	0
T53	922	0	0	0
T80	0	15	0	0
T82	0	25	0	0
T83	0	7	0	0
T85	0	10	0	0
T144	0	9	0	0
T274	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	75919	0	0
T6	25051	307	0	0
T7	9559	132	0	0
T8	6469	0	0	0
T10	0	1503	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	278	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	188	0	0
T65	0	1595	0	0
T142	0	6628	0	0
T261	0	670	0	0
T262	0	2100	0	0
T263	0	2394	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	858	0	0
T6	25051	6	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	21	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	6	0	0
T65	0	9	0	0
T142	0	19	0	0
T261	0	14	0	0
T262	0	20	0	0
T263	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7894027	0	0
T1	916	515	0	0
T2	8651	8242	0	0
T3	8682	8260	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	18561	0	0
T7	9559	5472	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7896249	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	18568	0	0
T7	9559	5473	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1448	0	0
T6	25051	6	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	21	0	0
T16	739	0	0	0
T17	7208	12	0	0
T21	7034	10	0	0
T27	0	9	0	0
T42	0	3	0	0
T43	0	20	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	6	0	0
T65	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	1442	0	0
T6	25051	6	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	21	0	0
T16	739	0	0	0
T17	7208	12	0	0
T21	7034	7	0	0
T27	0	9	0	0
T42	0	3	0	0
T43	0	20	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	6	0	0
T65	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	858	0	0
T6	25051	6	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	21	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	6	0	0
T65	0	9	0	0
T142	0	19	0	0
T261	0	14	0	0
T262	0	20	0	0
T263	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	858	0	0
T6	25051	6	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	21	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	6	0	0
T65	0	9	0	0
T142	0	19	0	0
T261	0	14	0	0
T262	0	20	0	0
T263	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	74976	0	0
T6	25051	301	0	0
T7	9559	127	0	0
T8	6469	0	0	0
T10	0	1482	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	273	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	182	0	0
T65	0	1580	0	0
T142	0	6601	0	0
T261	0	656	0	0
T262	0	2077	0	0
T263	0	2362	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	760	0	0
T6	25051	6	0	0
T7	9559	5	0	0
T8	6469	0	0	0
T10	0	21	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T48	501	0	0	0
T49	415	0	0	0
T50	421	0	0	0
T51	1391	0	0	0
T64	0	6	0	0
T65	0	3	0	0
T142	0	11	0	0
T261	0	14	0	0
T262	0	17	0	0
T263	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T3,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T21
0	1	Covered	T81,T84,T135
1	0	Covered	T21,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T21
0	1	Covered	T2,T3,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T21
1	-	Covered	T2,T3,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T21
DetectSt	168	Covered	T2,T3,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T21
DebounceSt->IdleSt	163	Covered	T21,T8,T11
DetectSt->IdleSt	186	Covered	T21,T81,T32
DetectSt->StableSt	191	Covered	T2,T3,T21
IdleSt->DebounceSt	148	Covered	T2,T3,T21
StableSt->IdleSt	206	Covered	T2,T3,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T21
0	1	Covered	T2,T3,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T11,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T21
DetectSt	-	-	-	-	1	-	-	Covered	T21,T81,T32
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T21
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T21
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T21
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9022276	931	0	0
CntIncr_A	9022276	53582	0	0
CntNoWrap_A	9022276	8367012	0	0
DetectStDropOut_A	9022276	89	0	0
DetectedOut_A	9022276	16577	0	0
DetectedPulseOut_A	9022276	347	0	0
DisabledIdleSt_A	9022276	7962847	0	0
DisabledNoDetection_A	9022276	7964535	0	0
EnterDebounceSt_A	9022276	493	0	0
EnterDetectSt_A	9022276	440	0	0
EnterStableSt_A	9022276	347	0	0
PulseIsPulse_A	9022276	347	0	0
StayInStableSt	9022276	16209	0	0
gen_high_level_sva.HighLevelEvent_A	9022276	8370344	0	0
gen_not_sticky_sva.StableStDropOut_A	9022276	322	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	931	0	0
T2	8651	12	0	0
T3	8682	4	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	27	0	0
T10	0	4	0	0
T11	0	11	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	7	0	0
T29	0	6	0	0
T65	0	12	0	0
T81	0	11	0	0
T262	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	53582	0	0
T2	8651	444	0	0
T3	8682	152	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	952	0	0
T10	0	122	0	0
T11	0	1328	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	132	0	0
T29	0	183	0	0
T65	0	168	0	0
T81	0	302	0	0
T262	0	207	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8367012	0	0
T1	916	515	0	0
T2	8651	8230	0	0
T3	8682	8256	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24600	0	0
T7	9559	9148	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	89	0	0
T54	767	0	0	0
T55	174567	0	0	0
T58	492	0	0	0
T81	4537	5	0	0
T84	0	1	0	0
T88	0	9	0	0
T93	0	2	0	0
T103	26456	0	0	0
T135	0	4	0	0
T251	0	1	0	0
T262	14527	0	0	0
T263	18565	0	0	0
T275	0	6	0	0
T276	0	7	0	0
T277	0	2	0	0
T278	0	2	0	0
T279	431	0	0	0
T280	506	0	0	0
T281	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	16577	0	0
T2	8651	58	0	0
T3	8682	16	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	822	0	0
T10	0	140	0	0
T11	0	197	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	80	0	0
T29	0	174	0	0
T65	0	403	0	0
T103	0	323	0	0
T262	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	347	0	0
T2	8651	6	0	0
T3	8682	2	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	13	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T29	0	3	0	0
T65	0	6	0	0
T103	0	5	0	0
T262	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7962847	0	0
T1	916	515	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34173	0	0
T5	502	101	0	0
T6	25051	24293	0	0
T7	9559	9016	0	0
T13	522	121	0	0
T14	495	94	0	0
T15	2649	244	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	7964535	0	0
T1	916	516	0	0
T2	8651	6043	0	0
T3	8682	6045	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24301	0	0
T7	9559	9018	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	493	0	0
T2	8651	6	0	0
T3	8682	2	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	14	0	0
T10	0	2	0	0
T11	0	6	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	5	0	0
T29	0	3	0	0
T65	0	6	0	0
T81	0	6	0	0
T262	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	440	0	0
T2	8651	6	0	0
T3	8682	2	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	13	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	2	0	0
T29	0	3	0	0
T65	0	6	0	0
T81	0	5	0	0
T262	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	347	0	0
T2	8651	6	0	0
T3	8682	2	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	13	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T29	0	3	0	0
T65	0	6	0	0
T103	0	5	0	0
T262	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	347	0	0
T2	8651	6	0	0
T3	8682	2	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	13	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	1	0	0
T29	0	3	0	0
T65	0	6	0	0
T103	0	5	0	0
T262	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	16209	0	0
T2	8651	52	0	0
T3	8682	13	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	809	0	0
T10	0	138	0	0
T11	0	192	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	79	0	0
T29	0	171	0	0
T65	0	397	0	0
T103	0	318	0	0
T262	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	8370344	0	0
T1	916	516	0	0
T2	8651	8245	0	0
T3	8682	8263	0	0
T4	35375	34175	0	0
T5	502	102	0	0
T6	25051	24608	0	0
T7	9559	9150	0	0
T13	522	122	0	0
T14	495	95	0	0
T15	2649	249	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9022276	322	0	0
T2	8651	6	0	0
T3	8682	1	0	0
T6	25051	0	0	0
T7	9559	0	0	0
T8	0	13	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	495	0	0	0
T15	2649	0	0	0
T16	739	0	0	0
T17	7208	0	0	0
T21	7034	0	0	0
T29	0	3	0	0
T65	0	6	0	0
T103	0	5	0	0
T105	0	6	0	0
T263	0	2	0	0