Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1172604666	9392	0	0
auto_block_debounce_ctl_rd_A	1172604666	1735	0	0
auto_block_out_ctl_rd_A	1172604666	2361	0	0
com_det_ctl_0_rd_A	1172604666	3722	0	0
com_det_ctl_1_rd_A	1172604666	3772	0	0
com_det_ctl_2_rd_A	1172604666	3821	0	0
com_det_ctl_3_rd_A	1172604666	3689	0	0
com_out_ctl_0_rd_A	1172604666	4385	0	0
com_out_ctl_1_rd_A	1172604666	4380	0	0
com_out_ctl_2_rd_A	1172604666	4479	0	0
com_out_ctl_3_rd_A	1172604666	4216	0	0
com_pre_det_ctl_0_rd_A	1172604666	1222	0	0
com_pre_det_ctl_1_rd_A	1172604666	1267	0	0
com_pre_det_ctl_2_rd_A	1172604666	1335	0	0
com_pre_det_ctl_3_rd_A	1172604666	1408	0	0
com_pre_sel_ctl_0_rd_A	1172604666	4640	0	0
com_pre_sel_ctl_1_rd_A	1172604666	4586	0	0
com_pre_sel_ctl_2_rd_A	1172604666	4269	0	0
com_pre_sel_ctl_3_rd_A	1172604666	4400	0	0
com_sel_ctl_0_rd_A	1172604666	4321	0	0
com_sel_ctl_1_rd_A	1172604666	4541	0	0
com_sel_ctl_2_rd_A	1172604666	4716	0	0
com_sel_ctl_3_rd_A	1172604666	4477	0	0
ec_rst_ctl_rd_A	1172604666	2386	0	0
intr_enable_rd_A	1172604666	2280	0	0
key_intr_ctl_rd_A	1172604666	3949	0	0
key_intr_debounce_ctl_rd_A	1172604666	1287	0	0
key_invert_ctl_rd_A	1172604666	5865	0	0
pin_allowed_ctl_rd_A	1172604666	5925	0	0
pin_out_ctl_rd_A	1172604666	4806	0	0
pin_out_value_rd_A	1172604666	4268	0	0
regwen_rd_A	1172604666	1822	0	0
ulp_ac_debounce_ctl_rd_A	1172604666	1447	0	0
ulp_ctl_rd_A	1172604666	1410	0	0
ulp_lid_debounce_ctl_rd_A	1172604666	1490	0	0
ulp_pwrb_debounce_ctl_rd_A	1172604666	1449	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	9392	0	0
T12	243801	0	0	0
T22	116449	0	0	0
T23	0	9	0	0
T26	60950	0	0	0
T38	0	9	0	0
T43	129062	0	0	0
T45	0	2	0	0
T60	164473	13	0	0
T61	206269	0	0	0
T62	63213	0	0	0
T64	130720	0	0	0
T84	0	6	0	0
T107	0	8	0	0
T126	117144	0	0	0
T127	202710	0	0	0
T155	0	6	0	0
T158	0	4	0	0
T292	0	15	0	0
T309	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1735	0	0
T31	120027	0	0	0
T34	297248	0	0	0
T44	78549	15	0	0
T69	0	2	0	0
T82	250839	0	0	0
T135	0	14	0	0
T149	0	7	0	0
T158	0	8	0	0
T210	0	1	0	0
T272	189569	0	0	0
T304	111910	0	0	0
T305	57377	0	0	0
T306	103603	0	0	0
T307	64343	0	0	0
T308	217139	0	0	0
T309	0	28	0	0
T310	0	11	0	0
T311	0	10	0	0
T312	0	22	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	2361	0	0
T31	120027	0	0	0
T34	297248	0	0	0
T44	78549	10	0	0
T69	0	1	0	0
T82	250839	0	0	0
T135	0	23	0	0
T158	0	1	0	0
T210	0	9	0	0
T245	0	14	0	0
T272	189569	0	0	0
T304	111910	0	0	0
T305	57377	0	0	0
T306	103603	0	0	0
T307	64343	0	0	0
T308	217139	0	0	0
T309	0	20	0	0
T310	0	5	0	0
T311	0	2	0	0
T312	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	3722	0	0
T3	164953	45	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	26	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	23	0	0
T48	248297	0	0	0
T83	0	33	0	0
T135	0	129	0	0
T145	0	67	0	0
T269	0	84	0	0
T309	0	14	0	0
T313	0	60	0	0
T314	0	66	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	3772	0	0
T3	164953	62	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	55	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	39	0	0
T48	248297	0	0	0
T83	0	38	0	0
T135	0	121	0	0
T145	0	82	0	0
T158	0	8	0	0
T309	0	32	0	0
T313	0	81	0	0
T314	0	87	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	3821	0	0
T3	164953	39	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	41	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	32	0	0
T48	248297	0	0	0
T83	0	41	0	0
T135	0	144	0	0
T145	0	69	0	0
T158	0	9	0	0
T309	0	20	0	0
T313	0	70	0	0
T314	0	85	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	3689	0	0
T3	164953	26	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	62	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	37	0	0
T48	248297	0	0	0
T83	0	30	0	0
T135	0	135	0	0
T145	0	44	0	0
T158	0	8	0	0
T309	0	10	0	0
T313	0	56	0	0
T314	0	57	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4385	0	0
T3	164953	37	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	71	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	40	0	0
T48	248297	0	0	0
T83	0	55	0	0
T135	0	141	0	0
T145	0	73	0	0
T158	0	10	0	0
T309	0	14	0	0
T313	0	66	0	0
T314	0	81	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4380	0	0
T3	164953	32	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	60	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	39	0	0
T48	248297	0	0	0
T83	0	35	0	0
T135	0	161	0	0
T145	0	76	0	0
T158	0	27	0	0
T309	0	21	0	0
T313	0	101	0	0
T314	0	42	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4479	0	0
T3	164953	32	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	72	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	36	0	0
T48	248297	0	0	0
T83	0	64	0	0
T135	0	116	0	0
T145	0	55	0	0
T158	0	11	0	0
T309	0	3	0	0
T313	0	74	0	0
T314	0	74	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4216	0	0
T3	164953	33	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	24	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	33	0	0
T48	248297	0	0	0
T83	0	54	0	0
T135	0	156	0	0
T145	0	76	0	0
T158	0	7	0	0
T309	0	12	0	0
T313	0	75	0	0
T314	0	76	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1222	0	0
T83	172767	0	0	0
T132	0	12	0	0
T135	0	19	0	0
T152	0	6	0	0
T158	173522	5	0	0
T159	233448	0	0	0
T169	0	14	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	8	0	0
T312	0	11	0	0
T315	0	20	0	0
T316	0	17	0	0
T317	0	6	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1267	0	0
T83	172767	0	0	0
T132	0	33	0	0
T135	0	36	0	0
T149	0	6	0	0
T152	0	9	0	0
T158	173522	6	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	9	0	0
T312	0	28	0	0
T315	0	23	0	0
T316	0	37	0	0
T317	0	3	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1335	0	0
T83	172767	0	0	0
T132	0	18	0	0
T135	0	18	0	0
T152	0	12	0	0
T158	173522	15	0	0
T159	233448	0	0	0
T169	0	33	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	3	0	0
T312	0	15	0	0
T315	0	23	0	0
T316	0	8	0	0
T317	0	7	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1408	0	0
T83	172767	0	0	0
T132	0	12	0	0
T135	0	23	0	0
T149	0	8	0	0
T152	0	3	0	0
T158	173522	8	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	4	0	0
T312	0	16	0	0
T315	0	28	0	0
T316	0	31	0	0
T317	0	6	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4640	0	0
T3	164953	24	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	62	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	34	0	0
T48	248297	0	0	0
T83	0	49	0	0
T135	0	153	0	0
T145	0	65	0	0
T158	0	6	0	0
T309	0	19	0	0
T313	0	77	0	0
T314	0	61	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4586	0	0
T3	164953	33	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	38	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	31	0	0
T48	248297	0	0	0
T83	0	40	0	0
T135	0	107	0	0
T145	0	59	0	0
T158	0	4	0	0
T309	0	6	0	0
T313	0	65	0	0
T314	0	65	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4269	0	0
T3	164953	27	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	37	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	50	0	0
T48	248297	0	0	0
T83	0	32	0	0
T135	0	148	0	0
T145	0	72	0	0
T158	0	6	0	0
T309	0	18	0	0
T313	0	85	0	0
T314	0	60	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4400	0	0
T3	164953	14	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	48	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	24	0	0
T48	248297	0	0	0
T83	0	30	0	0
T135	0	127	0	0
T145	0	70	0	0
T269	0	75	0	0
T309	0	11	0	0
T313	0	56	0	0
T314	0	82	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4321	0	0
T3	164953	45	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	41	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	26	0	0
T48	248297	0	0	0
T83	0	38	0	0
T135	0	145	0	0
T145	0	77	0	0
T269	0	71	0	0
T309	0	14	0	0
T313	0	68	0	0
T314	0	51	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4541	0	0
T3	164953	35	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	35	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	43	0	0
T48	248297	0	0	0
T83	0	50	0	0
T135	0	169	0	0
T145	0	70	0	0
T158	0	4	0	0
T309	0	46	0	0
T313	0	78	0	0
T314	0	47	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4716	0	0
T3	164953	65	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	60	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	40	0	0
T48	248297	0	0	0
T83	0	61	0	0
T135	0	153	0	0
T145	0	80	0	0
T158	0	12	0	0
T309	0	11	0	0
T313	0	57	0	0
T314	0	60	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4477	0	0
T3	164953	47	0	0
T6	125255	0	0	0
T7	114701	0	0	0
T10	0	53	0	0
T13	258736	0	0	0
T14	39646	0	0	0
T15	121872	0	0	0
T16	66620	0	0	0
T17	864989	0	0	0
T21	305332	0	0	0
T27	0	26	0	0
T48	248297	0	0	0
T83	0	43	0	0
T135	0	135	0	0
T145	0	58	0	0
T158	0	14	0	0
T309	0	27	0	0
T313	0	70	0	0
T314	0	55	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	2386	0	0
T10	936582	6	0	0
T11	480990	0	0	0
T12	243801	0	0	0
T22	116449	0	0	0
T26	60950	0	0	0
T27	0	8	0	0
T43	129062	0	0	0
T60	164473	0	0	0
T61	206269	0	0	0
T83	0	20	0	0
T126	117144	0	0	0
T135	0	102	0	0
T145	0	26	0	0
T158	0	19	0	0
T176	58887	0	0	0
T187	0	5	0	0
T309	0	14	0	0
T313	0	47	0	0
T321	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	2280	0	0
T23	244499	0	0	0
T27	114940	0	0	0
T28	658203	0	0	0
T57	59599	0	0	0
T65	790464	0	0	0
T69	0	15	0	0
T80	548668	0	0	0
T81	567222	0	0	0
T135	0	80	0	0
T149	0	18	0	0
T152	0	50	0	0
T158	0	10	0	0
T187	321853	19	0	0
T188	101834	0	0	0
T261	140140	0	0	0
T309	0	26	0	0
T312	0	22	0	0
T315	0	29	0	0
T322	0	12	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	3949	0	0
T39	0	3	0	0
T69	0	2	0	0
T83	172767	0	0	0
T135	0	20	0	0
T149	0	12	0	0
T158	173522	3	0	0
T159	233448	0	0	0
T173	0	4	0	0
T210	0	5	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	5	0	0
T312	0	11	0	0
T315	0	9	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1287	0	0
T83	172767	0	0	0
T132	0	13	0	0
T135	0	15	0	0
T149	0	16	0	0
T152	0	11	0	0
T158	173522	9	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	7	0	0
T312	0	6	0	0
T315	0	28	0	0
T316	0	23	0	0
T317	0	8	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	5865	0	0
T23	244499	0	0	0
T28	658203	53	0	0
T57	59599	0	0	0
T58	0	85	0	0
T59	0	45	0	0
T65	790464	0	0	0
T66	0	21	0	0
T80	548668	0	0	0
T81	567222	0	0	0
T157	0	56	0	0
T158	0	75	0	0
T236	0	69	0	0
T261	140140	0	0	0
T262	181586	0	0	0
T279	21570	0	0	0
T280	53219	0	0	0
T305	0	73	0	0
T307	0	60	0	0
T309	0	238	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	5925	0	0
T83	172767	0	0	0
T110	0	57	0	0
T135	0	157	0	0
T136	0	59	0	0
T149	0	34	0	0
T158	173522	10	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	59	0	0
T312	0	101	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0
T323	0	70	0	0
T324	0	45	0	0
T325	0	83	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4806	0	0
T83	172767	0	0	0
T110	0	61	0	0
T135	0	161	0	0
T136	0	65	0	0
T149	0	53	0	0
T158	173522	16	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	59	0	0
T312	0	134	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0
T323	0	70	0	0
T324	0	45	0	0
T325	0	63	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	4268	0	0
T83	172767	0	0	0
T110	0	77	0	0
T135	0	138	0	0
T136	0	59	0	0
T149	0	41	0	0
T158	173522	8	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	26	0	0
T312	0	70	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0
T323	0	79	0	0
T324	0	31	0	0
T325	0	43	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1822	0	0
T83	172767	0	0	0
T132	0	12	0	0
T135	0	22	0	0
T149	0	6	0	0
T152	0	12	0	0
T158	173522	2	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	9	0	0
T312	0	17	0	0
T315	0	18	0	0
T316	0	17	0	0
T317	0	6	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1447	0	0
T66	0	4	0	0
T83	172767	0	0	0
T108	0	11	0	0
T110	0	10	0	0
T121	0	4	0	0
T135	0	30	0	0
T149	0	13	0	0
T158	173522	3	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	19	0	0
T312	0	16	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0
T326	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1410	0	0
T83	172767	0	0	0
T108	0	6	0	0
T110	0	1	0	0
T135	0	32	0	0
T149	0	9	0	0
T152	0	19	0	0
T158	173522	6	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	38	0	0
T312	0	15	0	0
T315	0	18	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0
T326	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1490	0	0
T66	0	7	0	0
T83	172767	0	0	0
T108	0	12	0	0
T110	0	12	0	0
T121	0	1	0	0
T135	0	20	0	0
T152	0	14	0	0
T158	173522	7	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	15	0	0
T312	0	10	0	0
T315	0	19	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172604666	1449	0	0
T83	172767	0	0	0
T108	0	11	0	0
T110	0	6	0	0
T135	0	26	0	0
T149	0	3	0	0
T152	0	17	0	0
T158	173522	16	0	0
T159	233448	0	0	0
T216	115254	0	0	0
T217	204521	0	0	0
T266	376575	0	0	0
T284	217870	0	0	0
T309	0	18	0	0
T312	0	17	0	0
T315	0	13	0	0
T318	117468	0	0	0
T319	95422	0	0	0
T320	50637	0	0	0
T326	0	6	0	0