Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T21,T22
1	1	Covered	T4,T1,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	219696	0	0
SrcPulseCheck_M	2147483647	222269	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	219696
T2	7907449	48
T3	2595843	48
T4	34424	0
T5	123236	0
T6	3431987	136
T7	2848421	34
T8	9677811	16
T9	229678	0
T10	0	34
T11	0	192
T13	3888348	0
T14	601620	0
T15	1865166	4
T16	1616616	14
T17	20932728	17
T21	7809150	159
T23	0	12
T32	0	6
T33	0	14
T38	0	26
T42	455078	34
T43	0	1
T44	0	16
T45	0	16
T46	0	14
T47	0	18
T48	2736778	0
T49	1375121	0
T50	2323530	0
T51	1928806	0
T52	784983	0
T53	680442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	222269
T2	7397011	48
T3	2439572	48
T4	35375	0
T5	502	0
T6	3331783	136
T7	2743279	34
T8	9677811	16
T9	229678	0
T10	0	34
T11	0	192
T13	3630134	0
T14	562469	0
T15	1745943	4
T16	1616616	14
T17	20932728	17
T21	7809150	159
T23	0	12
T32	0	6
T33	0	14
T38	0	26
T42	455078	34
T43	0	1
T44	0	16
T45	0	16
T46	0	14
T47	0	18
T48	2736778	0
T49	1375121	0
T50	2323530	0
T51	1928806	0
T52	784983	0
T53	680442	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T25,T18,T289

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T25,T18,T289
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1760	0	0
SrcPulseCheck_M	1172604666	1833	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1760
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	1
T42	0	2
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1833
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	1
T42	0	2
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T25,T18,T289

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T25,T18,T289
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1823	0	0
SrcPulseCheck_M	9253749	1823	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1823
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	1
T42	0	2
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1823
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	1
T42	0	2
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T4,T1,T21
1	1	Covered	T1,T22,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T1,T22,T26
1	1	Covered	T4,T1,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	807	0	0
SrcPulseCheck_M	1172604666	881	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	807
T1	916	2
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	881
T1	58238	2
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T4,T1,T21
1	1	Covered	T1,T22,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T1,T22,T26
1	1	Covered	T4,T1,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	871	0	0
SrcPulseCheck_M	9253749	871	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	871
T1	58238	2
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	871
T1	916	2
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T4,T1,T21
1	1	Covered	T1,T22,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T1,T22,T26
1	1	Covered	T4,T1,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	827	0	0
SrcPulseCheck_M	1172604666	899	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	827
T1	916	2
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	899
T1	58238	2
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T4,T1,T21
1	1	Covered	T1,T22,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T1,T22,T26
1	1	Covered	T4,T1,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	890	0	0
SrcPulseCheck_M	9253749	890	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	890
T1	58238	2
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	890
T1	916	2
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T4,T1,T21
1	1	Covered	T1,T22,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T1,T22,T26
1	1	Covered	T4,T1,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	805	0	0
SrcPulseCheck_M	1172604666	879	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	805
T1	916	2
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	879
T1	58238	2
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T4,T1,T21
1	1	Covered	T1,T22,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T21
1	0	Covered	T1,T22,T26
1	1	Covered	T4,T1,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	869	0	0
SrcPulseCheck_M	9253749	869	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	869
T1	58238	2
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	869
T1	916	2
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T21	0	1
T22	0	2
T23	0	2
T26	0	2
T38	0	1
T54	0	1
T55	0	2
T56	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T21,T22
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T21,T22
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	738	0	0
SrcPulseCheck_M	1172604666	812	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	738
T1	916	2
T2	8651	0
T3	8682	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	0
T21	0	3
T22	0	2
T26	0	4
T32	0	4
T38	0	2
T54	0	2
T55	0	4
T56	0	2
T66	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	812
T1	58238	2
T2	519089	0
T3	164953	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	0
T21	0	4
T22	0	2
T26	0	4
T32	0	4
T38	0	2
T54	0	2
T55	0	4
T56	0	2
T66	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T21,T22
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T21,T22
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	803	0	0
SrcPulseCheck_M	9253749	803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	803
T1	58238	2
T2	519089	0
T3	164953	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	0
T21	0	4
T22	0	2
T26	0	4
T32	0	4
T38	0	2
T54	0	2
T55	0	4
T56	0	2
T66	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	803
T1	916	2
T2	8651	0
T3	8682	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	0
T21	0	4
T22	0	2
T26	0	4
T32	0	4
T38	0	2
T54	0	2
T55	0	4
T56	0	2
T66	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1093	0	0
SrcPulseCheck_M	1172604666	1164	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1093
T1	916	1
T2	8651	6
T3	8682	6
T6	25051	7
T7	9559	1
T8	0	13
T10	0	1
T11	0	13
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	0
T22	0	1
T26	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1164
T1	58238	1
T2	519089	6
T3	164953	6
T6	125255	7
T7	114701	1
T8	0	13
T10	0	1
T11	0	13
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	0
T22	0	1
T26	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T14,T15
1	0	Covered	T4,T14,T15
1	1	Covered	T4,T14,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T14,T15
1	0	Covered	T4,T14,T15
1	1	Covered	T4,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	2779	0	0
SrcPulseCheck_M	1172604666	2854	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	2779
T1	916	0
T2	8651	0
T3	8682	0
T4	35375	20
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	20
T15	2649	20
T23	0	40
T28	0	20
T38	0	20
T51	0	40
T57	0	20
T58	0	20
T59	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	2854
T1	58238	0
T2	519089	0
T3	164953	0
T4	34424	20
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	20
T15	121872	20
T23	0	40
T28	0	20
T38	0	20
T51	0	40
T57	0	20
T58	0	20
T59	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T14,T15
1	0	Covered	T4,T14,T15
1	1	Covered	T4,T14,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T14,T15
1	0	Covered	T4,T14,T15
1	1	Covered	T4,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	2845	0	0
SrcPulseCheck_M	9253749	2845	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	2845
T1	58238	0
T2	519089	0
T3	164953	0
T4	34424	20
T5	123236	0
T6	125255	0
T7	114701	0
T13	258736	0
T14	39646	20
T15	121872	20
T23	0	40
T28	0	20
T38	0	20
T51	0	40
T57	0	20
T58	0	20
T59	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	2845
T1	916	0
T2	8651	0
T3	8682	0
T4	35375	20
T5	502	0
T6	25051	0
T7	9559	0
T13	522	0
T14	495	20
T15	2649	20
T23	0	40
T28	0	20
T38	0	20
T51	0	40
T57	0	20
T58	0	20
T59	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T13
1	1	Covered	T5,T13,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T13,T15
1	1	Covered	T4,T5,T13

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	6318	0	0
SrcPulseCheck_M	1172604666	6400	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	6318
T1	916	0
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	20
T6	25051	0
T7	9559	0
T11	0	20
T13	522	20
T14	495	1
T15	2649	21
T48	0	20
T51	0	2
T52	0	20
T60	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	6400
T1	58238	0
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	20
T6	125255	0
T7	114701	0
T11	0	20
T13	258736	20
T14	39646	1
T15	121872	21
T48	0	20
T51	0	2
T52	0	20
T60	0	40

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T13
1	1	Covered	T5,T13,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T13,T15
1	1	Covered	T4,T5,T13

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	6386	0	0
SrcPulseCheck_M	9253749	6386	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	6386
T1	58238	0
T2	519089	0
T3	164953	0
T4	34424	1
T5	123236	20
T6	125255	0
T7	114701	0
T11	0	20
T13	258736	20
T14	39646	1
T15	121872	21
T48	0	20
T51	0	2
T52	0	20
T60	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	6386
T1	916	0
T2	8651	0
T3	8682	0
T4	35375	1
T5	502	20
T6	25051	0
T7	9559	0
T11	0	20
T13	522	20
T14	495	1
T15	2649	21
T48	0	20
T51	0	2
T52	0	20
T60	0	40

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T2
1	1	Covered	T5,T13,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T5,T13,T15
1	1	Covered	T4,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7526	0	0
SrcPulseCheck_M	1172604666	7603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7526
T1	916	0
T2	8651	3
T3	8682	3
T4	35375	1
T5	502	20
T6	25051	8
T7	9559	2
T13	522	20
T14	495	1
T15	2649	22
T17	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7603
T1	58238	0
T2	519089	3
T3	164953	3
T4	34424	1
T5	123236	20
T6	125255	8
T7	114701	2
T13	258736	20
T14	39646	1
T15	121872	22
T17	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T2
1	1	Covered	T5,T13,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T5,T13,T15
1	1	Covered	T4,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7589	0	0
SrcPulseCheck_M	9253749	7589	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7589
T1	58238	0
T2	519089	3
T3	164953	3
T4	34424	1
T5	123236	20
T6	125255	8
T7	114701	2
T13	258736	20
T14	39646	1
T15	121872	22
T17	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7589
T1	916	0
T2	8651	3
T3	8682	3
T4	35375	1
T5	502	20
T6	25051	8
T7	9559	2
T13	522	20
T14	495	1
T15	2649	22
T17	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T15
1	0	Covered	T5,T13,T15
1	1	Covered	T5,T13,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T15
1	0	Covered	T5,T13,T15
1	1	Covered	T5,T13,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	6175	0	0
SrcPulseCheck_M	1172604666	6248	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	6175
T1	916	0
T2	8651	0
T3	8682	0
T5	502	20
T6	25051	0
T7	9559	0
T11	0	20
T13	522	20
T14	495	0
T15	2649	20
T16	739	0
T48	0	20
T52	0	20
T60	0	40
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	6248
T1	58238	0
T2	519089	0
T3	164953	0
T5	123236	20
T6	125255	0
T7	114701	0
T11	0	20
T13	258736	20
T14	39646	0
T15	121872	20
T16	66620	0
T48	0	20
T52	0	20
T60	0	40
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T15
1	0	Covered	T5,T13,T15
1	1	Covered	T5,T13,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T15
1	0	Covered	T5,T13,T15
1	1	Covered	T5,T13,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	6237	0	0
SrcPulseCheck_M	9253749	6237	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	6237
T1	58238	0
T2	519089	0
T3	164953	0
T5	123236	20
T6	125255	0
T7	114701	0
T11	0	20
T13	258736	20
T14	39646	0
T15	121872	20
T16	66620	0
T48	0	20
T52	0	20
T60	0	40
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	6237
T1	916	0
T2	8651	0
T3	8682	0
T5	502	20
T6	25051	0
T7	9559	0
T11	0	20
T13	522	20
T14	495	0
T15	2649	20
T16	739	0
T48	0	20
T52	0	20
T60	0	40
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T21,T9,T12
1	0	Covered	T21,T9,T12
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T21,T9,T12
1	0	Covered	T21,T32,T25
1	1	Covered	T21,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	790	0	0
SrcPulseCheck_M	1172604666	865	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	790
T8	6469	0
T9	482	1
T12	0	1
T21	7034	28
T30	0	1
T31	0	1
T32	0	28
T33	0	1
T34	0	1
T35	0	1
T38	0	1
T42	9287	0
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T52	522	0
T53	922	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	865
T8	873332	0
T9	229196	1
T12	0	1
T21	305332	28
T30	0	1
T31	0	1
T32	0	28
T33	0	1
T34	0	1
T35	0	1
T38	0	1
T42	445791	0
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T52	261139	0
T53	225892	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T21,T9,T12
1	0	Covered	T21,T9,T12
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T21,T9,T12
1	0	Covered	T21,T32,T25
1	1	Covered	T21,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	857	0	0
SrcPulseCheck_M	9253749	857	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	857
T8	873332	0
T9	229196	1
T12	0	1
T21	305332	28
T30	0	1
T31	0	1
T32	0	28
T33	0	1
T34	0	1
T35	0	1
T38	0	1
T42	445791	0
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T52	261139	0
T53	225892	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	857
T8	6469	0
T9	482	1
T12	0	1
T21	7034	28
T30	0	1
T31	0	1
T32	0	28
T33	0	1
T34	0	1
T35	0	1
T38	0	1
T42	9287	0
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T52	522	0
T53	922	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1794	0	0
SrcPulseCheck_M	1172604666	1875	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1794
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T9	0	1
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	2
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1875
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T9	0	1
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	2
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1864	0	0
SrcPulseCheck_M	9253749	1864	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1864
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T9	0	1
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	2
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1864
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T9	0	1
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	2
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T21,T23
1	1	Covered	T16,T21,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T21,T23
1	1	Covered	T16,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1137	0	0
SrcPulseCheck_M	1172604666	1213	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1137
T8	6469	0
T16	739	4
T17	7208	0
T21	7034	2
T23	0	3
T32	0	2
T33	0	5
T38	0	8
T44	0	5
T45	0	5
T46	0	4
T47	0	6
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T52	522	0
T53	922	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1213
T8	873332	0
T16	66620	4
T17	864989	0
T21	305332	2
T23	0	3
T32	0	2
T33	0	5
T38	0	8
T44	0	5
T45	0	5
T46	0	4
T47	0	6
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T52	261139	0
T53	225892	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T21,T23
1	1	Covered	T16,T21,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T21,T23
1	1	Covered	T16,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1201	0	0
SrcPulseCheck_M	9253749	1201	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1201
T8	873332	0
T16	66620	4
T17	864989	0
T21	305332	2
T23	0	3
T32	0	2
T33	0	5
T38	0	8
T44	0	5
T45	0	5
T46	0	4
T47	0	6
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T52	261139	0
T53	225892	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1201
T8	6469	0
T16	739	4
T17	7208	0
T21	7034	2
T23	0	3
T32	0	2
T33	0	5
T38	0	8
T44	0	5
T45	0	5
T46	0	4
T47	0	6
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T52	522	0
T53	922	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T21,T23
1	1	Covered	T16,T23,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T23,T38
1	1	Covered	T16,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	951	0	0
SrcPulseCheck_M	1172604666	1026	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	951
T8	6469	0
T16	739	3
T17	7208	0
T21	7034	1
T23	0	3
T32	0	1
T33	0	2
T38	0	5
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T52	522	0
T53	922	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1026
T8	873332	0
T16	66620	3
T17	864989	0
T21	305332	1
T23	0	3
T32	0	1
T33	0	2
T38	0	5
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T52	261139	0
T53	225892	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T21,T23
1	1	Covered	T16,T23,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T21,T23
1	0	Covered	T16,T23,T38
1	1	Covered	T16,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1016	0	0
SrcPulseCheck_M	9253749	1016	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1016
T8	873332	0
T16	66620	3
T17	864989	0
T21	305332	1
T23	0	3
T32	0	1
T33	0	2
T38	0	5
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T52	261139	0
T53	225892	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1016
T8	6469	0
T16	739	3
T17	7208	0
T21	7034	1
T23	0	3
T32	0	1
T33	0	2
T38	0	5
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T52	522	0
T53	922	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	6941	0	0
SrcPulseCheck_M	1172604666	7018	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	6941
T6	25051	77
T7	9559	68
T8	6469	0
T10	0	72
T16	739	0
T17	7208	75
T21	7034	11
T27	0	58
T42	0	75
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	75
T65	0	65

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7018
T6	125255	77
T7	114701	68
T8	873332	0
T10	0	72
T16	66620	0
T17	864989	75
T21	305332	11
T27	0	58
T42	0	75
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	75
T65	0	65

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7008	0	0
SrcPulseCheck_M	9253749	7008	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7008
T6	125255	77
T7	114701	68
T8	873332	0
T10	0	72
T16	66620	0
T17	864989	75
T21	305332	11
T27	0	58
T42	0	75
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	75
T65	0	65

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7008
T6	25051	77
T7	9559	68
T8	6469	0
T10	0	72
T16	739	0
T17	7208	75
T21	7034	11
T27	0	58
T42	0	75
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	75
T65	0	65

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7005	0	0
SrcPulseCheck_M	1172604666	7083	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7005
T6	25051	64
T7	9559	59
T8	6469	0
T10	0	70
T16	739	0
T17	7208	75
T21	7034	11
T27	0	71
T42	0	52
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	75
T65	0	69

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7083
T6	125255	64
T7	114701	59
T8	873332	0
T10	0	70
T16	66620	0
T17	864989	75
T21	305332	11
T27	0	71
T42	0	52
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	75
T65	0	69

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7072	0	0
SrcPulseCheck_M	9253749	7072	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7072
T6	125255	64
T7	114701	59
T8	873332	0
T10	0	70
T16	66620	0
T17	864989	75
T21	305332	11
T27	0	71
T42	0	52
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	75
T65	0	69

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7072
T6	25051	64
T7	9559	59
T8	6469	0
T10	0	70
T16	739	0
T17	7208	75
T21	7034	11
T27	0	71
T42	0	52
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	75
T65	0	69

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7000	0	0
SrcPulseCheck_M	1172604666	7076	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7000
T6	25051	71
T7	9559	58
T8	6469	0
T10	0	84
T16	739	0
T17	7208	51
T21	7034	11
T27	0	58
T42	0	75
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	62
T65	0	69

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7076
T6	125255	71
T7	114701	58
T8	873332	0
T10	0	84
T16	66620	0
T17	864989	51
T21	305332	11
T27	0	58
T42	0	75
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	62
T65	0	69

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7063	0	0
SrcPulseCheck_M	9253749	7063	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7063
T6	125255	71
T7	114701	58
T8	873332	0
T10	0	84
T16	66620	0
T17	864989	51
T21	305332	11
T27	0	58
T42	0	75
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	62
T65	0	69

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7063
T6	25051	71
T7	9559	58
T8	6469	0
T10	0	84
T16	739	0
T17	7208	51
T21	7034	11
T27	0	58
T42	0	75
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	62
T65	0	69

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7060	0	0
SrcPulseCheck_M	1172604666	7138	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7060
T6	25051	82
T7	9559	68
T8	6469	0
T10	0	63
T16	739	0
T17	7208	75
T21	7034	11
T27	0	83
T42	0	75
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	86
T65	0	60

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7138
T6	125255	82
T7	114701	68
T8	873332	0
T10	0	63
T16	66620	0
T17	864989	75
T21	305332	11
T27	0	83
T42	0	75
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	86
T65	0	60

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7128	0	0
SrcPulseCheck_M	9253749	7128	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7128
T6	125255	82
T7	114701	68
T8	873332	0
T10	0	63
T16	66620	0
T17	864989	75
T21	305332	11
T27	0	83
T42	0	75
T43	0	51
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	86
T65	0	60

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7128
T6	25051	82
T7	9559	68
T8	6469	0
T10	0	63
T16	739	0
T17	7208	75
T21	7034	11
T27	0	83
T42	0	75
T43	0	51
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	86
T65	0	60

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	988	0	0
SrcPulseCheck_M	1172604666	1064	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	988
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1064
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1053	0	0
SrcPulseCheck_M	9253749	1053	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1053
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1053
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1010	0	0
SrcPulseCheck_M	1172604666	1086	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1010
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1086
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1077	0	0
SrcPulseCheck_M	9253749	1077	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1077
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1077
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	983	0	0
SrcPulseCheck_M	1172604666	1058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	983
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1058
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1048	0	0
SrcPulseCheck_M	9253749	1048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1048
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1048
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1019	0	0
SrcPulseCheck_M	1172604666	1095	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1019
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1095
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T6,T7,T17
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T7,T17
1	0	Covered	T21,T32,T25
1	1	Covered	T6,T7,T17

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1084	0	0
SrcPulseCheck_M	9253749	1084	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1084
T6	125255	8
T7	114701	2
T8	873332	0
T10	0	2
T16	66620	0
T17	864989	1
T21	305332	9
T27	0	2
T42	0	2
T43	0	1
T48	248297	0
T49	124596	0
T50	210809	0
T51	173955	0
T64	0	2
T65	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1084
T6	25051	8
T7	9559	2
T8	6469	0
T10	0	2
T16	739	0
T17	7208	1
T21	7034	9
T27	0	2
T42	0	2
T43	0	1
T48	501	0
T49	415	0
T50	421	0
T51	1391	0
T64	0	2
T65	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7667	0	0
SrcPulseCheck_M	1172604666	7743	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7667
T2	8651	3
T3	8682	3
T6	25051	77
T7	9559	68
T8	0	1
T10	0	72
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	75
T21	7034	11
T42	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7743
T2	519089	3
T3	164953	3
T6	125255	77
T7	114701	68
T8	0	1
T10	0	72
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	75
T21	305332	11
T42	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7732	0	0
SrcPulseCheck_M	9253749	7732	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7732
T2	519089	3
T3	164953	3
T6	125255	77
T7	114701	68
T8	0	1
T10	0	72
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	75
T21	305332	11
T42	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7732
T2	8651	3
T3	8682	3
T6	25051	77
T7	9559	68
T8	0	1
T10	0	72
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	75
T21	7034	11
T42	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7622	0	0
SrcPulseCheck_M	1172604666	7698	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7622
T2	8651	3
T3	8682	3
T6	25051	64
T7	9559	59
T8	0	1
T10	0	70
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	75
T21	7034	11
T42	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7698
T2	519089	3
T3	164953	3
T6	125255	64
T7	114701	59
T8	0	1
T10	0	70
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	75
T21	305332	11
T42	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7690	0	0
SrcPulseCheck_M	9253749	7690	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7690
T2	519089	3
T3	164953	3
T6	125255	64
T7	114701	59
T8	0	1
T10	0	70
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	75
T21	305332	11
T42	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7690
T2	8651	3
T3	8682	3
T6	25051	64
T7	9559	59
T8	0	1
T10	0	70
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	75
T21	7034	11
T42	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7630	0	0
SrcPulseCheck_M	1172604666	7708	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7630
T2	8651	3
T3	8682	3
T6	25051	71
T7	9559	58
T8	0	1
T10	0	84
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	51
T21	7034	11
T42	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7708
T2	519089	3
T3	164953	3
T6	125255	71
T7	114701	58
T8	0	1
T10	0	84
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	51
T21	305332	11
T42	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7697	0	0
SrcPulseCheck_M	9253749	7697	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7697
T2	519089	3
T3	164953	3
T6	125255	71
T7	114701	58
T8	0	1
T10	0	84
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	51
T21	305332	11
T42	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7697
T2	8651	3
T3	8682	3
T6	25051	71
T7	9559	58
T8	0	1
T10	0	84
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	51
T21	7034	11
T42	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	7718	0	0
SrcPulseCheck_M	1172604666	7796	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	7718
T2	8651	3
T3	8682	3
T6	25051	82
T7	9559	68
T8	0	1
T10	0	63
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	75
T21	7034	11
T42	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	7796
T2	519089	3
T3	164953	3
T6	125255	82
T7	114701	68
T8	0	1
T10	0	63
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	75
T21	305332	11
T42	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T17
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	7785	0	0
SrcPulseCheck_M	9253749	7785	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	7785
T2	519089	3
T3	164953	3
T6	125255	82
T7	114701	68
T8	0	1
T10	0	63
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	75
T21	305332	11
T42	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	7785
T2	8651	3
T3	8682	3
T6	25051	82
T7	9559	68
T8	0	1
T10	0	63
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	75
T21	7034	11
T42	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1707	0	0
SrcPulseCheck_M	1172604666	1782	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1707
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1782
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1771	0	0
SrcPulseCheck_M	9253749	1771	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1771
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1771
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1633	0	0
SrcPulseCheck_M	1172604666	1708	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1633
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1708
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1698	0	0
SrcPulseCheck_M	9253749	1698	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1698
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1698
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1628	0	0
SrcPulseCheck_M	1172604666	1702	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1628
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1702
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1691	0	0
SrcPulseCheck_M	9253749	1691	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1691
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1691
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1610	0	0
SrcPulseCheck_M	1172604666	1685	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1610
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1685
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1676	0	0
SrcPulseCheck_M	9253749	1676	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1676
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1676
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1690	0	0
SrcPulseCheck_M	1172604666	1765	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1690
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1765
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T15
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1753	0	0
SrcPulseCheck_M	9253749	1753	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1753
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T13	258736	0
T14	39646	0
T15	121872	1
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1753
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T13	522	0
T14	495	0
T15	2649	1
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1635	0	0
SrcPulseCheck_M	1172604666	1709	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1635
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1709
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1700	0	0
SrcPulseCheck_M	9253749	1700	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1700
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1700
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1641	0	0
SrcPulseCheck_M	1172604666	1716	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1641
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1716
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1709	0	0
SrcPulseCheck_M	9253749	1709	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1709
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1709
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9253749	1628	0	0
SrcPulseCheck_M	1172604666	1706	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9253749	1628
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1172604666	1706
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T21,T32,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T21,T32,T25
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1172604666	1695	0	0
SrcPulseCheck_M	9253749	1695	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1172604666	1695
T2	519089	3
T3	164953	3
T6	125255	8
T7	114701	2
T8	0	1
T10	0	2
T11	0	16
T13	258736	0
T14	39646	0
T15	121872	0
T16	66620	0
T17	864989	1
T21	305332	9
T42	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9253749	1695
T2	8651	3
T3	8682	3
T6	25051	8
T7	9559	2
T8	0	1
T10	0	2
T11	0	16
T13	522	0
T14	495	0
T15	2649	0
T16	739	0
T17	7208	1
T21	7034	9
T42	0	2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc