Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1946

1

T7

5

T8

6

T9

16

auto[1]

631

1

T7

2

T8

3

T9

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2027

1

T7

7

T8

3

T9

15

auto[1]

550

1

T8

6

T9

5

T33

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1978

1

T7

1

T9

11

T33

7

auto[1]

599

1

T7

6

T8

9

T9

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1907

1

T7

4

T8

3

T9

20

auto[1]

670

1

T7

3

T8

6

T33

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2291

1

T7

7

T8

9

T9

20

auto[1]

286

1

T30

4

T67

26

T213

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2357

1

T7

7

T8

9

T9

16

auto[1]

220

1

T9

4

T30

11

T34

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2293

1

T7

7

T8

9

T9

20

auto[1]

284

1

T30

13

T34

9

T65

12

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2377

1

T7

7

T8

9

T9

11

auto[1]

200

1

T9

9

T30

6

T34

7

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2376

1

T7

7

T8

9

T9

11

auto[1]

201

1

T9

9

T30

5

T34

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T7

2

T8

6

T9

20

auto[1]

634

1

T7

5

T8

3

T33

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

931

1

T7

7

T8

6

T33

18

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

81

1

T214

34

T184

3

T187

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T65

4

T213

7

T215

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T212

6

T316

4

T317

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T34

5

T40

2

T68

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T318

1

-

-

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

14

1

T9

5

T34

2

T319

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T76

4

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T30

9

T34

7

T187

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T30

4

T187

3

T217

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T87

3

T215

2

T320

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T90

8

T321

6

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T315

26

T322

7

T311

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T74

1

T214

2

T315

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T67

6

T213

10

T184

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T67

10

T213

5

T323

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23

1

T30

5

T308

2

T321

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T229

6

T136

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

18

1

T30

6

T87

2

T309

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T67

3

T324

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T9

4

T309

1

T325

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

13

1

T34

2

T65

6

T71

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T74

2

T90

10

T326

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T309

1

T77

2

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T308

2

T327

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

179

1

T37

16

T65

3

T213

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

105

1

T30

4

T67

5

T74

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

59

1

T30

6

T224

4

T215

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

117

1

T34

2

T225

10

T301

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

79

1

T30

9

T34

7

T274

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

97

1

T7

1

T65

3

T83

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T88

1

T232

1

T328

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

95

1

T33

11

T34

5

T45

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

84

1

T9

4

T84

6

T227

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T7

4

T67

3

T69

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T305

1

T226

1

T329

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

76

1

T30

5

T214

17

T268

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T7

2

T124

1

T231

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T8

3

T83

4

T67

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T67

6

T69

2

T219

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T34

2

T300

5

T214

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T316

3

T330

3

T331

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T227

9

T74

1

T299

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T33

4

T218

2

T198

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

74

1

T31

4

T65

4

T227

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T33

3

T224

2

T225

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T32

2

T304

5

T186

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T37

3

T92

1

T306

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T9

5

T32

7

T45

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T8

3

T32

2

T274

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T40

2

T69

3

T300

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T298

2

T332

2

T333

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T300

2

T124

3

T232

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T227

1

T305

1

T244

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T84

3

T334

1

T244

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T300

1

T220

1

T335

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded