Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

942

1

T7

11

T20

18

T60

8

auto[1]

938

1

T7

9

T20

22

T60

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

465

1

T7

3

T20

9

T60

5

from_0to1

464

1

T7

4

T20

8

T60

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

952

1

T7

9

T20

15

T60

10

auto[1]

928

1

T7

11

T20

25

T60

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T7

12

T20

19

T60

13

auto[1]

890

1

T7

8

T20

21

T60

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T7

1

T20

1

T60

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T20

1

T38

2

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T20

3

T60

1

T38

2

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T38

3

T35

1

T151

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T7

1

T20

1

T60

3

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T7

1

T38

1

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T38

1

T48

2

T63

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T7

1

T20

2

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T48

1

T61

1

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T20

1

T60

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T7

2

T20

2

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T20

1

T35

1

T151

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T60

1

T48

1

T62

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T38

1

T48

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T20

1

T38

2

T62

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T7

1

T20

4

T60

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T7

9

T20

16

T60

10

auto[1]

909

1

T7

11

T20

24

T60

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

451

1

T7

6

T20

10

T60

3

from_0to1

456

1

T7

7

T20

9

T60

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T7

6

T20

19

T60

13

auto[1]

906

1

T7

14

T20

21

T60

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T7

14

T20

20

T60

8

auto[1]

919

1

T7

6

T20

20

T60

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T7

1

T48

2

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T7

1

T62

2

T35

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T7

1

T20

1

T48

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T7

1

T20

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T20

1

T60

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T60

1

T38

1

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T20

1

T38

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T7

2

T48

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T20

2

T60

1

T38

3

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T20

2

T60

1

T62

4

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T7

2

T20

1

T61

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T20

3

T61

1

T37

2

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T7

1

T20

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T20

1

T151

1

T118

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T7

4

T20

3

T60

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T20

2

T48

1

T62

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992

1

T7

8

T20

19

T60

12

auto[1]

888

1

T7

12

T20

21

T60

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

449

1

T7

6

T20

7

T60

7

from_0to1

447

1

T7

6

T20

7

T60

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

925

1

T7

6

T20

20

T60

7

auto[1]

955

1

T7

14

T20

20

T60

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

908

1

T7

10

T20

26

T60

12

auto[1]

972

1

T7

10

T20

14

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T7

1

T20

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T20

1

T38

1

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T7

1

T20

1

T60

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T7

1

T20

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T20

2

T48

2

T62

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T60

1

T48

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T7

1

T60

2

T38

3

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T60

1

T151

2

T118

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T7

1

T20

2

T60

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T7

1

T60

1

T38

2

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T7

1

T20

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T61

1

T62

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T7

1

T38

1

T48

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T7

1

T20

1

T48

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T20

2

T60

1

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T7

3

T20

2

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

957

1

T7

12

T20

25

T60

11

auto[1]

923

1

T7

8

T20

15

T60

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

451

1

T7

6

T20

10

T60

4

from_0to1

445

1

T7

5

T20

11

T60

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

943

1

T7

10

T20

16

T60

5

auto[1]

937

1

T7

10

T20

24

T60

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948

1

T7

12

T20

16

T60

12

auto[1]

932

1

T7

8

T20

24

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T7

3

T20

2

T61

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T7

2

T20

3

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T20

1

T60

2

T38

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T60

1

T37

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T38

1

T48

2

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T20

2

T60

1

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T20

1

T60

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T7

1

T20

4

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T61

1

T62

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T38

2

T48

1

T63

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T20

3

T60

1

T48

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T7

1

T20

1

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T7

2

T20

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T7

1

T20

2

T38

2

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T7

1

T63

1

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T20

1

T60

1

T48

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T7

6

T20

18

T60

12

auto[1]

919

1

T7

14

T20

22

T60

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

445

1

T7

6

T20

12

T60

6

from_0to1

451

1

T7

6

T20

11

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

959

1

T7

14

T20

13

T60

10

auto[1]

921

1

T7

6

T20

27

T60

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951

1

T7

10

T20

20

T60

7

auto[1]

929

1

T7

10

T20

20

T60

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T7

2

T20

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T20

2

T48

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T20

1

T38

1

T48

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T20

1

T60

2

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T7

1

T38

2

T48

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T7

1

T60

3

T151

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T20

1

T38

1

T48

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T20

4

T38

1

T48

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T7

1

T20

2

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T7

1

T20

2

T60

2

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T7

1

T20

2

T38

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T7

1

T20

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T7

1

T20

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T7

2

T20

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T7

1

T20

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T20

3

T38

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

957

1

T7

11

T20

25

T60

13

auto[1]

923

1

T7

9

T20

15

T60

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

434

1

T7

5

T20

7

T60

2

from_0to1

442

1

T7

4

T20

8

T60

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T7

9

T20

16

T60

13

auto[1]

913

1

T7

11

T20

24

T60

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

946

1

T7

9

T20

25

T60

7

auto[1]

934

1

T7

11

T20

15

T60

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T20

2

T60

1

T35

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T7

1

T20

1

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T20

1

T48

1

T151

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T7

2

T20

1

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T38

1

T48

1

T61

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T60

1

T48

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T7

2

T20

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T7

1

T20

3

T35

2

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T7

1

T20

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T60

1

T61

1

T63

2

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T7

1

T20

1

T38

2

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T48

1

T61

1

T62

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T7

1

T20

1

T61

2

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T20

1

T48

1

T35

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T20

2

T60

2

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T38

1

T62

1

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948

1

T7

14

T20

24

T60

9

auto[1]

932

1

T7

6

T20

16

T60

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

436

1

T7

3

T20

10

T60

3

from_0to1

443

1

T7

4

T20

10

T60

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

922

1

T7

12

T20

18

T60

11

auto[1]

958

1

T7

8

T20

22

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

915

1

T7

10

T20

18

T60

12

auto[1]

965

1

T7

10

T20

22

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T20

2

T60

1

T48

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T7

1

T20

2

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T20

1

T60

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T38

2

T62

1

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T7

1

T60

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T7

1

T20

4

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T7

1

T20

3

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T20

1

T38

1

T48

2

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T20

1

T48

2

T61

2

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T20

2

T48

1

T151

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T7

2

T20

1

T38

2

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T20

1

T48

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T20

1

T38

2

T48

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T7

1

T60

1

T62

2

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T20

1

T60

2

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T61

2

T62

1

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948

1

T7

13

T20

15

T60

12

auto[1]

932

1

T7

7

T20

25

T60

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

453

1

T7

4

T20

8

T60

5

from_0to1

452

1

T7

5

T20

8

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T7

8

T20

20

T60

12

auto[1]

933

1

T7

12

T20

20

T60

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T7

10

T20

19

T60

9

auto[1]

933

1

T7

10

T20

21

T60

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T276

1

T114

2

T243

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T20

1

T60

1

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T7

1

T60

1

T48

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T7

2

T38

1

T48

2

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T20

2

T60

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T7

1

T20

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T7

2

T20

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T60

1

T38

1

T35

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T20

1

T60

1

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T20

1

T275

1

T276

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T20

2

T60

1

T38

3

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T7

1

T20

3

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T7

1

T60

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T20

2

T60

1

T38

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T7

1

T38

1

T48

3

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T20

2

T48

1

T35

1