Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145259	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110660

1

T4

6

T1

24

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133417	1			T4	3		T1	27		T5	2
values[0x0]	60912	1			T4	7		T1	11		T5	1
values[0x1]	61590	1			T4	2		T1	7		T2	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	117394	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138525

1

T4

7

T1

26

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	661	1			T14	2		T7	7		T38	1
valid_sources[0x01]	957	1			T7	2		T8	3		T12	1
valid_sources[0x02]	1106	1			T7	1		T8	7		T9	6
valid_sources[0x03]	881	1			T7	4		T8	14		T25	2
valid_sources[0x04]	847	1			T7	5		T8	1		T9	5
valid_sources[0x05]	1013	1			T7	2		T9	6		T38	6
valid_sources[0x06]	826	1			T7	2		T9	7		T25	2
valid_sources[0x07]	1304	1			T7	2		T9	10		T25	3
valid_sources[0x08]	694	1			T7	1		T8	4		T38	3
valid_sources[0x09]	881	1			T7	2		T9	1		T25	4
valid_sources[0x0a]	783	1			T7	9		T9	3		T38	1
valid_sources[0x0b]	785	1			T7	3		T25	1		T12	1
valid_sources[0x0c]	1320	1			T7	5		T9	2		T25	2
valid_sources[0x0d]	854	1			T3	1		T7	5		T59	1
valid_sources[0x0e]	1978	1			T7	12		T9	2		T10	2
valid_sources[0x0f]	773	1			T9	8		T25	3		T12	1
valid_sources[0x10]	1628	1			T7	3		T9	15		T25	1
valid_sources[0x11]	909	1			T25	2		T19	2		T38	1
valid_sources[0x12]	931	1			T13	19		T7	6		T8	5
valid_sources[0x13]	1354	1			T7	7		T9	1		T25	2
valid_sources[0x14]	835	1			T7	4		T9	3		T25	2
valid_sources[0x15]	723	1			T7	4		T9	3		T25	2
valid_sources[0x16]	1230	1			T7	4		T8	1		T9	4
valid_sources[0x17]	884	1			T7	3		T25	1		T60	1
valid_sources[0x18]	1105	1			T4	1		T1	3		T7	1
valid_sources[0x19]	887	1			T7	11		T8	6		T10	2
valid_sources[0x1a]	1669	1			T15	1		T7	8		T9	3
valid_sources[0x1b]	690	1			T7	5		T8	10		T9	5
valid_sources[0x1c]	836	1			T7	5		T9	7		T25	1
valid_sources[0x1d]	1834	1			T14	1		T7	2		T8	17
valid_sources[0x1e]	816	1			T1	2		T14	2		T7	5
valid_sources[0x1f]	895	1			T14	5		T7	2		T9	7
valid_sources[0x20]	805	1			T3	1		T7	6		T38	5
valid_sources[0x21]	1045	1			T7	5		T8	3		T9	2
valid_sources[0x22]	949	1			T7	6		T9	8		T12	1
valid_sources[0x23]	765	1			T14	2		T7	5		T8	2
valid_sources[0x24]	1768	1			T14	1		T7	2		T9	2
valid_sources[0x25]	916	1			T7	6		T9	6		T19	1
valid_sources[0x26]	684	1			T7	3		T8	5		T25	2
valid_sources[0x27]	794	1			T7	6		T9	4		T25	2
valid_sources[0x28]	844	1			T4	1		T7	4		T9	1
valid_sources[0x29]	920	1			T1	2		T7	5		T9	4
valid_sources[0x2a]	890	1			T7	4		T9	2		T25	2
valid_sources[0x2b]	881	1			T7	3		T8	2		T9	1
valid_sources[0x2c]	794	1			T7	7		T8	3		T9	4
valid_sources[0x2d]	701	1			T1	2		T7	4		T8	4
valid_sources[0x2e]	826	1			T7	4		T8	3		T9	6
valid_sources[0x2f]	895	1			T7	2		T9	4		T26	11
valid_sources[0x30]	1177	1			T14	5		T3	1		T7	9
valid_sources[0x31]	1634	1			T7	1		T8	9		T9	3
valid_sources[0x32]	800	1			T7	2		T9	3		T25	2
valid_sources[0x33]	1614	1			T7	6		T25	3		T38	4
valid_sources[0x34]	962	1			T7	3		T25	4		T30	10
valid_sources[0x35]	822	1			T7	4		T8	1		T60	4
valid_sources[0x36]	923	1			T7	1		T20	1		T21	1
valid_sources[0x37]	898	1			T7	6		T8	1		T25	2
valid_sources[0x38]	917	1			T7	10		T9	8		T24	1
valid_sources[0x39]	939	1			T7	2		T8	3		T9	7
valid_sources[0x3a]	837	1			T1	2		T7	4		T21	1
valid_sources[0x3b]	1653	1			T7	6		T25	4		T20	6
valid_sources[0x3c]	821	1			T7	5		T8	10		T9	3
valid_sources[0x3d]	1164	1			T14	1		T7	7		T9	1
valid_sources[0x3e]	707	1			T7	1		T9	7		T38	2
valid_sources[0x3f]	979	1			T9	2		T25	1		T38	2
valid_sources[0x40]	786	1			T14	1		T7	3		T9	5
valid_sources[0x41]	958	1			T1	1		T7	4		T9	6
valid_sources[0x42]	800	1			T7	2		T9	8		T25	3
valid_sources[0x43]	1514	1			T7	6		T9	17		T38	2
valid_sources[0x44]	944	1			T7	2		T8	13		T9	3
valid_sources[0x45]	813	1			T5	2		T15	2		T7	3
valid_sources[0x46]	1101	1			T7	2		T9	2		T25	1
valid_sources[0x47]	1217	1			T7	3		T11	1		T12	1
valid_sources[0x48]	1095	1			T7	7		T9	2		T25	1
valid_sources[0x49]	993	1			T7	5		T9	3		T25	2
valid_sources[0x4a]	877	1			T7	3		T8	7		T25	2
valid_sources[0x4b]	1293	1			T7	6		T8	2		T25	1
valid_sources[0x4c]	1765	1			T7	14		T9	3		T25	3
valid_sources[0x4d]	838	1			T7	11		T25	2		T38	2
valid_sources[0x4e]	958	1			T25	1		T26	9		T30	7
valid_sources[0x4f]	790	1			T14	3		T7	5		T8	5
valid_sources[0x50]	679	1			T7	3		T25	2		T30	10
valid_sources[0x51]	842	1			T1	1		T7	10		T25	3
valid_sources[0x52]	1013	1			T4	1		T7	1		T59	1
valid_sources[0x53]	829	1			T7	5		T9	9		T25	5
valid_sources[0x54]	974	1			T7	4		T25	1		T19	2
valid_sources[0x55]	661	1			T1	2		T7	2		T9	2
valid_sources[0x56]	893	1			T1	1		T7	5		T8	15
valid_sources[0x57]	903	1			T7	6		T9	3		T38	4
valid_sources[0x58]	808	1			T8	2		T9	1		T25	2
valid_sources[0x59]	1041	1			T7	1		T9	3		T46	1
valid_sources[0x5a]	986	1			T14	5		T7	3		T9	10
valid_sources[0x5b]	897	1			T7	3		T25	2		T26	9
valid_sources[0x5c]	735	1			T7	2		T9	1		T25	1
valid_sources[0x5d]	1038	1			T7	2		T9	3		T25	1
valid_sources[0x5e]	1345	1			T5	1		T9	7		T25	6
valid_sources[0x5f]	2062	1			T7	2		T9	1		T25	3
valid_sources[0x60]	832	1			T1	1		T7	2		T25	3
valid_sources[0x61]	731	1			T7	5		T8	3		T9	1
valid_sources[0x62]	1046	1			T7	2		T9	9		T25	3
valid_sources[0x63]	944	1			T7	5		T8	4		T9	2
valid_sources[0x64]	849	1			T7	1		T9	3		T25	1
valid_sources[0x65]	1601	1			T14	12		T7	7		T8	14
valid_sources[0x66]	952	1			T3	2		T9	1		T25	5
valid_sources[0x67]	1603	1			T4	2		T7	2		T9	5
valid_sources[0x68]	728	1			T7	11		T9	2		T25	1
valid_sources[0x69]	1156	1			T7	3		T25	2		T38	4
valid_sources[0x6a]	726	1			T7	11		T8	3		T9	4
valid_sources[0x6b]	888	1			T7	3		T46	3		T26	1
valid_sources[0x6c]	778	1			T7	6		T25	2		T38	2
valid_sources[0x6d]	1047	1			T7	7		T8	13		T25	3
valid_sources[0x6e]	808	1			T7	4		T25	2		T26	5
valid_sources[0x6f]	684	1			T7	3		T38	6		T30	8
valid_sources[0x70]	1578	1			T7	2		T8	3		T9	1
valid_sources[0x71]	1184	1			T1	2		T7	10		T9	2
valid_sources[0x72]	793	1			T7	11		T9	3		T25	1
valid_sources[0x73]	1122	1			T7	4		T9	2		T25	2
valid_sources[0x74]	971	1			T1	2		T7	4		T9	14
valid_sources[0x75]	797	1			T7	3		T9	2		T21	2
valid_sources[0x76]	807	1			T1	4		T7	3		T25	1
valid_sources[0x77]	877	1			T3	1		T7	3		T8	10
valid_sources[0x78]	916	1			T14	2		T7	6		T9	3
valid_sources[0x79]	1054	1			T7	5		T25	1		T38	2
valid_sources[0x7a]	877	1			T7	2		T8	3		T9	10
valid_sources[0x7b]	914	1			T7	2		T25	1		T10	2
valid_sources[0x7c]	906	1			T7	3		T8	1		T9	1
valid_sources[0x7d]	1991	1			T7	5		T9	1		T25	1
valid_sources[0x7e]	824	1			T7	7		T9	3		T38	1
valid_sources[0x7f]	1290	1			T7	4		T8	2		T25	2
valid_sources[0x80]	794	1			T3	1		T7	6		T60	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60180

1

T4

2

T1

16

T5

2

values[0x0]

all_enables

biggest_size

29611

1

T4

4

T1

6

T14

9

values[0x1]

all_enables

biggest_size

20869

1

T1

2

T2

1

T14

4