Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T13,T14
1	1	Covered	T21,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T93,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T21,T22,T23
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T22,T23
1	-	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T22,T23
DetectSt	168	Covered	T21,T22,T23
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T21,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T22,T23
DebounceSt->IdleSt	163	Covered	T21,T35,T37
DetectSt->IdleSt	186	Covered	T93,T98
DetectSt->StableSt	191	Covered	T21,T22,T23
IdleSt->DebounceSt	148	Covered	T21,T22,T23
StableSt->IdleSt	206	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T23
0	1	Covered	T21,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T35,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T93,T98
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	260	0	0
CntIncr_A	9010181	216905	0	0
CntNoWrap_A	9010181	8379160	0	0
DetectStDropOut_A	9010181	2	0	0
DetectedOut_A	9010181	865	0	0
DetectedPulseOut_A	9010181	120	0	0
DisabledIdleSt_A	9010181	8156489	0	0
DisabledNoDetection_A	9010181	8158715	0	0
EnterDebounceSt_A	9010181	145	0	0
EnterDetectSt_A	9010181	122	0	0
EnterStableSt_A	9010181	120	0	0
PulseIsPulse_A	9010181	120	0	0
StayInStableSt	9010181	745	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9010181	6554	0	0
gen_low_level_sva.LowLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	119	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	260	0	0
T21	617	3	0	0
T22	714	2	0	0
T23	0	2	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	3	0	0
T37	0	2	0	0
T38	6803	0	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	6	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	6	0	0
T82	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	216905	0	0
T21	617	82	0	0
T22	714	20	0	0
T23	0	92	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	171	0	0
T37	0	2892	0	0
T38	6803	0	0	0
T42	0	99	0	0
T44	0	48	0	0
T45	0	279	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	52	0	0
T82	0	15728	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379160	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2	0	0
T93	714	1	0	0
T98	0	1	0	0
T102	22335	0	0	0
T103	490	0	0	0
T104	499	0	0	0
T105	427	0	0	0
T106	789	0	0	0
T107	1888	0	0	0
T108	2077	0	0	0
T109	405	0	0	0
T110	57071	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	865	0	0
T21	617	9	0	0
T22	714	7	0	0
T23	0	6	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	11	0	0
T37	0	1	0	0
T38	6803	0	0	0
T42	0	9	0	0
T44	0	10	0	0
T45	0	14	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	22	0	0
T82	0	26	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	120	0	0
T21	617	1	0	0
T22	714	1	0	0
T23	0	1	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	3	0	0
T82	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8156489	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8158715	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	145	0	0
T21	617	2	0	0
T22	714	1	0	0
T23	0	1	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	6803	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	3	0	0
T82	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	122	0	0
T21	617	1	0	0
T22	714	1	0	0
T23	0	1	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	3	0	0
T82	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	120	0	0
T21	617	1	0	0
T22	714	1	0	0
T23	0	1	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	3	0	0
T82	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	120	0	0
T21	617	1	0	0
T22	714	1	0	0
T23	0	1	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	3	0	0
T82	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	745	0	0
T21	617	8	0	0
T22	714	6	0	0
T23	0	5	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	10	0	0
T38	6803	0	0	0
T42	0	8	0	0
T44	0	9	0	0
T45	0	12	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	19	0	0
T82	0	22	0	0
T111	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6554	0	0
T1	918	5	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	8	0	0
T7	14517	42	0	0
T8	5132	13	0	0
T9	0	22	0	0
T10	0	9	0	0
T12	0	4	0	0
T13	427	4	0	0
T14	526	4	0	0
T15	402	0	0	0
T25	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	119	0	0
T21	617	1	0	0
T22	714	1	0	0
T23	0	1	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T81	0	3	0	0
T82	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T10,T12,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T38
0	1	Covered	T37,T69,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T38
0	1	Unreachable
1	0	Covered	T10,T12,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T10,T12,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T10,T12,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T38
DebounceSt->IdleSt	163	Covered	T1,T38,T78
DetectSt->IdleSt	186	Covered	T37,T69,T78
DetectSt->StableSt	191	Covered	T10,T12,T38
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T38,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T37,T69,T78
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T38
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	190	0	0
CntIncr_A	9010181	339033	0	0
CntNoWrap_A	9010181	8379230	0	0
DetectStDropOut_A	9010181	9	0	0
DetectedOut_A	9010181	566266	0	0
DetectedPulseOut_A	9010181	59	0	0
DisabledIdleSt_A	9010181	6111828	0	0
DisabledNoDetection_A	9010181	6114103	0	0
EnterDebounceSt_A	9010181	122	0	0
EnterDetectSt_A	9010181	68	0	0
EnterStableSt_A	9010181	59	0	0
PulseIsPulse_A	9010181	59	0	0
StayInStableSt	9010181	566207	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9010181	6554	0	0
gen_low_level_sva.LowLevelEvent_A	9010181	8381696	0	0
gen_sticky_sva.StableStDropOut_A	9010181	1333371	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	190	0	0
T1	918	3	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	4	0	0
T12	0	4	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T38	0	6	0	0
T52	0	4	0	0
T53	0	4	0	0
T69	0	4	0	0
T70	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	339033	0	0
T1	918	81	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	22	0	0
T12	0	88	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	69	0	0
T37	0	34	0	0
T38	0	170	0	0
T52	0	54	0	0
T53	0	160	0	0
T69	0	104	0	0
T70	0	136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379230	0	0
T1	918	514	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	9	0	0
T36	706	0	0	0
T37	37176	2	0	0
T43	17462	0	0	0
T44	745	0	0	0
T55	493	0	0	0
T65	16095	0	0	0
T69	0	1	0	0
T78	0	3	0	0
T83	19116	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	501	0	0	0
T119	737	0	0	0
T120	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	566266	0	0
T10	557799	75	0	0
T11	483	0	0	0
T12	1206	117	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	253	0	0
T38	0	8	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	167	0	0
T53	0	706	0	0
T60	502	0	0	0
T69	0	161	0	0
T70	0	358	0	0
T78	0	155	0	0
T112	0	468	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T10	557799	2	0	0
T11	483	0	0	0
T12	1206	2	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T60	502	0	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6111828	0	0
T1	918	207	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6114103	0	0
T1	918	208	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	122	0	0
T1	918	3	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	2	0	0
T12	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	5	0	0
T52	0	2	0	0
T53	0	2	0	0
T69	0	2	0	0
T70	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	68	0	0
T10	557799	2	0	0
T11	483	0	0	0
T12	1206	2	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T60	502	0	0	0
T69	0	2	0	0
T70	0	2	0	0
T112	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T10	557799	2	0	0
T11	483	0	0	0
T12	1206	2	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T60	502	0	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T10	557799	2	0	0
T11	483	0	0	0
T12	1206	2	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T60	502	0	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	566207	0	0
T10	557799	73	0	0
T11	483	0	0	0
T12	1206	115	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	252	0	0
T38	0	7	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	165	0	0
T53	0	704	0	0
T60	502	0	0	0
T69	0	160	0	0
T70	0	356	0	0
T78	0	153	0	0
T112	0	466	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6554	0	0
T1	918	5	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	8	0	0
T7	14517	42	0	0
T8	5132	13	0	0
T9	0	22	0	0
T10	0	9	0	0
T12	0	4	0	0
T13	427	4	0	0
T14	526	4	0	0
T15	402	0	0	0
T25	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1333371	0	0
T10	557799	433396	0	0
T11	483	0	0	0
T12	1206	530	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T35	0	79	0	0
T38	0	106	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T52	0	449	0	0
T53	0	157	0	0
T60	502	0	0	0
T69	0	285	0	0
T70	0	339	0	0
T78	0	149	0	0
T112	0	120	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T13,T2
1	1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T38,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T13,T2
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T35,T52
0	1	Covered	T12,T79,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T35,T52
0	1	Unreachable
1	0	Covered	T38,T35,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T12,T38,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T38,T35,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T38,T35
DebounceSt->IdleSt	163	Covered	T1,T10,T69
DetectSt->IdleSt	186	Covered	T12,T79,T80
DetectSt->StableSt	191	Covered	T38,T35,T52
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T38,T35,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T38,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T38,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T10,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T79,T80
DetectSt	-	-	-	-	0	1	-	Covered	T38,T35,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T35,T52
StableSt	-	-	-	-	-	-	0	Covered	T38,T35,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	198	0	0
CntIncr_A	9010181	770473	0	0
CntNoWrap_A	9010181	8379222	0	0
DetectStDropOut_A	9010181	11	0	0
DetectedOut_A	9010181	320702	0	0
DetectedPulseOut_A	9010181	53	0	0
DisabledIdleSt_A	9010181	6111828	0	0
DisabledNoDetection_A	9010181	6114103	0	0
EnterDebounceSt_A	9010181	134	0	0
EnterDetectSt_A	9010181	64	0	0
EnterStableSt_A	9010181	53	0	0
PulseIsPulse_A	9010181	53	0	0
StayInStableSt	9010181	320649	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_sticky_sva.StableStDropOut_A	9010181	805650	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	198	0	0
T1	918	3	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	7	0	0
T12	0	8	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T52	0	4	0	0
T53	0	4	0	0
T69	0	5	0	0
T70	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	770473	0	0
T1	918	141	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	433349	0	0
T12	0	376	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	52	0	0
T37	0	60	0	0
T38	0	114	0	0
T52	0	92	0	0
T53	0	90	0	0
T69	0	195	0	0
T70	0	132	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379222	0	0
T1	918	514	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	11	0	0
T12	1206	4	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T22	714	0	0	0
T38	6803	0	0	0
T39	553	0	0	0
T41	443	0	0	0
T46	586	0	0	0
T60	502	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T121	0	1	0	0
T122	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	320702	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	249	0	0
T37	0	172	0	0
T38	6803	400	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T52	0	330	0	0
T53	0	274	0	0
T70	0	437	0	0
T78	0	518	0	0
T112	0	102	0	0
T113	0	731	0	0
T114	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	53	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6111828	0	0
T1	918	207	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6114103	0	0
T1	918	208	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	134	0	0
T1	918	3	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	7	0	0
T12	0	4	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T69	0	5	0	0
T70	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	64	0	0
T12	1206	4	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T22	714	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	2	0	0
T39	553	0	0	0
T41	443	0	0	0
T46	586	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T60	502	0	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	53	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	53	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	6803	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T70	0	2	0	0
T78	0	2	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	320649	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	248	0	0
T37	0	171	0	0
T38	6803	398	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T52	0	328	0	0
T53	0	272	0	0
T70	0	435	0	0
T78	0	516	0	0
T112	0	100	0	0
T113	0	730	0	0
T114	0	54	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	805650	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	104	0	0
T37	0	51	0	0
T38	6803	227	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T52	0	237	0	0
T53	0	668	0	0
T70	0	260	0	0
T78	0	283	0	0
T112	0	606	0	0
T113	0	115	0	0
T114	0	141	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T13,T2
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Covered	T10,T53,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Unreachable
1	0	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T1,T10,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T12
DebounceSt->IdleSt	163	Covered	T10,T52,T53
DetectSt->IdleSt	186	Covered	T10,T53,T78
DetectSt->StableSt	191	Covered	T1,T10,T12
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T1,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T52,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T10,T53,T78
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	202	0	0
CntIncr_A	9010181	359274	0	0
CntNoWrap_A	9010181	8379218	0	0
DetectStDropOut_A	9010181	19	0	0
DetectedOut_A	9010181	173987	0	0
DetectedPulseOut_A	9010181	61	0	0
DisabledIdleSt_A	9010181	6111828	0	0
DisabledNoDetection_A	9010181	6114103	0	0
EnterDebounceSt_A	9010181	122	0	0
EnterDetectSt_A	9010181	80	0	0
EnterStableSt_A	9010181	61	0	0
PulseIsPulse_A	9010181	61	0	0
StayInStableSt	9010181	173926	0	0
gen_high_event_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_sticky_sva.StableStDropOut_A	9010181	772301	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	202	0	0
T1	918	4	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	11	0	0
T12	0	4	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T52	0	2	0	0
T53	0	7	0	0
T69	0	2	0	0
T70	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	359274	0	0
T1	918	64	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	246	0	0
T12	0	186	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	13	0	0
T37	0	51	0	0
T38	0	91	0	0
T52	0	32	0	0
T53	0	212	0	0
T69	0	59	0	0
T70	0	170	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379218	0	0
T1	918	513	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	19	0	0
T10	557799	3	0	0
T11	483	0	0	0
T12	1206	0	0	0
T19	492	0	0	0
T20	4408	0	0	0
T21	617	0	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T53	0	2	0	0
T60	502	0	0	0
T78	0	1	0	0
T123	0	3	0	0
T124	0	3	0	0
T125	0	3	0	0
T126	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	173987	0	0
T1	918	36	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	44	0	0
T12	0	493	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	74	0	0
T37	0	71	0	0
T38	0	215	0	0
T53	0	165	0	0
T69	0	397	0	0
T70	0	595	0	0
T78	0	495	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	61	0	0
T1	918	2	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	2	0	0
T12	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T53	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6111828	0	0
T1	918	207	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6114103	0	0
T1	918	208	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	122	0	0
T1	918	2	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	6	0	0
T12	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T52	0	2	0	0
T53	0	4	0	0
T69	0	1	0	0
T70	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	80	0	0
T1	918	2	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	5	0	0
T12	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T53	0	3	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	61	0	0
T1	918	2	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	2	0	0
T12	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T53	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	61	0	0
T1	918	2	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	2	0	0
T12	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T53	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T78	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	173926	0	0
T1	918	34	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	42	0	0
T12	0	491	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	73	0	0
T37	0	70	0	0
T38	0	213	0	0
T53	0	164	0	0
T69	0	396	0	0
T70	0	593	0	0
T78	0	493	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	772301	0	0
T1	918	196	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T10	0	185694	0	0
T12	0	69	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T35	0	322	0	0
T37	0	169	0	0
T38	0	449	0	0
T53	0	372	0	0
T69	0	184	0	0
T70	0	75	0	0
T78	0	93	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T20,T38,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T20,T38,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T20,T38,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T20
1	0	Covered	T4,T1,T5
1	1	Covered	T20,T38,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T38,T35
0	1	Covered	T116
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T38,T35
0	1	Covered	T38,T127,T128
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T38,T35
1	-	Covered	T38,T127,T128

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T38,T35
DetectSt	168	Covered	T20,T38,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T20,T38,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T38,T35
DebounceSt->IdleSt	163	Covered	T129
DetectSt->IdleSt	186	Covered	T116
DetectSt->StableSt	191	Covered	T20,T38,T35
IdleSt->DebounceSt	148	Covered	T20,T38,T35
StableSt->IdleSt	206	Covered	T20,T38,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T38,T35
0	1	Covered	T20,T38,T35
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T38,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T38,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T38,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T129
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T38,T35
DetectSt	-	-	-	-	1	-	-	Covered	T116
DetectSt	-	-	-	-	0	1	-	Covered	T20,T38,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T127,T128
StableSt	-	-	-	-	-	-	0	Covered	T20,T38,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	75	0	0
CntIncr_A	9010181	52477	0	0
CntNoWrap_A	9010181	8379345	0	0
DetectStDropOut_A	9010181	1	0	0
DetectedOut_A	9010181	52711	0	0
DetectedPulseOut_A	9010181	36	0	0
DisabledIdleSt_A	9010181	7804053	0	0
DisabledNoDetection_A	9010181	7806279	0	0
EnterDebounceSt_A	9010181	39	0	0
EnterDetectSt_A	9010181	37	0	0
EnterStableSt_A	9010181	36	0	0
PulseIsPulse_A	9010181	36	0	0
StayInStableSt	9010181	52654	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	75	0	0
T20	4408	2	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	4	0	0
T38	6803	2	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	2	0	0
T119	0	2	0	0
T127	0	2	0	0
T128	0	2	0	0
T130	0	2	0	0
T131	0	4	0	0
T132	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	52477	0	0
T20	4408	10	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	87	0	0
T38	6803	79	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	50550	0	0
T119	0	47	0	0
T127	0	67	0	0
T128	0	41	0	0
T130	0	55	0	0
T131	0	148	0	0
T132	0	174	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379345	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1	0	0
T116	7333	1	0	0
T133	419	0	0	0
T134	422	0	0	0
T135	13387	0	0	0
T136	23389	0	0	0
T137	464	0	0	0
T138	512	0	0	0
T139	568	0	0	0
T140	785	0	0	0
T141	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	52711	0	0
T20	4408	110	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	183	0	0
T38	6803	72	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	50589	0	0
T119	0	53	0	0
T127	0	60	0	0
T128	0	1	0	0
T130	0	41	0	0
T131	0	84	0	0
T132	0	212	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	36	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	2	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	1	0	0
T119	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7804053	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	116	0	0
T7	14517	8140	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7806279	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	118	0	0
T7	14517	8155	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	39	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	2	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	1	0	0
T119	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	37	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	2	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	1	0	0
T119	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	36	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	2	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	1	0	0
T119	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	36	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	2	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	1	0	0
T119	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	52654	0	0
T20	4408	108	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	179	0	0
T38	6803	71	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T72	0	50587	0	0
T119	0	51	0	0
T127	0	59	0	0
T130	0	39	0	0
T131	0	81	0	0
T132	0	209	0	0
T142	0	196	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	13	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T127	0	1	0	0
T128	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T39,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T39,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T39,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T39
1	0	Covered	T13,T2,T14
1	1	Covered	T7,T39,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T39,T38
0	1	Covered	T35
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T39,T38
0	1	Covered	T38,T35,T36
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T39,T38
1	-	Covered	T38,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T39,T38
DetectSt	168	Covered	T7,T39,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T39,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T39,T38
DebounceSt->IdleSt	163	Covered	T35,T147,T121
DetectSt->IdleSt	186	Covered	T35
DetectSt->StableSt	191	Covered	T7,T39,T38
IdleSt->DebounceSt	148	Covered	T7,T39,T38
StableSt->IdleSt	206	Covered	T7,T38,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T39,T38
0	1	Covered	T7,T39,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T39,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T39,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T39,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T121,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T39,T38
DetectSt	-	-	-	-	1	-	-	Covered	T35
DetectSt	-	-	-	-	0	1	-	Covered	T7,T39,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T7,T39,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	121	0	0
CntIncr_A	9010181	117568	0	0
CntNoWrap_A	9010181	8379299	0	0
DetectStDropOut_A	9010181	1	0	0
DetectedOut_A	9010181	135211	0	0
DetectedPulseOut_A	9010181	58	0	0
DisabledIdleSt_A	9010181	8019628	0	0
DisabledNoDetection_A	9010181	8021850	0	0
EnterDebounceSt_A	9010181	63	0	0
EnterDetectSt_A	9010181	59	0	0
EnterStableSt_A	9010181	58	0	0
PulseIsPulse_A	9010181	58	0	0
StayInStableSt	9010181	135126	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9010181	2369	0	0
gen_low_level_sva.LowLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	121	0	0
T7	14517	2	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	2	0	0
T35	0	10	0	0
T36	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	4	0	0
T147	0	1	0	0
T149	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	117568	0	0
T7	14517	12	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	55	0	0
T35	0	5568	0	0
T36	0	100	0	0
T38	0	158	0	0
T39	0	37	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	40	0	0
T147	0	86	0	0
T149	0	23	0	0
T150	0	7511	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379299	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1	0	0
T35	21188	1	0	0
T36	706	0	0	0
T37	37176	0	0	0
T40	11065	0	0	0
T42	715	0	0	0
T43	17462	0	0	0
T52	1362	0	0	0
T65	16095	0	0	0
T118	501	0	0	0
T151	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	135211	0	0
T7	14517	113	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	306	0	0
T35	0	334	0	0
T36	0	55	0	0
T38	0	94	0	0
T39	0	106	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	104	0	0
T149	0	67	0	0
T150	0	12187	0	0
T152	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	58	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8019628	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	116	0	0
T7	14517	7997	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8021850	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	118	0	0
T7	14517	8011	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	63	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	1	0	0
T35	0	6	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	58	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	58	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	135126	0	0
T7	14517	111	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T33	0	304	0	0
T35	0	329	0	0
T36	0	54	0	0
T38	0	91	0	0
T39	0	104	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	101	0	0
T149	0	65	0	0
T150	0	12185	0	0
T152	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2369	0	0
T2	682	2	0	0
T3	670	1	0	0
T6	1945	8	0	0
T7	14517	30	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T13	427	1	0	0
T14	526	7	0	0
T15	402	0	0	0
T19	0	5	0	0
T20	0	22	0	0
T39	0	1	0	0
T58	409	0	0	0
T60	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	29	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	0	0	0
T34	23794	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T38	6803	1	0	0
T46	586	0	0	0
T47	427	0	0	0
T48	502	0	0	0
T113	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T142	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0