Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.34	89.13	90.48		83.33	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.34	89.13	90.48		83.33	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T13,T2
1	1	Covered	T4,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T13,T14
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T35
0	1	Covered	T7,T35,T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T35
0	1	Covered	T2,T35,T37
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T35
1	-	Covered	T2,T35,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T35,T153,T163
DetectSt->IdleSt	186	Covered	T7,T35,T200
DetectSt->StableSt	191	Covered	T2,T6,T35
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T2,T6,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T35,T200
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T35,T37
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	127	0	0
CntIncr_A	9010181	53542	0	0
CntNoWrap_A	9010181	8379293	0	0
DetectStDropOut_A	9010181	3	0	0
DetectedOut_A	9010181	21177	0	0
DetectedPulseOut_A	9010181	59	0	0
DisabledIdleSt_A	9010181	8115034	0	0
DisabledNoDetection_A	9010181	8117254	0	0
EnterDebounceSt_A	9010181	66	0	0
EnterDetectSt_A	9010181	62	0	0
EnterStableSt_A	9010181	59	0	0
PulseIsPulse_A	9010181	59	0	0
StayInStableSt	9010181	21089	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	127	0	0
T2	682	2	0	0
T3	670	0	0	0
T6	1945	2	0	0
T7	14517	2	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	10	0	0
T37	0	4	0	0
T45	0	2	0	0
T58	409	0	0	0
T119	0	4	0	0
T127	0	2	0	0
T149	0	2	0	0
T150	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	53542	0	0
T2	682	37	0	0
T3	670	0	0	0
T6	1945	62	0	0
T7	14517	47	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	5515	0	0
T37	0	124	0	0
T45	0	96	0	0
T58	409	0	0	0
T119	0	94	0	0
T127	0	67	0	0
T149	0	23	0	0
T150	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379293	0	0
T1	918	517	0	0
T2	682	279	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	340	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	3	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T200	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	21177	0	0
T2	682	3	0	0
T3	670	0	0	0
T6	1945	160	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	354	0	0
T37	0	73	0	0
T45	0	45	0	0
T58	409	0	0	0
T119	0	45	0	0
T127	0	237	0	0
T147	0	37	0	0
T149	0	67	0	0
T150	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	1	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	4	0	0
T37	0	2	0	0
T45	0	1	0	0
T58	409	0	0	0
T119	0	2	0	0
T127	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8115034	0	0
T1	918	517	0	0
T2	682	4	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	116	0	0
T7	14517	8140	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8117254	0	0
T1	918	518	0	0
T2	682	4	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	118	0	0
T7	14517	8155	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	66	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	6	0	0
T37	0	2	0	0
T45	0	1	0	0
T58	409	0	0	0
T119	0	2	0	0
T127	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	62	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	5	0	0
T37	0	2	0	0
T45	0	1	0	0
T58	409	0	0	0
T119	0	2	0	0
T127	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	1	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	4	0	0
T37	0	2	0	0
T45	0	1	0	0
T58	409	0	0	0
T119	0	2	0	0
T127	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	1	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	4	0	0
T37	0	2	0	0
T45	0	1	0	0
T58	409	0	0	0
T119	0	2	0	0
T127	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	21089	0	0
T2	682	2	0	0
T3	670	0	0	0
T6	1945	158	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	347	0	0
T37	0	71	0	0
T45	0	43	0	0
T58	409	0	0	0
T119	0	43	0	0
T127	0	236	0	0
T147	0	35	0	0
T149	0	65	0	0
T150	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	28	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T58	409	0	0	0
T113	0	1	0	0
T119	0	2	0	0
T127	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T174	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T7,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T7,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T7,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T13,T14
1	1	Covered	T2,T7,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T37
0	1	Covered	T7,T37,T150
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T37
1	-	Covered	T7,T37,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T37
DetectSt	168	Covered	T2,T7,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T7,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T37
DebounceSt->IdleSt	163	Covered	T129
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T7,T37
IdleSt->DebounceSt	148	Covered	T2,T7,T37
StableSt->IdleSt	206	Covered	T7,T37,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T37
0	1	Covered	T2,T7,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T37
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T37,T150
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	64	0	0
CntIncr_A	9010181	29165	0	0
CntNoWrap_A	9010181	8379356	0	0
DetectStDropOut_A	9010181	0	0	0
DetectedOut_A	9010181	7990	0	0
DetectedPulseOut_A	9010181	32	0	0
DisabledIdleSt_A	9010181	8255520	0	0
DisabledNoDetection_A	9010181	8257747	0	0
EnterDebounceSt_A	9010181	33	0	0
EnterDetectSt_A	9010181	32	0	0
EnterStableSt_A	9010181	32	0	0
PulseIsPulse_A	9010181	32	0	0
StayInStableSt	9010181	7942	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9010181	5916	0	0
gen_low_level_sva.LowLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	64	0	0
T2	682	2	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	2	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	4	0	0
T58	409	0	0	0
T79	0	2	0	0
T113	0	2	0	0
T132	0	2	0	0
T150	0	2	0	0
T154	0	2	0	0
T155	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	29165	0	0
T2	682	37	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	12	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	124	0	0
T58	409	0	0	0
T79	0	27542	0	0
T113	0	12	0	0
T132	0	87	0	0
T150	0	47	0	0
T154	0	62	0	0
T155	0	51	0	0
T163	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379356	0	0
T1	918	517	0	0
T2	682	279	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7990	0	0
T2	682	195	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	41	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	291	0	0
T58	409	0	0	0
T79	0	5408	0	0
T113	0	38	0	0
T132	0	430	0	0
T150	0	1	0	0
T154	0	124	0	0
T155	0	42	0	0
T163	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	32	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	2	0	0
T58	409	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T132	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8255520	0	0
T1	918	517	0	0
T2	682	4	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	116	0	0
T7	14517	8138	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8257747	0	0
T1	918	518	0	0
T2	682	4	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	118	0	0
T7	14517	8153	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	33	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	2	0	0
T58	409	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T132	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	32	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	2	0	0
T58	409	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T132	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	32	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	2	0	0
T58	409	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T132	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	32	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	2	0	0
T58	409	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T132	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7942	0	0
T2	682	193	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	40	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T37	0	288	0	0
T58	409	0	0	0
T79	0	5406	0	0
T113	0	36	0	0
T132	0	428	0	0
T142	0	78	0	0
T154	0	123	0	0
T155	0	40	0	0
T163	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	5916	0	0
T1	918	0	0	0
T2	682	1	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	11	0	0
T7	14517	42	0	0
T8	0	9	0	0
T9	0	24	0	0
T13	427	1	0	0
T14	526	6	0	0
T15	402	0	0	0
T24	0	1	0	0
T25	0	22	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	14	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T37	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T160	0	2	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T13,T2
1	1	Covered	T4,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T13,T14
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T20,T164,T199
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T6,T20
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T2,T6,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T35,T150,T79
DetectSt->IdleSt	186	Covered	T20,T164,T199
DetectSt->StableSt	191	Covered	T2,T3,T6
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T128,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T20,T164,T199
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T20
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	131	0	0
CntIncr_A	9010181	18631	0	0
CntNoWrap_A	9010181	8379289	0	0
DetectStDropOut_A	9010181	3	0	0
DetectedOut_A	9010181	7720	0	0
DetectedPulseOut_A	9010181	60	0	0
DisabledIdleSt_A	9010181	8258988	0	0
DisabledNoDetection_A	9010181	8261206	0	0
EnterDebounceSt_A	9010181	70	0	0
EnterDetectSt_A	9010181	63	0	0
EnterStableSt_A	9010181	60	0	0
PulseIsPulse_A	9010181	60	0	0
StayInStableSt	9010181	7632	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	131	0	0
T2	682	2	0	0
T3	670	2	0	0
T6	1945	2	0	0
T7	14517	2	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	4	0	0
T24	460	0	0	0
T33	0	4	0	0
T35	0	10	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T58	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	18631	0	0
T2	682	37	0	0
T3	670	97	0	0
T6	1945	62	0	0
T7	14517	12	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	20	0	0
T24	460	0	0	0
T33	0	110	0	0
T35	0	208	0	0
T36	0	100	0	0
T38	0	79	0	0
T39	0	37	0	0
T58	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379289	0	0
T1	918	517	0	0
T2	682	279	0	0
T3	670	267	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	340	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	3	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T38	6803	0	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T164	0	1	0	0
T199	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7720	0	0
T2	682	43	0	0
T3	670	164	0	0
T6	1945	60	0	0
T7	14517	126	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T33	0	146	0	0
T35	0	460	0	0
T36	0	41	0	0
T38	0	326	0	0
T39	0	42	0	0
T58	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	60	0	0
T2	682	1	0	0
T3	670	1	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8258988	0	0
T1	918	517	0	0
T2	682	4	0	0
T3	670	4	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	116	0	0
T7	14517	8138	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8261206	0	0
T1	918	518	0	0
T2	682	4	0	0
T3	670	4	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	118	0	0
T7	14517	8153	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	70	0	0
T2	682	1	0	0
T3	670	1	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T33	0	2	0	0
T35	0	6	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	63	0	0
T2	682	1	0	0
T3	670	1	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	60	0	0
T2	682	1	0	0
T3	670	1	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	60	0	0
T2	682	1	0	0
T3	670	1	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7632	0	0
T2	682	42	0	0
T3	670	162	0	0
T6	1945	59	0	0
T7	14517	124	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	460	0	0	0
T33	0	143	0	0
T35	0	453	0	0
T36	0	39	0	0
T38	0	324	0	0
T39	0	40	0	0
T58	409	0	0	0
T119	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	30	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	1	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T58	409	0	0	0
T119	0	1	0	0
T131	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T20,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T20,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T20,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T20
1	0	Covered	T4,T13,T14
1	1	Covered	T2,T20,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T35
0	1	Covered	T72,T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T35
0	1	Covered	T20,T35,T127
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T20,T35
1	-	Covered	T20,T35,T127

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T20,T35
DetectSt	168	Covered	T2,T20,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T20,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T20,T35
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T72,T200
DetectSt->StableSt	191	Covered	T2,T20,T35
IdleSt->DebounceSt	148	Covered	T2,T20,T35
StableSt->IdleSt	206	Covered	T20,T35,T127

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T20,T35
0	1	Covered	T2,T20,T35
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T20,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T20,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T20,T35
DetectSt	-	-	-	-	1	-	-	Covered	T72,T200
DetectSt	-	-	-	-	0	1	-	Covered	T2,T20,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T35,T127
StableSt	-	-	-	-	-	-	0	Covered	T2,T20,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	62	0	0
CntIncr_A	9010181	59210	0	0
CntNoWrap_A	9010181	8379358	0	0
DetectStDropOut_A	9010181	2	0	0
DetectedOut_A	9010181	2027	0	0
DetectedPulseOut_A	9010181	29	0	0
DisabledIdleSt_A	9010181	7814838	0	0
DisabledNoDetection_A	9010181	7817066	0	0
EnterDebounceSt_A	9010181	31	0	0
EnterDetectSt_A	9010181	31	0	0
EnterStableSt_A	9010181	29	0	0
PulseIsPulse_A	9010181	29	0	0
StayInStableSt	9010181	1980	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9010181	6009	0	0
gen_low_level_sva.LowLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	62	0	0
T2	682	2	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	4	0	0
T24	460	0	0	0
T35	0	4	0	0
T58	409	0	0	0
T72	0	2	0	0
T113	0	4	0	0
T127	0	4	0	0
T147	0	2	0	0
T150	0	2	0	0
T163	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	59210	0	0
T2	682	37	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	20	0	0
T24	460	0	0	0
T35	0	92	0	0
T58	409	0	0	0
T72	0	50550	0	0
T113	0	32	0	0
T127	0	134	0	0
T147	0	86	0	0
T150	0	7511	0	0
T163	0	20	0	0
T174	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379358	0	0
T1	918	517	0	0
T2	682	279	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2	0	0
T72	209765	1	0	0
T78	1349	0	0	0
T86	4531	0	0	0
T200	0	1	0	0
T201	692	0	0	0
T202	491	0	0	0
T203	688	0	0	0
T204	449	0	0	0
T205	7165	0	0	0
T206	494	0	0	0
T207	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2027	0	0
T2	682	115	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	87	0	0
T24	460	0	0	0
T35	0	225	0	0
T58	409	0	0	0
T113	0	81	0	0
T127	0	150	0	0
T128	0	163	0	0
T147	0	37	0	0
T150	0	44	0	0
T163	0	54	0	0
T174	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	29	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T35	0	2	0	0
T58	409	0	0	0
T113	0	2	0	0
T127	0	2	0	0
T128	0	1	0	0
T147	0	1	0	0
T150	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7814838	0	0
T1	918	517	0	0
T2	682	4	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8138	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7817066	0	0
T1	918	518	0	0
T2	682	4	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8153	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	31	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T35	0	2	0	0
T58	409	0	0	0
T72	0	1	0	0
T113	0	2	0	0
T127	0	2	0	0
T147	0	1	0	0
T150	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	31	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T35	0	2	0	0
T58	409	0	0	0
T72	0	1	0	0
T113	0	2	0	0
T127	0	2	0	0
T147	0	1	0	0
T150	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	29	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T35	0	2	0	0
T58	409	0	0	0
T113	0	2	0	0
T127	0	2	0	0
T128	0	1	0	0
T147	0	1	0	0
T150	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	29	0	0
T2	682	1	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T35	0	2	0	0
T58	409	0	0	0
T113	0	2	0	0
T127	0	2	0	0
T128	0	1	0	0
T147	0	1	0	0
T150	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1980	0	0
T2	682	113	0	0
T3	670	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T20	0	84	0	0
T24	460	0	0	0
T35	0	222	0	0
T58	409	0	0	0
T113	0	77	0	0
T127	0	147	0	0
T128	0	161	0	0
T147	0	35	0	0
T150	0	43	0	0
T163	0	52	0	0
T174	0	140	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6009	0	0
T1	918	0	0	0
T2	682	1	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	11	0	0
T7	14517	41	0	0
T8	0	11	0	0
T9	0	26	0	0
T11	0	1	0	0
T13	427	2	0	0
T14	526	6	0	0
T15	402	0	0	0
T25	0	21	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	9	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T35	0	1	0	0
T38	6803	0	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T121	0	1	0	0
T127	0	1	0	0
T150	0	1	0	0
T176	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T13,T2
1	1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T7,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T39
1	0	Covered	T1,T13,T2
1	1	Covered	T6,T7,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T39
0	1	Covered	T20,T149,T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T39
0	1	Covered	T35,T37,T36
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T39
1	-	Covered	T35,T37,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T39
DetectSt	168	Covered	T6,T7,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T39
DebounceSt->IdleSt	163	Covered	T144,T129
DetectSt->IdleSt	186	Covered	T20,T149,T164
DetectSt->StableSt	191	Covered	T6,T7,T39
IdleSt->DebounceSt	148	Covered	T6,T7,T39
StableSt->IdleSt	206	Covered	T6,T7,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T39
0	1	Covered	T6,T7,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T144
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T39
DetectSt	-	-	-	-	1	-	-	Covered	T20,T149,T164
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T36
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	103	0	0
CntIncr_A	9010181	60350	0	0
CntNoWrap_A	9010181	8379317	0	0
DetectStDropOut_A	9010181	4	0	0
DetectedOut_A	9010181	110317	0	0
DetectedPulseOut_A	9010181	47	0	0
DisabledIdleSt_A	9010181	8147566	0	0
DisabledNoDetection_A	9010181	8149797	0	0
EnterDebounceSt_A	9010181	53	0	0
EnterDetectSt_A	9010181	51	0	0
EnterStableSt_A	9010181	47	0	0
PulseIsPulse_A	9010181	47	0	0
StayInStableSt	9010181	110250	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	103	0	0
T6	1945	2	0	0
T7	14517	2	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T20	0	2	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	6	0	0
T39	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	60350	0	0
T6	1945	62	0	0
T7	14517	12	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T20	0	10	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	158	0	0
T36	0	100	0	0
T37	0	186	0	0
T39	0	37	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	12	0	0
T149	0	23	0	0
T150	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379317	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	340	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	4	0	0
T20	4408	1	0	0
T21	617	0	0	0
T22	714	0	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T33	227835	0	0	0
T38	6803	0	0	0
T46	586	0	0	0
T47	427	0	0	0
T60	502	0	0	0
T149	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	110317	0	0
T6	1945	37	0	0
T7	14517	60	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	352	0	0
T36	0	56	0	0
T37	0	132	0	0
T39	0	41	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T79	0	23209	0	0
T113	0	39	0	0
T150	0	40	0	0
T153	0	214	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	47	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8147566	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	116	0	0
T7	14517	8138	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8149797	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	118	0	0
T7	14517	8153	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	53	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	51	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T20	0	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T113	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	47	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	47	0	0
T6	1945	1	0	0
T7	14517	1	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T79	0	1	0	0
T113	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	110250	0	0
T6	1945	35	0	0
T7	14517	58	0	0
T8	5132	0	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T35	0	348	0	0
T36	0	55	0	0
T37	0	128	0	0
T39	0	39	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T79	0	23208	0	0
T113	0	37	0	0
T150	0	39	0	0
T153	0	212	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	25	0	0
T35	21188	2	0	0
T36	706	1	0	0
T37	37176	2	0	0
T40	11065	0	0	0
T42	715	0	0	0
T43	17462	0	0	0
T52	1362	0	0	0
T65	16095	0	0	0
T79	0	1	0	0
T98	0	1	0	0
T118	501	0	0	0
T131	0	2	0	0
T150	0	1	0	0
T151	503	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T189	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T33,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T33,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T33,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T38,T33
1	0	Covered	T1,T13,T14
1	1	Covered	T33,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T35,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T35,T36
0	1	Covered	T35,T153,T182
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T35,T36
1	-	Covered	T35,T153,T182

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T35,T36
DetectSt	168	Covered	T33,T35,T36
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T33,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T35,T36
DebounceSt->IdleSt	163	Covered	T116
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T33,T35,T36
IdleSt->DebounceSt	148	Covered	T33,T35,T36
StableSt->IdleSt	206	Covered	T33,T35,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T35,T36
0	1	Covered	T33,T35,T36
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T35,T36
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T116
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T35,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T33,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T153,T182
StableSt	-	-	-	-	-	-	0	Covered	T33,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	75	0	0
CntIncr_A	9010181	125137	0	0
CntNoWrap_A	9010181	8379345	0	0
DetectStDropOut_A	9010181	0	0	0
DetectedOut_A	9010181	58220	0	0
DetectedPulseOut_A	9010181	37	0	0
DisabledIdleSt_A	9010181	7711194	0	0
DisabledNoDetection_A	9010181	7713418	0	0
EnterDebounceSt_A	9010181	38	0	0
EnterDetectSt_A	9010181	37	0	0
EnterStableSt_A	9010181	37	0	0
PulseIsPulse_A	9010181	37	0	0
StayInStableSt	9010181	58161	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9010181	6554	0	0
gen_low_level_sva.LowLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	75	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	2	0	0
T34	23794	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	2	0	0
T79	0	2	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	2	0	0
T132	0	4	0	0
T150	0	2	0	0
T153	0	4	0	0
T182	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	125137	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	55	0	0
T34	23794	0	0	0
T35	0	205	0	0
T36	0	100	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	50550	0	0
T79	0	27542	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	55	0	0
T132	0	174	0	0
T150	0	47	0	0
T153	0	176	0	0
T182	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8379345	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	58220	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	150	0	0
T34	23794	0	0	0
T35	0	95	0	0
T36	0	40	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	50590	0	0
T79	0	5407	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	41	0	0
T132	0	199	0	0
T150	0	90	0	0
T153	0	171	0	0
T182	0	184	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	37	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	1	0	0
T34	23794	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	1	0	0
T132	0	2	0	0
T150	0	1	0	0
T153	0	2	0	0
T182	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7711194	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	4	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7713418	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	4	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	38	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	1	0	0
T34	23794	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	1	0	0
T132	0	2	0	0
T150	0	1	0	0
T153	0	2	0	0
T182	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	37	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	1	0	0
T34	23794	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	1	0	0
T132	0	2	0	0
T150	0	1	0	0
T153	0	2	0	0
T182	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	37	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	1	0	0
T34	23794	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	1	0	0
T132	0	2	0	0
T150	0	1	0	0
T153	0	2	0	0
T182	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	37	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	1	0	0
T34	23794	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	1	0	0
T132	0	2	0	0
T150	0	1	0	0
T153	0	2	0	0
T182	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	58161	0	0
T26	4272	0	0	0
T30	30644	0	0	0
T31	13765	0	0	0
T33	227835	148	0	0
T34	23794	0	0	0
T35	0	90	0	0
T36	0	38	0	0
T47	427	0	0	0
T48	502	0	0	0
T61	504	0	0	0
T72	0	50588	0	0
T79	0	5405	0	0
T99	407	0	0	0
T100	423	0	0	0
T130	0	39	0	0
T132	0	197	0	0
T150	0	88	0	0
T153	0	169	0	0
T182	0	182	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	6554	0	0
T1	918	5	0	0
T2	682	0	0	0
T3	670	0	0	0
T5	402	0	0	0
T6	1945	8	0	0
T7	14517	42	0	0
T8	5132	13	0	0
T9	0	22	0	0
T10	0	9	0	0
T12	0	4	0	0
T13	427	4	0	0
T14	526	4	0	0
T15	402	0	0	0
T25	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	13	0	0
T35	21188	1	0	0
T36	706	0	0	0
T37	37176	0	0	0
T40	11065	0	0	0
T42	715	0	0	0
T43	17462	0	0	0
T52	1362	0	0	0
T65	16095	0	0	0
T118	501	0	0	0
T129	0	1	0	0
T132	0	2	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T151	503	0	0	0
T153	0	2	0	0
T156	0	1	0	0
T182	0	2	0	0
T199	0	1	0	0