Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T25,T26
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T30,T34
1	1	Covered	T4,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T24
0	1	Covered	T25,T26,T66
1	0	Covered	T9,T74,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T24,T30
0	1	Covered	T30,T34,T40
1	0	Covered	T77,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T24,T30
1	-	Covered	T30,T34,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T24
DetectSt	168	Covered	T4,T9,T24
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T4,T24,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T24
DebounceSt->IdleSt	163	Covered	T209,T210,T211
DetectSt->IdleSt	186	Covered	T9,T25,T26
DetectSt->StableSt	191	Covered	T4,T24,T30
IdleSt->DebounceSt	148	Covered	T4,T9,T24
StableSt->IdleSt	206	Covered	T30,T34,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T9,T24
0	1	Covered	T4,T9,T24
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T24
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T9,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T209,T210,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T9,T25,T26
DetectSt	-	-	-	-	0	1	-	Covered	T4,T24,T30
DetectSt	-	-	-	-	0	0	-	Covered	T4,T9,T24
StableSt	-	-	-	-	-	-	1	Covered	T30,T34,T40
StableSt	-	-	-	-	-	-	0	Covered	T4,T24,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	2568	0	0
CntIncr_A	9010181	77310	0	0
CntNoWrap_A	9010181	8376852	0	0
DetectStDropOut_A	9010181	334	0	0
DetectedOut_A	9010181	58428	0	0
DetectedPulseOut_A	9010181	746	0	0
DisabledIdleSt_A	9010181	7986172	0	0
DisabledNoDetection_A	9010181	7988259	0	0
EnterDebounceSt_A	9010181	1305	0	0
EnterDetectSt_A	9010181	1266	0	0
EnterStableSt_A	9010181	746	0	0
PulseIsPulse_A	9010181	746	0	0
StayInStableSt	9010181	57581	0	0
gen_high_event_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	641	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2568	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	2	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T9	0	16	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	2	0	0
T25	0	16	0	0
T26	0	12	0	0
T30	0	12	0	0
T34	0	54	0	0
T40	0	30	0	0
T65	0	42	0	0
T66	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	77310	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	21	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T9	0	492	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	21	0	0
T25	0	316	0	0
T26	0	192	0	0
T30	0	354	0	0
T34	0	729	0	0
T40	0	465	0	0
T65	0	1344	0	0
T66	0	300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8376852	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	57	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	334	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T19	492	0	0	0
T20	4408	0	0	0
T25	4620	8	0	0
T26	0	6	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T60	502	0	0	0
T66	0	6	0	0
T85	0	23	0	0
T86	0	10	0	0
T87	0	9	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	14	0	0
T212	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	58428	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	35	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	34	0	0
T30	0	655	0	0
T34	0	2373	0	0
T40	0	473	0	0
T65	0	533	0	0
T67	0	987	0	0
T68	0	339	0	0
T178	0	41	0	0
T213	0	3018	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	746	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T30	0	6	0	0
T34	0	27	0	0
T40	0	15	0	0
T65	0	21	0	0
T67	0	8	0	0
T68	0	8	0	0
T178	0	1	0	0
T213	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7986172	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	3	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7988259	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	3	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1305	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T9	0	8	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T25	0	8	0	0
T26	0	6	0	0
T30	0	6	0	0
T34	0	27	0	0
T40	0	15	0	0
T65	0	21	0	0
T66	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1266	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T9	0	8	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T25	0	8	0	0
T26	0	6	0	0
T30	0	6	0	0
T34	0	27	0	0
T40	0	15	0	0
T65	0	21	0	0
T66	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	746	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T30	0	6	0	0
T34	0	27	0	0
T40	0	15	0	0
T65	0	21	0	0
T67	0	8	0	0
T68	0	8	0	0
T178	0	1	0	0
T213	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	746	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T30	0	6	0	0
T34	0	27	0	0
T40	0	15	0	0
T65	0	21	0	0
T67	0	8	0	0
T68	0	8	0	0
T178	0	1	0	0
T213	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	57581	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	33	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	0	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	32	0	0
T30	0	646	0	0
T34	0	2340	0	0
T40	0	458	0	0
T65	0	510	0	0
T67	0	978	0	0
T68	0	331	0	0
T178	0	39	0	0
T213	0	2985	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	641	0	0
T30	30644	3	0	0
T31	13765	0	0	0
T34	23794	21	0	0
T40	0	15	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	19	0	0
T67	0	7	0	0
T68	0	8	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T184	0	6	0	0
T213	0	19	0	0
T214	0	18	0	0
T215	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T7,T8
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T4,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T6,T7,T9
1	1	Covered	T4,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T31,T32,T83
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T7,T8,T11
1	0	Covered	T49,T216,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T11
1	-	Covered	T7,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T8
DetectSt	168	Covered	T7,T8,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T11
DebounceSt->IdleSt	163	Covered	T4,T24,T41
DetectSt->IdleSt	186	Covered	T31,T32,T83
DetectSt->StableSt	191	Covered	T7,T8,T11
IdleSt->DebounceSt	148	Covered	T4,T7,T8
StableSt->IdleSt	206	Covered	T7,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T8
0	1	Covered	T4,T7,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T24,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T31,T32,T83
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T11
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	940	0	0
CntIncr_A	9010181	50180	0	0
CntNoWrap_A	9010181	8378480	0	0
DetectStDropOut_A	9010181	70	0	0
DetectedOut_A	9010181	15454	0	0
DetectedPulseOut_A	9010181	356	0	0
DisabledIdleSt_A	9010181	7985556	0	0
DisabledNoDetection_A	9010181	7987090	0	0
EnterDebounceSt_A	9010181	510	0	0
EnterDetectSt_A	9010181	431	0	0
EnterStableSt_A	9010181	356	0	0
PulseIsPulse_A	9010181	356	0	0
StayInStableSt	9010181	15069	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	940	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	6	0	0
T8	0	6	0	0
T11	0	2	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T30	0	6	0	0
T33	0	6	0	0
T34	0	10	0	0
T38	0	1	0	0
T41	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	50180	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	20	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	177	0	0
T8	0	216	0	0
T11	0	25	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	20	0	0
T30	0	174	0	0
T33	0	483	0	0
T34	0	215	0	0
T38	0	20	0	0
T41	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8378480	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	58	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8275	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	70	0	0
T23	649	0	0	0
T31	13765	2	0	0
T32	0	1	0	0
T54	500	0	0	0
T61	504	0	0	0
T62	506	0	0	0
T63	501	0	0	0
T64	522	0	0	0
T83	0	5	0	0
T84	0	8	0	0
T88	0	1	0	0
T92	0	2	0	0
T94	0	10	0	0
T95	0	7	0	0
T96	0	2	0	0
T97	0	2	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	15454	0	0
T7	14517	39	0	0
T8	5132	58	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	3	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	77	0	0
T33	0	253	0	0
T34	0	365	0	0
T37	0	258	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	109	0	0
T67	0	53	0	0
T69	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	356	0	0
T7	14517	3	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	3	0	0
T33	0	3	0	0
T34	0	5	0	0
T37	0	4	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7985556	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	25	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	6990	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7987090	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	25	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	7003	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	510	0	0
T1	918	0	0	0
T2	682	0	0	0
T3	670	0	0	0
T4	460	1	0	0
T5	402	0	0	0
T6	1945	0	0	0
T7	14517	3	0	0
T8	0	3	0	0
T11	0	1	0	0
T13	427	0	0	0
T14	526	0	0	0
T15	402	0	0	0
T24	0	1	0	0
T30	0	3	0	0
T33	0	3	0	0
T34	0	5	0	0
T38	0	1	0	0
T41	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	431	0	0
T7	14517	3	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	5	0	0
T37	0	4	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	356	0	0
T7	14517	3	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	3	0	0
T33	0	3	0	0
T34	0	5	0	0
T37	0	4	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	356	0	0
T7	14517	3	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	3	0	0
T33	0	3	0	0
T34	0	5	0	0
T37	0	4	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	15069	0	0
T7	14517	36	0	0
T8	5132	55	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	2	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	72	0	0
T33	0	250	0	0
T34	0	360	0	0
T37	0	254	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	107	0	0
T67	0	52	0	0
T69	0	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	323	0	0
T7	14517	3	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	1	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	1	0	0
T33	0	3	0	0
T34	0	5	0	0
T37	0	4	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1	0	0
T67	0	1	0	0
T69	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T25,T26
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T30,T34
1	1	Covered	T9,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T26
0	1	Covered	T9,T25,T26
1	0	Covered	T87,T217,T218

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T34,T40
0	1	Covered	T30,T34,T40
1	0	Covered	T75,T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T34,T40
1	-	Covered	T30,T34,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T26
DetectSt	168	Covered	T9,T25,T26
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T30,T34,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T25,T26
DebounceSt->IdleSt	163	Covered	T209,T210,T211
DetectSt->IdleSt	186	Covered	T9,T25,T26
DetectSt->StableSt	191	Covered	T30,T34,T40
IdleSt->DebounceSt	148	Covered	T9,T25,T26
StableSt->IdleSt	206	Covered	T30,T34,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T25,T26
0	1	Covered	T9,T25,T26
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T25,T26
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T9,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T25,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T209,T210,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T9,T25,T26
DetectSt	-	-	-	-	0	1	-	Covered	T30,T34,T40
DetectSt	-	-	-	-	0	0	-	Covered	T9,T25,T26
StableSt	-	-	-	-	-	-	1	Covered	T30,T34,T40
StableSt	-	-	-	-	-	-	0	Covered	T30,T34,T40
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	2932	0	0
CntIncr_A	9010181	91988	0	0
CntNoWrap_A	9010181	8376488	0	0
DetectStDropOut_A	9010181	377	0	0
DetectedOut_A	9010181	65939	0	0
DetectedPulseOut_A	9010181	902	0	0
DisabledIdleSt_A	9010181	7982944	0	0
DisabledNoDetection_A	9010181	7985034	0	0
EnterDebounceSt_A	9010181	1486	0	0
EnterDetectSt_A	9010181	1449	0	0
EnterStableSt_A	9010181	902	0	0
PulseIsPulse_A	9010181	902	0	0
StayInStableSt	9010181	64939	0	0
gen_high_event_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	801	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2932	0	0
T9	14824	26	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	16	0	0
T26	0	14	0	0
T30	0	22	0	0
T34	0	58	0	0
T40	0	26	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	42	0	0
T66	0	30	0	0
T67	0	40	0	0
T68	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	91988	0	0
T9	14824	784	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	318	0	0
T26	0	225	0	0
T30	0	528	0	0
T34	0	1218	0	0
T40	0	585	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1176	0	0
T66	0	756	0	0
T67	0	1400	0	0
T68	0	816	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8376488	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	377	0	0
T9	14824	13	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	8	0	0
T26	0	7	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T66	0	15	0	0
T85	0	17	0	0
T86	0	4	0	0
T87	0	4	0	0
T89	0	4	0	0
T91	0	13	0	0
T217	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	65939	0	0
T30	30644	1071	0	0
T31	13765	0	0	0
T34	23794	2084	0	0
T40	0	228	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	701	0	0
T67	0	2093	0	0
T68	0	1075	0	0
T74	0	482	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T213	0	2032	0	0
T214	0	486	0	0
T215	0	402	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	902	0	0
T30	30644	11	0	0
T31	13765	0	0	0
T34	23794	29	0	0
T40	0	13	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	21	0	0
T67	0	20	0	0
T68	0	24	0	0
T74	0	10	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T213	0	22	0	0
T214	0	5	0	0
T215	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7982944	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7985034	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1486	0	0
T9	14824	13	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	8	0	0
T26	0	7	0	0
T30	0	11	0	0
T34	0	29	0	0
T40	0	13	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	21	0	0
T66	0	15	0	0
T67	0	20	0	0
T68	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1449	0	0
T9	14824	13	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	8	0	0
T26	0	7	0	0
T30	0	11	0	0
T34	0	29	0	0
T40	0	13	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	21	0	0
T66	0	15	0	0
T67	0	20	0	0
T68	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	902	0	0
T30	30644	11	0	0
T31	13765	0	0	0
T34	23794	29	0	0
T40	0	13	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	21	0	0
T67	0	20	0	0
T68	0	24	0	0
T74	0	10	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T213	0	22	0	0
T214	0	5	0	0
T215	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	902	0	0
T30	30644	11	0	0
T31	13765	0	0	0
T34	23794	29	0	0
T40	0	13	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	21	0	0
T67	0	20	0	0
T68	0	24	0	0
T74	0	10	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T213	0	22	0	0
T214	0	5	0	0
T215	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	64939	0	0
T30	30644	1058	0	0
T31	13765	0	0	0
T34	23794	2050	0	0
T40	0	215	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	678	0	0
T67	0	2070	0	0
T68	0	1050	0	0
T74	0	472	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T213	0	2005	0	0
T214	0	481	0	0
T215	0	392	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	801	0	0
T30	30644	9	0	0
T31	13765	0	0	0
T34	23794	24	0	0
T40	0	13	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	19	0	0
T67	0	17	0	0
T68	0	23	0	0
T74	0	10	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T213	0	17	0	0
T214	0	5	0	0
T215	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T33
1	0	Covered	T6,T7,T9
1	1	Covered	T7,T8,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T30
0	1	Covered	T7,T8,T219
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T34,T31
0	1	Covered	T30,T31,T32
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T34,T31
1	-	Covered	T30,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T30
DetectSt	168	Covered	T7,T8,T30
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T30,T34,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T30
DebounceSt->IdleSt	163	Covered	T32,T45,T67
DetectSt->IdleSt	186	Covered	T7,T8,T219
DetectSt->StableSt	191	Covered	T30,T34,T31
IdleSt->DebounceSt	148	Covered	T7,T8,T30
StableSt->IdleSt	206	Covered	T30,T34,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T30
0	1	Covered	T7,T8,T30
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T30
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T45,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T30
DetectSt	-	-	-	-	1	-	-	Covered	T7,T8,T219
DetectSt	-	-	-	-	0	1	-	Covered	T30,T34,T31
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T30
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T30,T34,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	865	0	0
CntIncr_A	9010181	45240	0	0
CntNoWrap_A	9010181	8378555	0	0
DetectStDropOut_A	9010181	54	0	0
DetectedOut_A	9010181	16946	0	0
DetectedPulseOut_A	9010181	351	0	0
DisabledIdleSt_A	9010181	7984721	0	0
DisabledNoDetection_A	9010181	7986329	0	0
EnterDebounceSt_A	9010181	458	0	0
EnterDetectSt_A	9010181	410	0	0
EnterStableSt_A	9010181	351	0	0
PulseIsPulse_A	9010181	351	0	0
StayInStableSt	9010181	16565	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	865	0	0
T7	14517	2	0	0
T8	5132	6	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	8	0	0
T31	0	8	0	0
T32	0	5	0	0
T34	0	2	0	0
T45	0	3	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	4	0	0
T67	0	7	0	0
T83	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	45240	0	0
T7	14517	94	0	0
T8	5132	273	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	164	0	0
T31	0	456	0	0
T32	0	320	0	0
T34	0	51	0	0
T45	0	191	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	88	0	0
T67	0	265	0	0
T83	0	516	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8378555	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	54	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T94	0	1	0	0
T97	0	1	0	0
T102	0	1	0	0
T129	0	3	0	0
T219	0	7	0	0
T220	0	2	0	0
T221	0	8	0	0
T222	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	16946	0	0
T30	30644	175	0	0
T31	13765	22	0	0
T32	0	62	0	0
T34	23794	63	0	0
T45	0	21	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	175	0	0
T67	0	146	0	0
T68	0	39	0	0
T69	0	182	0	0
T83	0	128	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	351	0	0
T30	30644	4	0	0
T31	13765	4	0	0
T32	0	2	0	0
T34	23794	1	0	0
T45	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	2	0	0
T67	0	3	0	0
T68	0	1	0	0
T69	0	3	0	0
T83	0	4	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7984721	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	7065	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7986329	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	7079	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	458	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	4	0	0
T31	0	4	0	0
T32	0	3	0	0
T34	0	1	0	0
T45	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2	0	0
T67	0	4	0	0
T83	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	410	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	0	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	4	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	1	0	0
T45	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2	0	0
T67	0	3	0	0
T83	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	351	0	0
T30	30644	4	0	0
T31	13765	4	0	0
T32	0	2	0	0
T34	23794	1	0	0
T45	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	2	0	0
T67	0	3	0	0
T68	0	1	0	0
T69	0	3	0	0
T83	0	4	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	351	0	0
T30	30644	4	0	0
T31	13765	4	0	0
T32	0	2	0	0
T34	23794	1	0	0
T45	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	2	0	0
T67	0	3	0	0
T68	0	1	0	0
T69	0	3	0	0
T83	0	4	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	16565	0	0
T30	30644	171	0	0
T31	13765	18	0	0
T32	0	60	0	0
T34	23794	61	0	0
T45	0	20	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	173	0	0
T67	0	141	0	0
T68	0	38	0	0
T69	0	179	0	0
T83	0	124	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	320	0	0
T30	30644	4	0	0
T31	13765	4	0	0
T32	0	2	0	0
T34	23794	0	0	0
T45	0	1	0	0
T47	427	0	0	0
T48	502	0	0	0
T54	500	0	0	0
T61	504	0	0	0
T65	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	3	0	0
T83	0	4	0	0
T84	0	6	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T25,T26
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T30,T34
1	1	Covered	T9,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T26
0	1	Covered	T25,T26,T66
1	0	Covered	T90,T217,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T30,T34
0	1	Covered	T9,T30,T34
1	0	Covered	T76,T223

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T30,T34
1	-	Covered	T9,T30,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T26
DetectSt	168	Covered	T9,T25,T26
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T30,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T25,T26
DebounceSt->IdleSt	163	Covered	T209,T210,T211
DetectSt->IdleSt	186	Covered	T25,T26,T66
DetectSt->StableSt	191	Covered	T9,T30,T34
IdleSt->DebounceSt	148	Covered	T9,T25,T26
StableSt->IdleSt	206	Covered	T9,T30,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T25,T26
0	1	Covered	T9,T25,T26
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T25,T26
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T9,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T25,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T209,T210,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T25,T26,T66
DetectSt	-	-	-	-	0	1	-	Covered	T9,T30,T34
DetectSt	-	-	-	-	0	0	-	Covered	T9,T25,T26
StableSt	-	-	-	-	-	-	1	Covered	T9,T30,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T30,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	2813	0	0
CntIncr_A	9010181	91388	0	0
CntNoWrap_A	9010181	8376607	0	0
DetectStDropOut_A	9010181	361	0	0
DetectedOut_A	9010181	78023	0	0
DetectedPulseOut_A	9010181	897	0	0
DisabledIdleSt_A	9010181	7969813	0	0
DisabledNoDetection_A	9010181	7971898	0	0
EnterDebounceSt_A	9010181	1424	0	0
EnterDetectSt_A	9010181	1389	0	0
EnterStableSt_A	9010181	897	0	0
PulseIsPulse_A	9010181	897	0	0
StayInStableSt	9010181	77023	0	0
gen_high_event_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	770	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2813	0	0
T9	14824	12	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	48	0	0
T26	0	48	0	0
T30	0	44	0	0
T34	0	30	0	0
T40	0	56	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	30	0	0
T66	0	34	0	0
T67	0	26	0	0
T68	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	91388	0	0
T9	14824	270	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	963	0	0
T26	0	789	0	0
T30	0	1496	0	0
T34	0	570	0	0
T40	0	1344	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	690	0	0
T66	0	857	0	0
T67	0	845	0	0
T68	0	312	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8376607	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	361	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T19	492	0	0	0
T20	4408	0	0	0
T25	4620	24	0	0
T26	0	24	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T60	502	0	0	0
T66	0	17	0	0
T75	0	4	0	0
T85	0	30	0	0
T86	0	29	0	0
T89	0	15	0	0
T90	0	14	0	0
T91	0	7	0	0
T217	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	78023	0	0
T9	14824	961	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	1289	0	0
T34	0	617	0	0
T40	0	1685	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1286	0	0
T67	0	1878	0	0
T68	0	283	0	0
T74	0	1396	0	0
T213	0	804	0	0
T214	0	500	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	897	0	0
T9	14824	6	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	22	0	0
T34	0	15	0	0
T40	0	28	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	15	0	0
T67	0	13	0	0
T68	0	13	0	0
T74	0	10	0	0
T213	0	14	0	0
T214	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7969813	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7971898	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1424	0	0
T9	14824	6	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	24	0	0
T26	0	24	0	0
T30	0	22	0	0
T34	0	15	0	0
T40	0	28	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	15	0	0
T66	0	17	0	0
T67	0	13	0	0
T68	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1389	0	0
T9	14824	6	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	24	0	0
T26	0	24	0	0
T30	0	22	0	0
T34	0	15	0	0
T40	0	28	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	15	0	0
T66	0	17	0	0
T67	0	13	0	0
T68	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	897	0	0
T9	14824	6	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	22	0	0
T34	0	15	0	0
T40	0	28	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	15	0	0
T67	0	13	0	0
T68	0	13	0	0
T74	0	10	0	0
T213	0	14	0	0
T214	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	897	0	0
T9	14824	6	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	22	0	0
T34	0	15	0	0
T40	0	28	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	15	0	0
T67	0	13	0	0
T68	0	13	0	0
T74	0	10	0	0
T213	0	14	0	0
T214	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	77023	0	0
T9	14824	952	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	1259	0	0
T34	0	600	0	0
T40	0	1655	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1271	0	0
T67	0	1863	0	0
T68	0	270	0	0
T74	0	1386	0	0
T213	0	787	0	0
T214	0	495	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	770	0	0
T9	14824	3	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	14	0	0
T34	0	13	0	0
T40	0	26	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	15	0	0
T67	0	11	0	0
T68	0	13	0	0
T74	0	10	0	0
T213	0	11	0	0
T214	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T7,T9
1	1	Covered	T7,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T31,T83,T224
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T65,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T9
1	-	Covered	T7,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T9
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T33,T32,T83
DetectSt->IdleSt	186	Covered	T31,T83,T224
DetectSt->StableSt	191	Covered	T7,T8,T9
IdleSt->DebounceSt	148	Covered	T7,T8,T9
StableSt->IdleSt	206	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T32,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T31,T83,T224
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	818	0	0
CntIncr_A	9010181	47746	0	0
CntNoWrap_A	9010181	8378602	0	0
DetectStDropOut_A	9010181	55	0	0
DetectedOut_A	9010181	16064	0	0
DetectedPulseOut_A	9010181	324	0	0
DisabledIdleSt_A	9010181	7993184	0	0
DisabledNoDetection_A	9010181	7994813	0	0
EnterDebounceSt_A	9010181	436	0	0
EnterDetectSt_A	9010181	383	0	0
EnterStableSt_A	9010181	324	0	0
PulseIsPulse_A	9010181	324	0	0
StayInStableSt	9010181	15711	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	818	0	0
T7	14517	2	0	0
T8	5132	6	0	0
T9	14824	2	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	12	0	0
T31	0	2	0	0
T32	0	5	0	0
T33	0	23	0	0
T34	0	4	0	0
T37	0	16	0	0
T40	0	4	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	47746	0	0
T7	14517	90	0	0
T8	5132	246	0	0
T9	14824	56	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	324	0	0
T31	0	119	0	0
T32	0	254	0	0
T33	0	2616	0	0
T34	0	74	0	0
T37	0	1416	0	0
T40	0	100	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8378602	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8279	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	55	0	0
T23	649	0	0	0
T31	13765	1	0	0
T54	500	0	0	0
T61	504	0	0	0
T62	506	0	0	0
T63	501	0	0	0
T64	522	0	0	0
T83	0	6	0	0
T92	0	1	0	0
T96	0	1	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T102	0	4	0	0
T219	0	6	0	0
T221	0	4	0	0
T224	0	1	0	0
T225	0	3	0	0
T226	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	16064	0	0
T7	14517	5	0	0
T8	5132	27	0	0
T9	14824	35	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	174	0	0
T32	0	128	0	0
T33	0	186	0	0
T34	0	155	0	0
T37	0	67	0	0
T40	0	102	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	324	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	6	0	0
T32	0	2	0	0
T33	0	11	0	0
T34	0	2	0	0
T37	0	8	0	0
T40	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7993184	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	7065	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7994813	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	7079	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	436	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	3	0	0
T33	0	12	0	0
T34	0	2	0	0
T37	0	8	0	0
T40	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	383	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	11	0	0
T34	0	2	0	0
T37	0	8	0	0
T40	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	324	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	6	0	0
T32	0	2	0	0
T33	0	11	0	0
T34	0	2	0	0
T37	0	8	0	0
T40	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	324	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	6	0	0
T32	0	2	0	0
T33	0	11	0	0
T34	0	2	0	0
T37	0	8	0	0
T40	0	2	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	15711	0	0
T7	14517	4	0	0
T8	5132	24	0	0
T9	14824	34	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	162	0	0
T32	0	126	0	0
T33	0	175	0	0
T34	0	151	0	0
T37	0	59	0	0
T40	0	98	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	88	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	292	0	0
T7	14517	1	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T32	0	2	0	0
T33	0	11	0	0
T37	0	8	0	0
T45	0	1	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T67	0	1	0	0
T84	0	3	0	0
T227	0	6	0	0