Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T25,T26
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T25,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T30,T34
1	1	Covered	T9,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T26
0	1	Covered	T25,T26,T66
1	0	Covered	T68,T218,T228

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T30,T34
0	1	Covered	T9,T30,T34
1	0	Covered	T229

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T30,T34
1	-	Covered	T9,T30,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T26
DetectSt	168	Covered	T9,T25,T26
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T30,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T25,T26
DebounceSt->IdleSt	163	Covered	T209,T210,T211
DetectSt->IdleSt	186	Covered	T25,T26,T66
DetectSt->StableSt	191	Covered	T9,T30,T34
IdleSt->DebounceSt	148	Covered	T9,T25,T26
StableSt->IdleSt	206	Covered	T9,T30,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T25,T26
0	1	Covered	T9,T25,T26
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T25,T26
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T9,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T25,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T209,T210,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T25,T26,T66
DetectSt	-	-	-	-	0	1	-	Covered	T9,T30,T34
DetectSt	-	-	-	-	0	0	-	Covered	T9,T25,T26
StableSt	-	-	-	-	-	-	1	Covered	T9,T30,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T30,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	2844	0	0
CntIncr_A	9010181	91501	0	0
CntNoWrap_A	9010181	8376576	0	0
DetectStDropOut_A	9010181	367	0	0
DetectedOut_A	9010181	64326	0	0
DetectedPulseOut_A	9010181	853	0	0
DisabledIdleSt_A	9010181	7983266	0	0
DisabledNoDetection_A	9010181	7985358	0	0
EnterDebounceSt_A	9010181	1443	0	0
EnterDetectSt_A	9010181	1403	0	0
EnterStableSt_A	9010181	853	0	0
PulseIsPulse_A	9010181	853	0	0
StayInStableSt	9010181	63377	0	0
gen_high_event_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	754	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	2844	0	0
T9	14824	16	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	44	0	0
T26	0	48	0	0
T30	0	18	0	0
T34	0	26	0	0
T40	0	10	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	60	0	0
T66	0	50	0	0
T67	0	26	0	0
T68	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	91501	0	0
T9	14824	400	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	878	0	0
T26	0	789	0	0
T30	0	630	0	0
T34	0	416	0	0
T40	0	195	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	1680	0	0
T66	0	1280	0	0
T67	0	689	0	0
T68	0	1055	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8376576	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	367	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T19	492	0	0	0
T20	4408	0	0	0
T25	4620	22	0	0
T26	0	24	0	0
T39	553	0	0	0
T41	443	0	0	0
T51	633	0	0	0
T60	502	0	0	0
T66	0	25	0	0
T85	0	28	0	0
T86	0	12	0	0
T89	0	7	0	0
T91	0	28	0	0
T198	0	2	0	0
T218	0	3	0	0
T230	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	64326	0	0
T9	14824	1145	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	354	0	0
T34	0	673	0	0
T40	0	116	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2046	0	0
T67	0	2034	0	0
T74	0	1125	0	0
T87	0	522	0	0
T213	0	69	0	0
T214	0	4915	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	853	0	0
T9	14824	8	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	9	0	0
T34	0	13	0	0
T40	0	5	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	30	0	0
T67	0	13	0	0
T74	0	7	0	0
T87	0	11	0	0
T213	0	2	0	0
T214	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7983266	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8281	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7985358	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1443	0	0
T9	14824	8	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	22	0	0
T26	0	24	0	0
T30	0	9	0	0
T34	0	13	0	0
T40	0	5	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	30	0	0
T66	0	25	0	0
T67	0	13	0	0
T68	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	1403	0	0
T9	14824	8	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	22	0	0
T26	0	24	0	0
T30	0	9	0	0
T34	0	13	0	0
T40	0	5	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	30	0	0
T66	0	25	0	0
T67	0	13	0	0
T68	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	853	0	0
T9	14824	8	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	9	0	0
T34	0	13	0	0
T40	0	5	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	30	0	0
T67	0	13	0	0
T74	0	7	0	0
T87	0	11	0	0
T213	0	2	0	0
T214	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	853	0	0
T9	14824	8	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	9	0	0
T34	0	13	0	0
T40	0	5	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	30	0	0
T67	0	13	0	0
T74	0	7	0	0
T87	0	11	0	0
T213	0	2	0	0
T214	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	63377	0	0
T9	14824	1133	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	342	0	0
T34	0	659	0	0
T40	0	111	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	2013	0	0
T67	0	2019	0	0
T74	0	1118	0	0
T87	0	509	0	0
T213	0	67	0	0
T214	0	4875	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	754	0	0
T9	14824	4	0	0
T10	557799	0	0	0
T11	483	0	0	0
T12	1206	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	6	0	0
T34	0	12	0	0
T40	0	5	0	0
T41	443	0	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	27	0	0
T67	0	11	0	0
T74	0	7	0	0
T87	0	9	0	0
T213	0	2	0	0
T214	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T7,T9
1	1	Covered	T7,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T31,T84,T231
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T71,T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T9
1	-	Covered	T7,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T9
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T32,T65,T83
DetectSt->IdleSt	186	Covered	T31,T84,T231
DetectSt->StableSt	191	Covered	T7,T8,T9
IdleSt->DebounceSt	148	Covered	T7,T8,T9
StableSt->IdleSt	206	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T65,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T31,T84,T231
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9010181	915	0	0
CntIncr_A	9010181	54176	0	0
CntNoWrap_A	9010181	8378505	0	0
DetectStDropOut_A	9010181	49	0	0
DetectedOut_A	9010181	15787	0	0
DetectedPulseOut_A	9010181	385	0	0
DisabledIdleSt_A	9010181	7989903	0	0
DisabledNoDetection_A	9010181	7991504	0	0
EnterDebounceSt_A	9010181	477	0	0
EnterDetectSt_A	9010181	439	0	0
EnterStableSt_A	9010181	385	0	0
PulseIsPulse_A	9010181	385	0	0
StayInStableSt	9010181	15374	0	0
gen_high_level_sva.HighLevelEvent_A	9010181	8381696	0	0
gen_not_sticky_sva.StableStDropOut_A	9010181	353	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	915	0	0
T7	14517	8	0	0
T8	5132	6	0	0
T9	14824	8	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	4	0	0
T31	0	4	0	0
T32	0	16	0	0
T33	0	8	0	0
T34	0	2	0	0
T37	0	16	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	54176	0	0
T7	14517	356	0	0
T8	5132	210	0	0
T9	14824	260	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	96	0	0
T31	0	238	0	0
T32	0	1153	0	0
T33	0	708	0	0
T34	0	60	0	0
T37	0	1320	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8378505	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	8273	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	49	0	0
T23	649	0	0	0
T31	13765	2	0	0
T54	500	0	0	0
T61	504	0	0	0
T62	506	0	0	0
T63	501	0	0	0
T64	522	0	0	0
T84	0	6	0	0
T94	0	4	0	0
T99	407	0	0	0
T100	423	0	0	0
T101	620	0	0	0
T102	0	3	0	0
T231	0	1	0	0
T232	0	1	0	0
T233	0	2	0	0
T234	0	5	0	0
T235	0	1	0	0
T236	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	15787	0	0
T7	14517	23	0	0
T8	5132	64	0	0
T9	14824	103	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	75	0	0
T32	0	68	0	0
T33	0	272	0	0
T34	0	57	0	0
T37	0	163	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	251	0	0
T83	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	385	0	0
T7	14517	4	0	0
T8	5132	3	0	0
T9	14824	4	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	2	0	0
T32	0	7	0	0
T33	0	4	0	0
T34	0	1	0	0
T37	0	8	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	3	0	0
T83	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7989903	0	0
T1	918	517	0	0
T2	682	281	0	0
T3	670	269	0	0
T4	460	59	0	0
T5	402	1	0	0
T6	1945	342	0	0
T7	14517	7065	0	0
T13	427	26	0	0
T14	526	125	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	7991504	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	7079	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	477	0	0
T7	14517	4	0	0
T8	5132	3	0	0
T9	14824	4	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	9	0	0
T33	0	4	0	0
T34	0	1	0	0
T37	0	8	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	439	0	0
T7	14517	4	0	0
T8	5132	3	0	0
T9	14824	4	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	7	0	0
T33	0	4	0	0
T34	0	1	0	0
T37	0	8	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	385	0	0
T7	14517	4	0	0
T8	5132	3	0	0
T9	14824	4	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	2	0	0
T32	0	7	0	0
T33	0	4	0	0
T34	0	1	0	0
T37	0	8	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	3	0	0
T83	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	385	0	0
T7	14517	4	0	0
T8	5132	3	0	0
T9	14824	4	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	2	0	0
T32	0	7	0	0
T33	0	4	0	0
T34	0	1	0	0
T37	0	8	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	3	0	0
T83	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	15374	0	0
T7	14517	19	0	0
T8	5132	61	0	0
T9	14824	96	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	73	0	0
T32	0	61	0	0
T33	0	268	0	0
T34	0	56	0	0
T37	0	155	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	248	0	0
T83	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	8381696	0	0
T1	918	518	0	0
T2	682	282	0	0
T3	670	270	0	0
T4	460	60	0	0
T5	402	2	0	0
T6	1945	345	0	0
T7	14517	8297	0	0
T13	427	27	0	0
T14	526	126	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9010181	353	0	0
T7	14517	4	0	0
T8	5132	3	0	0
T9	14824	1	0	0
T10	557799	0	0	0
T11	483	0	0	0
T24	460	0	0	0
T25	4620	0	0	0
T30	0	2	0	0
T32	0	7	0	0
T33	0	4	0	0
T34	0	1	0	0
T37	0	8	0	0
T51	633	0	0	0
T58	409	0	0	0
T59	4402	0	0	0
T65	0	3	0	0
T83	0	6	0	0