Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1224288996 13121 0 0
auto_block_debounce_ctl_rd_A 1224288996 2076 0 0
auto_block_out_ctl_rd_A 1224288996 2732 0 0
com_det_ctl_0_rd_A 1224288996 3819 0 0
com_det_ctl_1_rd_A 1224288996 3852 0 0
com_det_ctl_2_rd_A 1224288996 3610 0 0
com_det_ctl_3_rd_A 1224288996 3926 0 0
com_out_ctl_0_rd_A 1224288996 4354 0 0
com_out_ctl_1_rd_A 1224288996 4400 0 0
com_out_ctl_2_rd_A 1224288996 4213 0 0
com_out_ctl_3_rd_A 1224288996 4305 0 0
com_pre_det_ctl_0_rd_A 1224288996 1602 0 0
com_pre_det_ctl_1_rd_A 1224288996 1640 0 0
com_pre_det_ctl_2_rd_A 1224288996 1639 0 0
com_pre_det_ctl_3_rd_A 1224288996 1699 0 0
com_pre_sel_ctl_0_rd_A 1224288996 4536 0 0
com_pre_sel_ctl_1_rd_A 1224288996 4525 0 0
com_pre_sel_ctl_2_rd_A 1224288996 4396 0 0
com_pre_sel_ctl_3_rd_A 1224288996 4396 0 0
com_sel_ctl_0_rd_A 1224288996 4615 0 0
com_sel_ctl_1_rd_A 1224288996 4494 0 0
com_sel_ctl_2_rd_A 1224288996 4625 0 0
com_sel_ctl_3_rd_A 1224288996 4581 0 0
ec_rst_ctl_rd_A 1224288996 2544 0 0
intr_enable_rd_A 1224288996 2627 0 0
key_intr_ctl_rd_A 1224288996 4448 0 0
key_intr_debounce_ctl_rd_A 1224288996 1658 0 0
key_invert_ctl_rd_A 1224288996 5316 0 0
pin_allowed_ctl_rd_A 1224288996 6527 0 0
pin_out_ctl_rd_A 1224288996 4612 0 0
pin_out_value_rd_A 1224288996 4887 0 0
regwen_rd_A 1224288996 2074 0 0
ulp_ac_debounce_ctl_rd_A 1224288996 1854 0 0
ulp_ctl_rd_A 1224288996 1814 0 0
ulp_lid_debounce_ctl_rd_A 1224288996 1825 0 0
ulp_pwrb_debounce_ctl_rd_A 1224288996 1843 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 13121 0 0
T7 696967 9 0 0
T8 251477 0 0 0
T9 148244 0 0 0
T10 251482 0 0 0
T11 236593 0 0 0
T20 0 4 0 0
T24 57611 0 0 0
T25 577675 0 0 0
T35 0 10 0 0
T37 0 22 0 0
T38 0 13 0 0
T45 0 4 0 0
T51 79164 0 0 0
T58 100312 0 0 0
T59 180504 0 0 0
T150 0 10 0 0
T205 0 4 0 0
T263 0 3 0 0
T264 0 32 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 2076 0 0
T20 104268 8 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 12 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 61 0 0
T81 0 13 0 0
T111 0 10 0 0
T153 0 12 0 0
T174 0 31 0 0
T265 0 11 0 0
T266 0 10 0 0
T267 0 12 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 2732 0 0
T20 104268 22 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 7 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T44 0 7 0 0
T45 0 16 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T81 0 12 0 0
T111 0 16 0 0
T153 0 15 0 0
T265 0 6 0 0
T266 0 10 0 0
T267 0 5 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 3819 0 0
T20 104268 12 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 64 0 0
T33 480080 0 0 0
T34 0 82 0 0
T38 709006 0 0 0
T45 0 8 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 76 0 0
T68 0 31 0 0
T74 0 23 0 0
T153 0 8 0 0
T227 0 60 0 0
T268 0 63 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 3852 0 0
T20 104268 12 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 31 0 0
T33 480080 0 0 0
T34 0 71 0 0
T38 709006 0 0 0
T45 0 7 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 71 0 0
T68 0 11 0 0
T74 0 28 0 0
T153 0 11 0 0
T227 0 82 0 0
T268 0 96 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 3610 0 0
T20 104268 8 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 30 0 0
T33 480080 0 0 0
T34 0 77 0 0
T38 709006 0 0 0
T45 0 5 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 33 0 0
T68 0 13 0 0
T74 0 16 0 0
T153 0 25 0 0
T227 0 63 0 0
T268 0 35 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 3926 0 0
T20 104268 19 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 42 0 0
T33 480080 0 0 0
T34 0 65 0 0
T38 709006 0 0 0
T45 0 4 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 76 0 0
T68 0 36 0 0
T74 0 22 0 0
T153 0 27 0 0
T227 0 71 0 0
T268 0 50 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4354 0 0
T20 104268 8 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 54 0 0
T33 480080 0 0 0
T34 0 71 0 0
T38 709006 0 0 0
T45 0 9 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 64 0 0
T68 0 25 0 0
T74 0 18 0 0
T153 0 15 0 0
T227 0 68 0 0
T268 0 66 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4400 0 0
T20 104268 11 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 30 0 0
T33 480080 0 0 0
T34 0 67 0 0
T38 709006 0 0 0
T45 0 16 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 68 0 0
T68 0 11 0 0
T74 0 24 0 0
T153 0 13 0 0
T227 0 52 0 0
T268 0 63 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4213 0 0
T20 104268 18 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 65 0 0
T33 480080 0 0 0
T34 0 58 0 0
T38 709006 0 0 0
T45 0 7 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 55 0 0
T68 0 28 0 0
T74 0 17 0 0
T153 0 8 0 0
T227 0 86 0 0
T268 0 62 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4305 0 0
T20 104268 12 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 40 0 0
T33 480080 0 0 0
T34 0 88 0 0
T38 709006 0 0 0
T45 0 19 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 66 0 0
T68 0 23 0 0
T74 0 48 0 0
T153 0 11 0 0
T227 0 68 0 0
T268 0 50 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1602 0 0
T20 104268 6 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 35 0 0
T121 0 14 0 0
T124 0 18 0 0
T153 0 17 0 0
T174 0 25 0 0
T231 0 7 0 0
T269 0 17 0 0
T270 0 21 0 0
T271 0 10 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1640 0 0
T20 104268 20 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 39 0 0
T121 0 17 0 0
T124 0 39 0 0
T153 0 11 0 0
T174 0 23 0 0
T231 0 25 0 0
T269 0 23 0 0
T270 0 12 0 0
T271 0 16 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1639 0 0
T20 104268 16 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 3 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 28 0 0
T124 0 21 0 0
T153 0 9 0 0
T174 0 25 0 0
T231 0 13 0 0
T269 0 3 0 0
T270 0 14 0 0
T271 0 8 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1699 0 0
T20 104268 11 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 5 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 36 0 0
T124 0 22 0 0
T153 0 18 0 0
T174 0 24 0 0
T231 0 24 0 0
T269 0 14 0 0
T270 0 21 0 0
T271 0 22 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4536 0 0
T20 104268 1 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 43 0 0
T33 480080 0 0 0
T34 0 60 0 0
T38 709006 0 0 0
T45 0 4 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 36 0 0
T68 0 23 0 0
T74 0 45 0 0
T153 0 25 0 0
T227 0 69 0 0
T268 0 72 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4525 0 0
T20 104268 4 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 59 0 0
T33 480080 0 0 0
T34 0 69 0 0
T38 709006 0 0 0
T45 0 7 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 76 0 0
T68 0 5 0 0
T74 0 20 0 0
T153 0 22 0 0
T227 0 60 0 0
T268 0 59 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4396 0 0
T20 104268 10 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 35 0 0
T33 480080 0 0 0
T34 0 70 0 0
T38 709006 0 0 0
T45 0 20 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 68 0 0
T68 0 2 0 0
T74 0 20 0 0
T153 0 16 0 0
T227 0 81 0 0
T268 0 62 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4396 0 0
T20 104268 5 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 36 0 0
T33 480080 0 0 0
T34 0 77 0 0
T38 709006 0 0 0
T45 0 8 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 32 0 0
T68 0 21 0 0
T74 0 39 0 0
T153 0 13 0 0
T227 0 81 0 0
T268 0 59 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4615 0 0
T20 104268 14 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 30 0 0
T33 480080 0 0 0
T34 0 63 0 0
T38 709006 0 0 0
T45 0 10 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 50 0 0
T68 0 26 0 0
T74 0 20 0 0
T153 0 22 0 0
T227 0 62 0 0
T268 0 76 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4494 0 0
T20 104268 10 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 61 0 0
T33 480080 0 0 0
T34 0 64 0 0
T38 709006 0 0 0
T45 0 21 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 53 0 0
T68 0 7 0 0
T74 0 23 0 0
T153 0 14 0 0
T227 0 68 0 0
T268 0 74 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4625 0 0
T20 104268 13 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 41 0 0
T33 480080 0 0 0
T34 0 51 0 0
T38 709006 0 0 0
T45 0 9 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 59 0 0
T68 0 11 0 0
T74 0 27 0 0
T153 0 9 0 0
T227 0 80 0 0
T268 0 67 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4581 0 0
T20 104268 13 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 44 0 0
T33 480080 0 0 0
T34 0 77 0 0
T38 709006 0 0 0
T45 0 4 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T67 0 57 0 0
T68 0 27 0 0
T74 0 24 0 0
T153 0 19 0 0
T227 0 84 0 0
T268 0 93 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 2544 0 0
T20 104268 12 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 17 0 0
T33 480080 0 0 0
T34 0 34 0 0
T38 709006 0 0 0
T45 0 10 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T66 0 1 0 0
T67 0 14 0 0
T68 0 5 0 0
T153 0 21 0 0
T227 0 43 0 0
T272 0 6 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 2627 0 0
T20 104268 14 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T32 0 9 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 8 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 22 0 0
T124 0 57 0 0
T153 0 20 0 0
T174 0 59 0 0
T231 0 38 0 0
T269 0 91 0 0
T270 0 43 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4448 0 0
T3 105965 2 0 0
T6 933651 0 0 0
T7 696967 0 0 0
T8 251477 0 0 0
T9 148244 0 0 0
T10 251482 0 0 0
T20 0 17 0 0
T24 57611 0 0 0
T25 577675 0 0 0
T36 0 4 0 0
T45 0 2 0 0
T58 100312 0 0 0
T59 180504 0 0 0
T79 0 30 0 0
T119 0 5 0 0
T124 0 30 0 0
T149 0 6 0 0
T153 0 11 0 0
T174 0 25 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1658 0 0
T20 104268 13 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 2 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 37 0 0
T124 0 18 0 0
T153 0 15 0 0
T174 0 26 0 0
T231 0 10 0 0
T269 0 7 0 0
T270 0 21 0 0
T271 0 18 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 5316 0 0
T20 104268 19 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 6 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T55 0 40 0 0
T57 0 67 0 0
T60 251059 0 0 0
T79 0 131 0 0
T124 0 182 0 0
T153 0 170 0 0
T174 0 152 0 0
T273 0 69 0 0
T274 0 63 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 6527 0 0
T20 104268 161 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T63 0 45 0 0
T79 0 24 0 0
T153 0 22 0 0
T172 0 26 0 0
T174 0 82 0 0
T274 0 60 0 0
T275 0 63 0 0
T276 0 68 0 0
T277 0 54 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4612 0 0
T20 104268 152 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 17 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T63 0 44 0 0
T153 0 13 0 0
T172 0 29 0 0
T174 0 74 0 0
T274 0 78 0 0
T275 0 52 0 0
T276 0 76 0 0
T277 0 39 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 4887 0 0
T20 104268 148 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T45 0 2 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T63 0 67 0 0
T153 0 11 0 0
T172 0 25 0 0
T174 0 101 0 0
T274 0 75 0 0
T275 0 63 0 0
T276 0 80 0 0
T277 0 33 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 2074 0 0
T20 104268 10 0 0
T21 154369 0 0 0
T22 343058 0 0 0
T26 534023 0 0 0
T30 597551 0 0 0
T33 480080 0 0 0
T38 709006 0 0 0
T46 51694 0 0 0
T47 40662 0 0 0
T60 251059 0 0 0
T79 0 38 0 0
T121 0 29 0 0
T124 0 18 0 0
T153 0 16 0 0
T174 0 20 0 0
T231 0 21 0 0
T269 0 23 0 0
T270 0 14 0 0
T271 0 21 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1854 0 0
T1 121801 15 0 0
T2 57112 0 0 0
T3 105965 0 0 0
T5 188873 0 0 0
T6 933651 0 0 0
T7 696967 0 0 0
T8 251477 0 0 0
T10 0 13 0 0
T13 32033 0 0 0
T14 68428 0 0 0
T15 201290 0 0 0
T20 0 12 0 0
T45 0 5 0 0
T52 0 5 0 0
T79 0 54 0 0
T153 0 19 0 0
T174 0 44 0 0
T278 0 11 0 0
T279 0 3 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1814 0 0
T1 121801 13 0 0
T2 57112 0 0 0
T3 105965 0 0 0
T5 188873 0 0 0
T6 933651 0 0 0
T7 696967 0 0 0
T8 251477 0 0 0
T10 0 13 0 0
T13 32033 0 0 0
T14 68428 0 0 0
T15 201290 0 0 0
T20 0 9 0 0
T45 0 1 0 0
T79 0 48 0 0
T124 0 54 0 0
T153 0 14 0 0
T174 0 31 0 0
T278 0 8 0 0
T279 0 2 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1825 0 0
T1 121801 9 0 0
T2 57112 0 0 0
T3 105965 0 0 0
T5 188873 0 0 0
T6 933651 0 0 0
T7 696967 0 0 0
T8 251477 0 0 0
T10 0 7 0 0
T13 32033 0 0 0
T14 68428 0 0 0
T15 201290 0 0 0
T20 0 14 0 0
T45 0 8 0 0
T52 0 8 0 0
T79 0 37 0 0
T153 0 25 0 0
T174 0 29 0 0
T278 0 8 0 0
T279 0 4 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1224288996 1843 0 0
T1 121801 7 0 0
T2 57112 0 0 0
T3 105965 0 0 0
T5 188873 0 0 0
T6 933651 0 0 0
T7 696967 0 0 0
T8 251477 0 0 0
T10 0 6 0 0
T13 32033 0 0 0
T14 68428 0 0 0
T15 201290 0 0 0
T20 0 5 0 0
T45 0 6 0 0
T52 0 7 0 0
T79 0 44 0 0
T153 0 25 0 0
T174 0 28 0 0
T278 0 19 0 0
T279 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%