Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T1,T7
1	0	Covered	T4,T1,T7
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T1,T7
1	0	Covered	T1,T10,T12
1	1	Covered	T4,T1,T7

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	206887	0	0
SrcPulseCheck_M	2147483647	209360	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	206887
T1	122719	0
T2	57794	0
T3	106635	0
T4	226251	2
T5	189275	0
T6	935596	0
T7	1408451	8
T8	251477	3
T9	0	15
T11	0	2
T13	32460	0
T14	68954	0
T15	201692	0
T21	309972	16
T22	687544	14
T23	0	16
T24	0	2
T25	0	3
T26	1076590	1
T30	1256390	0
T32	0	22
T33	1415830	45
T34	642438	0
T35	0	18
T37	0	18
T38	1431618	2
T41	0	2
T42	0	14
T43	0	24
T44	0	16
T45	0	30
T46	104560	0
T47	82178	0
T48	247634	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	209360
T1	122719	0
T2	57794	0
T3	106635	0
T4	226251	2
T5	189275	0
T6	935596	0
T7	726001	8
T8	5132	3
T9	0	15
T11	0	2
T13	32460	0
T14	68954	0
T15	201692	0
T21	309972	16
T22	687544	14
T23	0	16
T24	0	2
T25	0	3
T26	1076590	1
T30	1256390	0
T32	0	22
T33	1415830	45
T34	642438	0
T35	0	18
T37	0	18
T38	1431618	2
T41	0	2
T42	0	14
T43	0	24
T44	0	16
T45	0	30
T46	104560	0
T47	82178	0
T48	247634	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T29,T16,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T29,T16,T17
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1749	0	0
SrcPulseCheck_M	1224288996	1824	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1749
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	4
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T38	0	3
T41	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1824
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	4
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T38	0	3
T41	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T29,T16,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T29,T16,T17
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1813	0	0
SrcPulseCheck_M	9241877	1813	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1813
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	4
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T38	0	3
T41	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1813
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	4
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T38	0	3
T41	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	795	0	0
SrcPulseCheck_M	1224288996	865	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	795
T1	918	3
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	3
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	865
T1	121801	3
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	3
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	856	0	0
SrcPulseCheck_M	9241877	856	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	856
T1	121801	3
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	3
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	856
T1	918	3
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	3
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	807	0	0
SrcPulseCheck_M	1224288996	880	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	807
T1	918	3
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	3
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	880
T1	121801	3
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	3
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	872	0	0
SrcPulseCheck_M	9241877	872	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	872
T1	121801	3
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	3
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	872
T1	918	3
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	3
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	820	0	0
SrcPulseCheck_M	1224288996	890	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	820
T1	918	3
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	3
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	890
T1	121801	3
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	3
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	881	0	0
SrcPulseCheck_M	9241877	881	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	881
T1	121801	3
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	3
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	881
T1	918	3
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	3
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T33	0	1
T35	0	2
T37	0	2
T38	0	2
T46	0	1
T52	0	3
T53	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	844	0	0
SrcPulseCheck_M	1224288996	916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	844
T1	918	4
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	4
T12	0	4
T13	427	0
T14	526	0
T15	402	0
T35	0	2
T37	0	2
T38	0	4
T52	0	4
T53	0	4
T69	0	2
T70	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	916
T1	121801	4
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	4
T12	0	4
T13	32033	0
T14	68428	0
T15	201290	0
T35	0	2
T37	0	2
T38	0	4
T52	0	4
T53	0	4
T69	0	2
T70	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	907	0	0
SrcPulseCheck_M	9241877	907	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	907
T1	121801	4
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	0
T8	251477	0
T10	0	4
T12	0	4
T13	32033	0
T14	68428	0
T15	201290	0
T35	0	2
T37	0	2
T38	0	4
T52	0	4
T53	0	4
T69	0	2
T70	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	907
T1	918	4
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	0
T8	5132	0
T10	0	4
T12	0	4
T13	427	0
T14	526	0
T15	402	0
T35	0	2
T37	0	2
T38	0	4
T52	0	4
T53	0	4
T69	0	2
T70	0	4

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T8,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T8,T10
1	1	Covered	T1,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1123	0	0
SrcPulseCheck_M	1224288996	1197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1123
T1	918	2
T2	682	0
T3	670	0
T5	402	0
T6	1945	0
T7	14517	2
T8	5132	3
T9	0	1
T10	0	2
T12	0	2
T13	427	0
T14	526	0
T15	402	0
T30	0	5
T33	0	13
T34	0	5
T38	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1197
T1	121801	2
T2	57112	0
T3	105965	0
T5	188873	0
T6	933651	0
T7	696967	2
T8	251477	3
T9	0	1
T10	0	2
T12	0	2
T13	32033	0
T14	68428	0
T15	201290	0
T30	0	5
T33	0	13
T34	0	5
T38	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T19
1	1	Covered	T6,T7,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T19
1	1	Covered	T6,T7,T19

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	2568	0	0
SrcPulseCheck_M	1224288996	2638	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	2568
T6	1945	20
T7	14517	60
T8	5132	0
T9	14824	0
T10	557799	0
T19	0	20
T24	460	0
T25	4620	0
T35	0	20
T37	0	40
T38	0	40
T51	633	0
T54	0	20
T55	0	20
T56	0	20
T57	0	20
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	2638
T6	933651	20
T7	696967	60
T8	251477	0
T9	148244	0
T10	251482	0
T19	0	20
T24	57611	0
T25	577675	0
T35	0	20
T37	0	40
T38	0	40
T51	79164	0
T54	0	20
T55	0	20
T56	0	20
T57	0	20
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T19
1	1	Covered	T6,T7,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T19
1	1	Covered	T6,T7,T19

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	2632	0	0
SrcPulseCheck_M	9241877	2632	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	2632
T6	933651	20
T7	696967	60
T8	251477	0
T9	148244	0
T10	251482	0
T19	0	20
T24	57611	0
T25	577675	0
T35	0	20
T37	0	40
T38	0	40
T51	79164	0
T54	0	20
T55	0	20
T56	0	20
T57	0	20
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	2632
T6	1945	20
T7	14517	60
T8	5132	0
T9	14824	0
T10	557799	0
T19	0	20
T24	460	0
T25	4620	0
T35	0	20
T37	0	40
T38	0	40
T51	633	0
T54	0	20
T55	0	20
T56	0	20
T57	0	20
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T6,T7
1	0	Covered	T14,T6,T7
1	1	Covered	T14,T7,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T6,T7
1	0	Covered	T14,T7,T20
1	1	Covered	T14,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	5685	0	0
SrcPulseCheck_M	1224288996	5761	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	5685
T3	670	0
T6	1945	1
T7	14517	63
T8	5132	0
T9	14824	0
T14	526	20
T15	402	0
T19	0	1
T20	0	60
T24	460	0
T38	0	42
T48	0	20
T54	0	1
T58	409	0
T59	4402	0
T60	0	20
T61	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	5761
T3	105965	0
T6	933651	1
T7	696967	63
T8	251477	0
T9	148244	0
T14	68428	20
T15	201290	0
T19	0	1
T20	0	60
T24	57611	0
T38	0	42
T48	0	20
T54	0	1
T58	100312	0
T59	180504	0
T60	0	20
T61	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T6,T7
1	0	Covered	T14,T6,T7
1	1	Covered	T14,T7,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T6,T7
1	0	Covered	T14,T7,T20
1	1	Covered	T14,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	5748	0	0
SrcPulseCheck_M	9241877	5748	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	5748
T3	105965	0
T6	933651	1
T7	696967	63
T8	251477	0
T9	148244	0
T14	68428	20
T15	201290	0
T19	0	1
T20	0	60
T24	57611	0
T38	0	42
T48	0	20
T54	0	1
T58	100312	0
T59	180504	0
T60	0	20
T61	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	5748
T3	670	0
T6	1945	1
T7	14517	63
T8	5132	0
T9	14824	0
T14	526	20
T15	402	0
T19	0	1
T20	0	60
T24	460	0
T38	0	42
T48	0	20
T54	0	1
T58	409	0
T59	4402	0
T60	0	20
T61	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T14,T6
1	0	Covered	T4,T14,T6
1	1	Covered	T14,T7,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T14,T6
1	0	Covered	T14,T7,T20
1	1	Covered	T4,T14,T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	6783	0	0
SrcPulseCheck_M	1224288996	6858	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	6783
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	1
T7	14517	68
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	20
T15	402	0
T24	0	1
T25	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	6858
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	1
T7	696967	68
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	20
T15	201290	0
T24	0	1
T25	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T14,T6
1	0	Covered	T4,T14,T6
1	1	Covered	T14,T7,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T14,T6
1	0	Covered	T14,T7,T20
1	1	Covered	T4,T14,T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	6847	0	0
SrcPulseCheck_M	9241877	6847	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	6847
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	1
T7	696967	68
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	20
T15	201290	0
T24	0	1
T25	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	6847
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	1
T7	14517	68
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	20
T15	402	0
T24	0	1
T25	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T7,T20
1	0	Covered	T14,T7,T20
1	1	Covered	T14,T7,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T7,T20
1	0	Covered	T14,T7,T20
1	1	Covered	T14,T7,T20

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	5626	0	0
SrcPulseCheck_M	1224288996	5703	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	5626
T3	670	0
T6	1945	0
T7	14517	60
T8	5132	0
T9	14824	0
T14	526	20
T15	402	0
T20	0	60
T24	460	0
T38	0	40
T48	0	20
T58	409	0
T59	4402	0
T60	0	20
T61	0	20
T62	0	20
T63	0	20
T64	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	5703
T3	105965	0
T6	933651	0
T7	696967	60
T8	251477	0
T9	148244	0
T14	68428	20
T15	201290	0
T20	0	60
T24	57611	0
T38	0	40
T48	0	20
T58	100312	0
T59	180504	0
T60	0	20
T61	0	20
T62	0	20
T63	0	20
T64	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T7,T20
1	0	Covered	T14,T7,T20
1	1	Covered	T14,T7,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T14,T7,T20
1	0	Covered	T14,T7,T20
1	1	Covered	T14,T7,T20

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	5694	0	0
SrcPulseCheck_M	9241877	5694	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	5694
T3	105965	0
T6	933651	0
T7	696967	60
T8	251477	0
T9	148244	0
T14	68428	20
T15	201290	0
T20	0	60
T24	57611	0
T38	0	40
T48	0	20
T58	100312	0
T59	180504	0
T60	0	20
T61	0	20
T62	0	20
T63	0	20
T64	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	5694
T3	670	0
T6	1945	0
T7	14517	60
T8	5132	0
T9	14824	0
T14	526	20
T15	402	0
T20	0	60
T24	460	0
T38	0	40
T48	0	20
T58	409	0
T59	4402	0
T60	0	20
T61	0	20
T62	0	20
T63	0	20
T64	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T3,T6
1	0	Covered	T49,T50,T29
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	819	0	0
SrcPulseCheck_M	1224288996	893	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	819
T2	682	1
T3	670	1
T6	1945	1
T7	14517	2
T8	5132	0
T9	14824	0
T14	526	0
T15	402	0
T20	0	1
T24	460	0
T33	0	1
T35	0	6
T37	0	1
T38	0	1
T39	0	1
T58	409	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	893
T2	57112	1
T3	105965	1
T6	933651	1
T7	696967	2
T8	251477	0
T9	148244	0
T14	68428	0
T15	201290	0
T20	0	1
T24	57611	0
T33	0	1
T35	0	6
T37	0	1
T38	0	1
T39	0	1
T58	100312	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T3,T6
1	0	Covered	T49,T50,T29
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	885	0	0
SrcPulseCheck_M	9241877	885	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	885
T2	57112	1
T3	105965	1
T6	933651	1
T7	696967	2
T8	251477	0
T9	148244	0
T14	68428	0
T15	201290	0
T20	0	1
T24	57611	0
T33	0	1
T35	0	6
T37	0	1
T38	0	1
T39	0	1
T58	100312	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	885
T2	682	1
T3	670	1
T6	1945	1
T7	14517	2
T8	5132	0
T9	14824	0
T14	526	0
T15	402	0
T20	0	1
T24	460	0
T33	0	1
T35	0	6
T37	0	1
T38	0	1
T39	0	1
T58	409	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T2,T3
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T2,T3
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1702	0	0
SrcPulseCheck_M	1224288996	1773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1702
T1	918	0
T2	682	1
T3	670	1
T4	460	1
T5	402	0
T6	1945	1
T7	14517	5
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1773
T1	121801	0
T2	57112	1
T3	105965	1
T4	225791	1
T5	188873	0
T6	933651	1
T7	696967	5
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T2,T3
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T2,T3
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1762	0	0
SrcPulseCheck_M	9241877	1762	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1762
T1	121801	0
T2	57112	1
T3	105965	1
T4	225791	1
T5	188873	0
T6	933651	1
T7	696967	5
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1762
T1	918	0
T2	682	1
T3	670	1
T4	460	1
T5	402	0
T6	1945	1
T7	14517	5
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1130	0	0
SrcPulseCheck_M	1224288996	1204	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1130
T21	617	5
T22	714	4
T23	0	5
T26	4272	0
T30	30644	0
T32	0	3
T33	227835	0
T34	23794	0
T35	0	6
T37	0	6
T38	6803	0
T42	0	4
T43	0	6
T44	0	5
T45	0	9
T46	586	0
T47	427	0
T48	502	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1204
T21	154369	5
T22	343058	4
T23	0	5
T26	534023	0
T30	597551	0
T32	0	3
T33	480080	0
T34	297425	0
T35	0	6
T37	0	6
T38	709006	0
T42	0	4
T43	0	6
T44	0	5
T45	0	9
T46	51694	0
T47	40662	0
T48	123315	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1195	0	0
SrcPulseCheck_M	9241877	1195	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1195
T21	154369	5
T22	343058	4
T23	0	5
T26	534023	0
T30	597551	0
T32	0	3
T33	480080	0
T34	297425	0
T35	0	6
T37	0	6
T38	709006	0
T42	0	4
T43	0	6
T44	0	5
T45	0	9
T46	51694	0
T47	40662	0
T48	123315	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1195
T21	617	5
T22	714	4
T23	0	5
T26	4272	0
T30	30644	0
T32	0	3
T33	227835	0
T34	23794	0
T35	0	6
T37	0	6
T38	6803	0
T42	0	4
T43	0	6
T44	0	5
T45	0	9
T46	586	0
T47	427	0
T48	502	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	964	0	0
SrcPulseCheck_M	1224288996	1034	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	964
T21	617	3
T22	714	3
T23	0	3
T26	4272	0
T30	30644	0
T32	0	3
T33	227835	0
T34	23794	0
T35	0	3
T37	0	3
T38	6803	0
T42	0	3
T43	0	6
T44	0	3
T45	0	6
T46	586	0
T47	427	0
T48	502	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1034
T21	154369	3
T22	343058	3
T23	0	3
T26	534023	0
T30	597551	0
T32	0	3
T33	480080	0
T34	297425	0
T35	0	3
T37	0	3
T38	709006	0
T42	0	3
T43	0	6
T44	0	3
T45	0	6
T46	51694	0
T47	40662	0
T48	123315	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1024	0	0
SrcPulseCheck_M	9241877	1024	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1024
T21	154369	3
T22	343058	3
T23	0	3
T26	534023	0
T30	597551	0
T32	0	3
T33	480080	0
T34	297425	0
T35	0	3
T37	0	3
T38	709006	0
T42	0	3
T43	0	6
T44	0	3
T45	0	6
T46	51694	0
T47	40662	0
T48	123315	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1024
T21	617	3
T22	714	3
T23	0	3
T26	4272	0
T30	30644	0
T32	0	3
T33	227835	0
T34	23794	0
T35	0	3
T37	0	3
T38	6803	0
T42	0	3
T43	0	6
T44	0	3
T45	0	6
T46	586	0
T47	427	0
T48	502	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T4,T9,T24
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T9,T25,T26
1	1	Covered	T4,T9,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	6647	0	0
SrcPulseCheck_M	1224288996	6724	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	6647
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	0
T9	0	63
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	51
T26	0	51
T30	0	87
T34	0	73
T40	0	74
T65	0	73
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	6724
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	0
T9	0	63
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	51
T26	0	51
T30	0	87
T34	0	73
T40	0	74
T65	0	73
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T4,T9,T24
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T9,T25,T26
1	1	Covered	T4,T9,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	6716	0	0
SrcPulseCheck_M	9241877	6716	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	6716
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	0
T9	0	63
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	51
T26	0	51
T30	0	87
T34	0	73
T40	0	74
T65	0	73
T66	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	6716
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	0
T9	0	63
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	51
T26	0	51
T30	0	87
T34	0	73
T40	0	74
T65	0	73
T66	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	6471	0	0
SrcPulseCheck_M	1224288996	6548	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	6471
T9	14824	63
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	82
T34	0	71
T40	0	76
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	73
T66	0	51
T67	0	54
T68	0	55

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	6548
T9	148244	63
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	82
T34	0	71
T40	0	76
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	73
T66	0	51
T67	0	54
T68	0	55

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	6539	0	0
SrcPulseCheck_M	9241877	6539	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	6539
T9	148244	63
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	82
T34	0	71
T40	0	76
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	73
T66	0	51
T67	0	54
T68	0	55

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	6539
T9	14824	63
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	82
T34	0	71
T40	0	76
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	73
T66	0	51
T67	0	54
T68	0	55

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	6475	0	0
SrcPulseCheck_M	1224288996	6552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	6475
T9	14824	57
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	71
T34	0	85
T40	0	61
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	79
T66	0	51
T67	0	61
T68	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	6552
T9	148244	57
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	71
T34	0	85
T40	0	61
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	79
T66	0	51
T67	0	61
T68	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	6543	0	0
SrcPulseCheck_M	9241877	6543	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	6543
T9	148244	57
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	71
T34	0	85
T40	0	61
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	79
T66	0	51
T67	0	61
T68	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	6543
T9	14824	57
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	71
T34	0	85
T40	0	61
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	79
T66	0	51
T67	0	61
T68	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	6539	0	0
SrcPulseCheck_M	1224288996	6610	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	6539
T9	14824	55
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	84
T34	0	87
T40	0	84
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	64
T66	0	51
T67	0	61
T68	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	6610
T9	148244	55
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	84
T34	0	87
T40	0	84
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	64
T66	0	51
T67	0	61
T68	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	6602	0	0
SrcPulseCheck_M	9241877	6602	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	6602
T9	148244	55
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	84
T34	0	87
T40	0	84
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	64
T66	0	51
T67	0	61
T68	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	6602
T9	14824	55
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	84
T34	0	87
T40	0	84
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	64
T66	0	51
T67	0	61
T68	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T4,T9,T24
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T9,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1066	0	0
SrcPulseCheck_M	1224288996	1137	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1066
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	0
T9	0	5
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T65	0	5
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1137
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	0
T9	0	5
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T65	0	5
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T4,T9,T24
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T9,T24
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T9,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1129	0	0
SrcPulseCheck_M	9241877	1129	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1129
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	0
T9	0	5
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T65	0	5
T66	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1129
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	0
T9	0	5
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T65	0	5
T66	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T49,T50,T29
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	996	0	0
SrcPulseCheck_M	1224288996	1071	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	996
T9	14824	5
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1071
T9	148244	5
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T49,T50,T29
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1062	0	0
SrcPulseCheck_M	9241877	1062	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1062
T9	148244	5
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1062
T9	14824	5
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T49,T50,T29
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1014	0	0
SrcPulseCheck_M	1224288996	1081	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1014
T9	14824	5
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1081
T9	148244	5
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T49,T50,T29
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1072	0	0
SrcPulseCheck_M	9241877	1072	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1072
T9	148244	5
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1072
T9	14824	5
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T49,T50,T29
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	993	0	0
SrcPulseCheck_M	1224288996	1068	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	993
T9	14824	5
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1068
T9	148244	5
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T9,T25,T26
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T25,T26
1	0	Covered	T49,T50,T29
1	1	Covered	T9,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1060	0	0
SrcPulseCheck_M	9241877	1060	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1060
T9	148244	5
T10	251482	0
T11	236593	0
T12	247039	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	82159	0
T51	79164	0
T58	100312	0
T59	180504	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1060
T9	14824	5
T10	557799	0
T11	483	0
T12	1206	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T34	0	9
T40	0	3
T41	443	0
T51	633	0
T58	409	0
T59	4402	0
T65	0	5
T66	0	1
T67	0	4
T68	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T9,T25,T26
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	7270	0	0
SrcPulseCheck_M	1224288996	7348	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	7270
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	3
T8	0	1
T9	0	63
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	51
T33	0	15
T38	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	7348
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	3
T8	0	1
T9	0	63
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	51
T33	0	15
T38	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T9,T25,T26
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	7339	0	0
SrcPulseCheck_M	9241877	7339	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	7339
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	3
T8	0	1
T9	0	63
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	51
T33	0	15
T38	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	7339
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	3
T8	0	1
T9	0	63
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	51
T33	0	15
T38	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T9,T25,T26
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	7063	0	0
SrcPulseCheck_M	1224288996	7136	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	7063
T7	14517	2
T8	5132	1
T9	14824	63
T10	557799	0
T11	483	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	82
T31	0	5
T32	0	10
T33	0	15
T34	0	71
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	7136
T7	696967	2
T8	251477	1
T9	148244	63
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	82
T31	0	5
T32	0	10
T33	0	15
T34	0	71
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T9,T25,T26
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	7128	0	0
SrcPulseCheck_M	9241877	7128	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	7128
T7	696967	2
T8	251477	1
T9	148244	63
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	82
T31	0	5
T32	0	10
T33	0	15
T34	0	71
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	7128
T7	14517	2
T8	5132	1
T9	14824	63
T10	557799	0
T11	483	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	82
T31	0	5
T32	0	10
T33	0	15
T34	0	71
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T9,T25,T26
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	7075	0	0
SrcPulseCheck_M	1224288996	7149	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	7075
T7	14517	2
T8	5132	1
T9	14824	57
T10	557799	0
T11	483	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	71
T31	0	5
T32	0	10
T33	0	15
T34	0	85
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	7149
T7	696967	2
T8	251477	1
T9	148244	57
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	71
T31	0	5
T32	0	10
T33	0	15
T34	0	85
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T9,T25,T26
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	7141	0	0
SrcPulseCheck_M	9241877	7141	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	7141
T7	696967	2
T8	251477	1
T9	148244	57
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	71
T31	0	5
T32	0	10
T33	0	15
T34	0	85
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	7141
T7	14517	2
T8	5132	1
T9	14824	57
T10	557799	0
T11	483	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	71
T31	0	5
T32	0	10
T33	0	15
T34	0	85
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T9,T25,T26
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	7095	0	0
SrcPulseCheck_M	1224288996	7168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	7095
T7	14517	2
T8	5132	1
T9	14824	55
T10	557799	0
T11	483	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	84
T31	0	5
T32	0	10
T33	0	15
T34	0	87
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	7168
T7	696967	2
T8	251477	1
T9	148244	55
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	84
T31	0	5
T32	0	10
T33	0	15
T34	0	87
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T9,T25,T26
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	7161	0	0
SrcPulseCheck_M	9241877	7161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	7161
T7	696967	2
T8	251477	1
T9	148244	55
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	51
T26	0	51
T30	0	84
T31	0	5
T32	0	10
T33	0	15
T34	0	87
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	7161
T7	14517	2
T8	5132	1
T9	14824	55
T10	557799	0
T11	483	0
T24	460	0
T25	4620	51
T26	0	51
T30	0	84
T31	0	5
T32	0	10
T33	0	15
T34	0	87
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1662	0	0
SrcPulseCheck_M	1224288996	1732	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1662
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	3
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1732
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	3
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1723	0	0
SrcPulseCheck_M	9241877	1723	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1723
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	3
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1723
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	3
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1580	0	0
SrcPulseCheck_M	1224288996	1653	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1580
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1653
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1644	0	0
SrcPulseCheck_M	9241877	1644	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1644
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1644
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1590	0	0
SrcPulseCheck_M	1224288996	1661	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1590
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1661
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1652	0	0
SrcPulseCheck_M	9241877	1652	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1652
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1652
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1590	0	0
SrcPulseCheck_M	1224288996	1660	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1590
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1660
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1651	0	0
SrcPulseCheck_M	9241877	1651	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1651
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1651
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1615	0	0
SrcPulseCheck_M	1224288996	1683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1615
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	3
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1683
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	3
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T7,T8
1	0	Covered	T49,T50,T29
1	1	Covered	T4,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1672	0	0
SrcPulseCheck_M	9241877	1672	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1672
T1	121801	0
T2	57112	0
T3	105965	0
T4	225791	1
T5	188873	0
T6	933651	0
T7	696967	3
T8	0	1
T9	0	5
T11	0	1
T13	32033	0
T14	68428	0
T15	201290	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1672
T1	918	0
T2	682	0
T3	670	0
T4	460	1
T5	402	0
T6	1945	0
T7	14517	3
T8	0	1
T9	0	5
T11	0	1
T13	427	0
T14	526	0
T15	402	0
T24	0	1
T25	0	1
T33	0	15
T38	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1602	0	0
SrcPulseCheck_M	1224288996	1673	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1602
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1673
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1662	0	0
SrcPulseCheck_M	9241877	1662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1662
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1662
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1592	0	0
SrcPulseCheck_M	1224288996	1665	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1592
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1665
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1655	0	0
SrcPulseCheck_M	9241877	1655	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1655
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1655
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9241877	1605	0	0
SrcPulseCheck_M	1224288996	1673	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9241877	1605
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1224288996	1673
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T49,T50,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T8,T9
1	0	Covered	T49,T50,T29
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1224288996	1665	0	0
SrcPulseCheck_M	9241877	1665	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1224288996	1665
T7	696967	2
T8	251477	1
T9	148244	5
T10	251482	0
T11	236593	0
T24	57611	0
T25	577675	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	79164	0
T58	100312	0
T59	180504	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9241877	1665
T7	14517	2
T8	5132	1
T9	14824	5
T10	557799	0
T11	483	0
T24	460	0
T25	4620	1
T26	0	1
T30	0	12
T31	0	5
T32	0	10
T33	0	15
T34	0	9
T51	633	0
T58	409	0
T59	4402	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc