Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1711

1

T1

10

T11

2

T12

11

auto[1]

573

1

T11

4

T12

10

T43

14

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1652

1

T12

16

T30

22

T43

15

auto[1]

632

1

T1

10

T11

6

T12

5

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1743

1

T1

3

T11

6

T12

4

auto[1]

541

1

T1

7

T12

17

T30

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1759

1

T1

10

T11

4

T12

16

auto[1]

525

1

T11

2

T12

5

T30

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2159

1

T1

10

T11

6

T12

21

auto[1]

125

1

T30

4

T32

1

T37

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2105

1

T1

10

T11

6

T12

21

auto[1]

179

1

T30

2

T32

1

T54

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2112

1

T1

10

T11

6

T12

21

auto[1]

172

1

T30

4

T32

2

T54

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2090

1

T1

10

T11

6

T12

21

auto[1]

194

1

T30

2

T54

2

T42

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2080

1

T1

10

T11

6

T12

21

auto[1]

204

1

T30

4

T37

3

T42

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1773

1

T1

7

T11

4

T12

20

auto[1]

511

1

T1

3

T11

2

T12

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

838

1

T1

10

T11

6

T12

21

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

44

1

T37

2

T259

2

T150

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

89

1

T37

3

T42

3

T76

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T119

4

T138

3

T265

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

82

1

T76

8

T190

22

T259

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T358

2

T359

4

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

18

1

T42

1

T189

1

T109

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T30

2

T109

4

T354

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T32

2

T360

1

T172

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T361

2

T350

3

T217

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T30

2

T252

3

T265

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T217

3

T362

2

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T190

4

T363

1

T364

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T189

2

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T119

2

T172

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

80

1

T36

4

T189

7

T351

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T32

1

T351

1

T365

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

12

1

T110

1

T350

1

T366

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

24

1

T119

2

T172

1

T350

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

10

1

T138

3

T367

1

T364

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T30

2

T76

1

T368

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

6

1

T345

4

T364

2

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T369

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T370

3

T269

2

T366

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T54

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

121

1

T43

14

T42

3

T199

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

71

1

T54

2

T76

1

T138

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

52

1

T190

11

T141

2

T170

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T32

2

T138

3

T139

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

38

1

T41

1

T140

4

T121

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T30

2

T120

5

T140

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T271

1

T371

5

T367

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

131

1

T12

11

T30

2

T139

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

59

1

T12

5

T189

1

T360

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T76

8

T350

1

T225

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T119

2

T352

3

T127

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T32

1

T37

3

T36

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T110

1

T340

6

T196

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T43

1

T125

3

T347

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T351

2

T365

1

T371

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

121

1

T30

2

T107

14

T119

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T11

2

T199

6

T172

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T1

3

T43

6

T190

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

69

1

T11

2

T107

4

T190

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T11

2

T140

1

T150

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T12

4

T120

3

T360

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T217

6

T342

3

T359

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T291

1

T372

1

T373

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T1

7

T249

6

T109

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T42

1

T269

4

T374

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T37

2

T139

2

T268

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T260

3

T268

2

T196

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T138

4

T139

3

T291

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T107

1

T213

2

T375

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T199

1

T259

2

T346

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T12

1

T141

1

T268

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded