Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T15

7

T16

13

T18

13

auto[1]

1015

1

T15

13

T16

7

T18

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T15

5

T16

6

T18

4

from_0to1

494

1

T15

5

T16

6

T18

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T15

9

T16

9

T18

12

auto[1]

1062

1

T15

11

T16

11

T18

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T15

11

T16

9

T18

7

auto[1]

1071

1

T15

9

T16

11

T18

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T15

1

T71

1

T28

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T15

1

T16

2

T18

2

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T15

1

T48

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T16

1

T18

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T16

1

T48

1

T70

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T18

1

T28

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T16

2

T28

2

T131

2

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T16

2

T18

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T16

2

T18

1

T70

2

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T70

1

T25

2

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T48

2

T70

1

T28

3

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T15

2

T16

1

T133

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T15

1

T28

2

T262

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T15

2

T18

2

T28

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T15

1

T48

1

T70

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T15

1

T16

1

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T15

10

T16

12

T18

12

auto[1]

1024

1

T15

10

T16

8

T18

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T15

5

T16

4

T18

3

from_0to1

483

1

T15

5

T16

5

T18

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T15

8

T16

11

T18

9

auto[1]

1061

1

T15

12

T16

9

T18

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T15

9

T16

10

T18

8

auto[1]

1069

1

T15

11

T16

10

T18

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T15

1

T16

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T15

1

T16

1

T18

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T15

1

T16

1

T48

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T15

1

T70

3

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T16

1

T28

2

T25

2

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T18

1

T48

1

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T70

2

T71

1

T28

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T15

1

T16

1

T18

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T28

4

T262

1

T25

3

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T16

1

T71

2

T131

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T15

1

T48

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T18

1

T48

2

T28

4

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T48

1

T70

1

T71

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T15

1

T48

1

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T15

3

T16

2

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T16

1

T18

1

T48

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T15

13

T16

11

T18

12

auto[1]

1040

1

T15

7

T16

9

T18

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

503

1

T15

4

T16

7

T18

3

from_0to1

499

1

T15

4

T16

6

T18

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T15

7

T16

9

T18

8

auto[1]

1079

1

T15

13

T16

11

T18

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T15

11

T16

10

T18

14

auto[1]

1045

1

T15

9

T16

10

T18

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T15

1

T16

1

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T16

2

T70

1

T28

3

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T16

1

T18

1

T70

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T15

1

T16

2

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T70

1

T28

1

T133

2

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T28

3

T262

1

T25

2

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T15

1

T16

2

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T15

2

T28

2

T131

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T48

1

T70

2

T28

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T15

1

T16

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T15

1

T28

6

T131

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T18

1

T70

1

T71

2

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T16

1

T18

1

T48

2

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T15

1

T16

1

T18

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T16

2

T48

1

T71

3

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T71

2

T28

2

T131

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T15

10

T16

9

T18

7

auto[1]

1027

1

T15

10

T16

11

T18

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T15

5

T16

5

T18

5

from_0to1

499

1

T15

5

T16

5

T18

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T15

5

T16

10

T18

8

auto[1]

1040

1

T15

15

T16

10

T18

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T15

10

T16

12

T18

13

auto[1]

1042

1

T15

10

T16

8

T18

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T70

1

T71

2

T28

2

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T18

1

T48

1

T28

2

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T15

1

T16

2

T18

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T15

2

T16

1

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T16

1

T71

1

T28

3

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T18

2

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T28

3

T133

1

T25

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T15

2

T48

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T15

1

T16

1

T48

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T16

1

T18

1

T70

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T15

1

T18

1

T48

1

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T48

2

T70

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T15

2

T16

1

T18

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T48

1

T70

1

T28

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T16

1

T18

2

T48

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T15

1

T16

1

T48

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T15

8

T16

11

T18

9

auto[1]

1052

1

T15

12

T16

9

T18

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T15

4

T16

4

T18

6

from_0to1

497

1

T15

4

T16

3

T18

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T15

10

T16

10

T18

11

auto[1]

1022

1

T15

10

T16

10

T18

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T15

12

T16

10

T18

11

auto[1]

1047

1

T15

8

T16

10

T18

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T48

1

T70

2

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T70

1

T28

1

T131

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T15

2

T48

1

T70

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T16

1

T18

1

T28

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T70

1

T28

3

T133

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T15

1

T18

1

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T16

3

T18

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T15

1

T48

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T16

1

T18

1

T71

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T15

2

T16

1

T18

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T18

1

T48

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T16

1

T18

1

T28

4

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T18

2

T131

1

T133

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T15

1

T48

1

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T15

1

T18

2

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T70

1

T28

4

T131

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T15

8

T16

10

T18

7

auto[1]

1054

1

T15

12

T16

10

T18

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T15

5

T16

5

T18

5

from_0to1

505

1

T15

5

T16

4

T18

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T15

10

T16

8

T18

9

auto[1]

1049

1

T15

10

T16

12

T18

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T15

11

T16

8

T18

6

auto[1]

1041

1

T15

9

T16

12

T18

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T16

1

T18

1

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T70

2

T28

2

T133

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T28

3

T262

1

T25

2

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T16

1

T18

1

T28

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T15

1

T133

1

T262

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T15

1

T48

1

T70

2

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T16

2

T48

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T15

1

T18

2

T48

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T15

2

T48

1

T71

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T18

3

T48

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T15

1

T48

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T15

2

T16

3

T70

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T15

1

T28

3

T131

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T16

1

T28

1

T262

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T18

2

T28

1

T131

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T15

1

T16

1

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T15

12

T16

9

T18

14

auto[1]

1051

1

T15

8

T16

11

T18

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T15

5

T16

4

T18

3

from_0to1

505

1

T15

5

T16

4

T18

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T15

11

T16

7

T18

8

auto[1]

1058

1

T15

9

T16

13

T18

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T15

12

T16

7

T18

9

auto[1]

1075

1

T15

8

T16

13

T18

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T18

1

T48

2

T28

3

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T15

2

T18

1

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T71

1

T133

1

T262

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T15

1

T16

3

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T15

1

T16

1

T18

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T16

1

T48

1

T133

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T15

2

T18

1

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T28

3

T131

2

T262

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T15

1

T48

1

T28

3

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T133

1

T262

4

T25

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T15

1

T16

1

T18

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T70

1

T28

1

T133

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T70

2

T28

3

T25

2

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T15

2

T16

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T16

1

T48

1

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T18

1

T48

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T15

8

T16

8

T18

9

auto[1]

1072

1

T15

12

T16

12

T18

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T15

6

T16

7

T18

6

from_0to1

523

1

T15

6

T16

8

T18

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T15

9

T16

10

T18

10

auto[1]

1011

1

T15

11

T16

10

T18

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T15

10

T16

13

T18

12

auto[1]

1054

1

T15

10

T16

7

T18

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T16

1

T18

3

T28

3

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T16

1

T70

2

T28

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T16

2

T28

3

T133

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T70

1

T71

2

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T15

1

T71

1

T28

3

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T18

1

T71

3

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T18

2

T70

1

T28

3

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T15

2

T18

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T15

1

T16

2

T18

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T15

1

T16

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T15

1

T70

1

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T15

3

T18

2

T48

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T15

2

T16

2

T48

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T18

1

T71

1

T28

3

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T16

3

T18

1

T70

2

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T15

1

T16

2

T48

1