Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152587	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115353

1

T1

256

T5

185

T6

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138625	1			T1	398		T5	276		T6	9
values[0x0]	63980	1			T1	75		T5	40		T13	5
values[0x1]	65335	1			T1	85		T5	53		T6	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144623

1

T1

310

T5

225

T6

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	963	1			T13	1		T59	1		T60	1
valid_sources[0x01]	877	1			T1	1		T13	2		T17	12
valid_sources[0x02]	797	1			T1	1		T13	1		T48	1
valid_sources[0x03]	891	1			T1	7		T5	5		T13	1
valid_sources[0x04]	774	1			T1	2		T13	1		T11	6
valid_sources[0x05]	831	1			T1	3		T13	2		T12	2
valid_sources[0x06]	861	1			T1	2		T13	3		T17	26
valid_sources[0x07]	887	1			T1	4		T13	2		T17	20
valid_sources[0x08]	969	1			T1	9		T13	1		T11	1
valid_sources[0x09]	877	1			T13	1		T16	2		T18	1
valid_sources[0x0a]	1466	1			T1	1		T13	3		T48	1
valid_sources[0x0b]	2719	1			T1	1		T13	1		T16	2
valid_sources[0x0c]	1025	1			T1	7		T5	7		T13	2
valid_sources[0x0d]	902	1			T1	5		T13	1		T48	3
valid_sources[0x0e]	871	1			T1	1		T13	2		T70	1
valid_sources[0x0f]	996	1			T1	6		T13	2		T17	9
valid_sources[0x10]	1307	1			T1	5		T5	1		T13	3
valid_sources[0x11]	1179	1			T1	2		T13	2		T16	4
valid_sources[0x12]	1310	1			T1	3		T13	5		T18	2
valid_sources[0x13]	977	1			T1	2		T13	1		T16	2
valid_sources[0x14]	1369	1			T1	2		T13	1		T18	1
valid_sources[0x15]	804	1			T1	3		T16	8		T71	1
valid_sources[0x16]	827	1			T1	1		T13	2		T16	7
valid_sources[0x17]	1878	1			T1	1		T13	2		T17	10
valid_sources[0x18]	962	1			T1	1		T2	2		T11	1
valid_sources[0x19]	931	1			T1	3		T5	3		T16	1
valid_sources[0x1a]	874	1			T1	10		T13	4		T70	1
valid_sources[0x1b]	1343	1			T1	2		T13	1		T18	1
valid_sources[0x1c]	1003	1			T1	1		T13	1		T16	5
valid_sources[0x1d]	977	1			T1	1		T5	13		T13	2
valid_sources[0x1e]	943	1			T1	5		T5	5		T70	2
valid_sources[0x1f]	816	1			T1	10		T13	1		T70	3
valid_sources[0x20]	966	1			T1	8		T26	1		T11	2
valid_sources[0x21]	1403	1			T1	1		T12	1		T30	6
valid_sources[0x22]	830	1			T1	1		T13	3		T70	1
valid_sources[0x23]	821	1			T1	2		T17	1		T70	2
valid_sources[0x24]	1037	1			T1	3		T13	2		T17	9
valid_sources[0x25]	865	1			T1	9		T13	2		T48	2
valid_sources[0x26]	906	1			T1	2		T5	4		T13	2
valid_sources[0x27]	1162	1			T13	2		T48	1		T70	1
valid_sources[0x28]	879	1			T1	3		T13	1		T17	2
valid_sources[0x29]	900	1			T13	3		T70	1		T26	1
valid_sources[0x2a]	933	1			T1	4		T13	1		T16	2
valid_sources[0x2b]	865	1			T1	5		T13	2		T11	6
valid_sources[0x2c]	876	1			T1	1		T13	3		T16	1
valid_sources[0x2d]	804	1			T1	3		T13	1		T2	3
valid_sources[0x2e]	1657	1			T1	3		T13	2		T48	6
valid_sources[0x2f]	1486	1			T1	7		T13	3		T18	1
valid_sources[0x30]	878	1			T1	2		T13	1		T71	1
valid_sources[0x31]	950	1			T1	3		T13	2		T18	2
valid_sources[0x32]	835	1			T1	1		T13	2		T71	2
valid_sources[0x33]	1087	1			T1	1		T13	1		T11	8
valid_sources[0x34]	1961	1			T1	2		T13	1		T16	1
valid_sources[0x35]	676	1			T13	1		T70	1		T56	1
valid_sources[0x36]	866	1			T5	7		T13	3		T70	1
valid_sources[0x37]	912	1			T1	8		T13	2		T12	1
valid_sources[0x38]	900	1			T13	2		T18	1		T26	1
valid_sources[0x39]	999	1			T13	1		T48	2		T26	2
valid_sources[0x3a]	805	1			T48	1		T11	2		T30	8
valid_sources[0x3b]	945	1			T5	3		T13	2		T66	1
valid_sources[0x3c]	2008	1			T1	1		T7	1		T12	3
valid_sources[0x3d]	1158	1			T1	4		T5	3		T13	3
valid_sources[0x3e]	1811	1			T1	2		T13	1		T18	3
valid_sources[0x3f]	883	1			T1	2		T5	4		T13	1
valid_sources[0x40]	1090	1			T1	1		T59	1		T26	1
valid_sources[0x41]	819	1			T1	2		T13	2		T16	1
valid_sources[0x42]	868	1			T1	1		T13	1		T48	3
valid_sources[0x43]	894	1			T1	4		T13	1		T16	7
valid_sources[0x44]	970	1			T1	1		T5	23		T13	2
valid_sources[0x45]	1264	1			T13	1		T48	2		T23	3
valid_sources[0x46]	804	1			T13	1		T17	5		T48	1
valid_sources[0x47]	927	1			T5	1		T13	1		T18	1
valid_sources[0x48]	936	1			T13	2		T16	1		T17	29
valid_sources[0x49]	2099	1			T5	1		T13	4		T71	2
valid_sources[0x4a]	1634	1			T1	2		T13	1		T2	2
valid_sources[0x4b]	1120	1			T1	3		T13	1		T2	1
valid_sources[0x4c]	807	1			T1	1		T13	1		T2	2
valid_sources[0x4d]	1016	1			T1	3		T13	2		T16	2
valid_sources[0x4e]	782	1			T1	11		T13	3		T11	4
valid_sources[0x4f]	915	1			T1	3		T13	2		T71	2
valid_sources[0x50]	1043	1			T1	6		T13	1		T70	3
valid_sources[0x51]	847	1			T1	1		T26	1		T11	2
valid_sources[0x52]	873	1			T13	4		T16	1		T12	3
valid_sources[0x53]	1880	1			T17	26		T18	3		T12	1
valid_sources[0x54]	1228	1			T1	6		T5	4		T13	4
valid_sources[0x55]	956	1			T1	3		T13	2		T2	1
valid_sources[0x56]	880	1			T5	4		T13	3		T11	1
valid_sources[0x57]	950	1			T13	2		T2	1		T59	1
valid_sources[0x58]	762	1			T1	2		T13	2		T48	2
valid_sources[0x59]	918	1			T13	3		T18	1		T70	1
valid_sources[0x5a]	893	1			T1	5		T26	1		T12	3
valid_sources[0x5b]	1717	1			T1	2		T13	5		T23	1
valid_sources[0x5c]	1960	1			T1	1		T5	7		T13	1
valid_sources[0x5d]	960	1			T1	1		T13	1		T17	20
valid_sources[0x5e]	817	1			T13	2		T17	3		T26	1
valid_sources[0x5f]	895	1			T13	2		T18	1		T30	12
valid_sources[0x60]	797	1			T1	1		T13	1		T17	2
valid_sources[0x61]	871	1			T1	3		T13	1		T70	2
valid_sources[0x62]	807	1			T13	1		T23	1		T11	1
valid_sources[0x63]	1006	1			T1	2		T70	1		T60	1
valid_sources[0x64]	1179	1			T1	1		T13	1		T17	1
valid_sources[0x65]	1027	1			T1	1		T13	1		T16	3
valid_sources[0x66]	2609	1			T1	2		T13	3		T18	1
valid_sources[0x67]	833	1			T1	3		T13	1		T23	1
valid_sources[0x68]	1170	1			T1	5		T13	1		T2	2
valid_sources[0x69]	953	1			T1	7		T13	1		T48	1
valid_sources[0x6a]	1088	1			T1	9		T5	6		T13	1
valid_sources[0x6b]	935	1			T23	2		T12	1		T30	4
valid_sources[0x6c]	811	1			T13	4		T16	3		T71	5
valid_sources[0x6d]	914	1			T1	2		T13	1		T17	10
valid_sources[0x6e]	1038	1			T1	1		T13	7		T15	122
valid_sources[0x6f]	1078	1			T1	3		T13	1		T17	5
valid_sources[0x70]	916	1			T13	1		T2	2		T18	3
valid_sources[0x71]	799	1			T5	9		T11	1		T12	2
valid_sources[0x72]	1275	1			T1	1		T13	1		T26	1
valid_sources[0x73]	1096	1			T1	1		T13	3		T18	1
valid_sources[0x74]	1016	1			T1	2		T5	4		T16	1
valid_sources[0x75]	816	1			T5	2		T4	2		T11	2
valid_sources[0x76]	861	1			T1	2		T13	1		T10	15
valid_sources[0x77]	1790	1			T1	5		T13	3		T16	5
valid_sources[0x78]	958	1			T1	5		T13	4		T17	11
valid_sources[0x79]	1901	1			T1	1		T13	2		T16	3
valid_sources[0x7a]	910	1			T1	3		T13	2		T7	1
valid_sources[0x7b]	1705	1			T1	9		T13	1		T11	2
valid_sources[0x7c]	954	1			T1	5		T11	1		T12	5
valid_sources[0x7d]	1887	1			T1	2		T18	1		T12	3
valid_sources[0x7e]	990	1			T1	5		T5	4		T13	1
valid_sources[0x7f]	971	1			T1	5		T5	5		T13	1
valid_sources[0x80]	906	1			T13	1		T60	1		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62308

1

T1

184

T5

142

T6

5

values[0x0]

all_enables

biggest_size

31074

1

T1

41

T5

23

T13

3

values[0x1]

all_enables

biggest_size

21971

1

T1

31

T5

20

T13

5