Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T27,T28,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T27,T28,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T27,T28,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T44
1	0	Covered	T1,T5,T6
1	1	Covered	T27,T28,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T44,T45
0	1	Covered	T28,T22,T41
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T44,T45
0	1	Covered	T27,T44,T45
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T44,T45
1	-	Covered	T27,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T44
DetectSt	168	Covered	T27,T28,T44
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T27,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T28,T44
DebounceSt->IdleSt	163	Covered	T22,T41,T117
DetectSt->IdleSt	186	Covered	T28,T22,T41
DetectSt->StableSt	191	Covered	T27,T44,T45
IdleSt->DebounceSt	148	Covered	T27,T28,T44
StableSt->IdleSt	206	Covered	T27,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T28,T44
0	1	Covered	T27,T28,T44
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T44
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T44
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T41,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T44
DetectSt	-	-	-	-	1	-	-	Covered	T28,T22,T41
DetectSt	-	-	-	-	0	1	-	Covered	T27,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T27,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	255	0	0
CntIncr_A	7903577	207561	0	0
CntNoWrap_A	7903577	7250832	0	0
DetectStDropOut_A	7903577	4	0	0
DetectedOut_A	7903577	740	0	0
DetectedPulseOut_A	7903577	113	0	0
DisabledIdleSt_A	7903577	7037535	0	0
DisabledNoDetection_A	7903577	7039763	0	0
EnterDebounceSt_A	7903577	140	0	0
EnterDetectSt_A	7903577	117	0	0
EnterStableSt_A	7903577	113	0	0
PulseIsPulse_A	7903577	113	0	0
StayInStableSt	7903577	627	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6775	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	112	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	255	0	0
T22	0	13	0	0
T27	766	2	0	0
T28	12055	2	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	21	0	0
T43	20986	0	0	0
T44	0	6	0	0
T45	0	4	0	0
T46	0	4	0	0
T47	0	4	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	3	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	207561	0	0
T22	0	9530	0	0
T27	766	65	0	0
T28	12055	74	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	556	0	0
T43	20986	0	0	0
T44	0	108	0	0
T45	0	112	0	0
T46	0	107	0	0
T47	0	106	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	58245	0	0
T118	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250832	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	4	0	0
T22	0	1	0	0
T28	12055	1	0	0
T29	775	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	1	0	0
T52	422	0	0	0
T96	418	0	0	0
T126	0	1	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T133	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	740	0	0
T22	0	20	0	0
T27	766	9	0	0
T28	12055	0	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	72	0	0
T43	20986	0	0	0
T44	0	14	0	0
T45	0	6	0	0
T46	0	13	0	0
T47	0	15	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	6	0	0
T118	0	4	0	0
T140	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	113	0	0
T22	0	5	0	0
T27	766	1	0	0
T28	12055	0	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	9	0	0
T43	20986	0	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7037535	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7039763	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	140	0	0
T22	0	7	0	0
T27	766	1	0	0
T28	12055	1	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	11	0	0
T43	20986	0	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	2	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	117	0	0
T22	0	6	0	0
T27	766	1	0	0
T28	12055	1	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	10	0	0
T43	20986	0	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	1	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	113	0	0
T22	0	5	0	0
T27	766	1	0	0
T28	12055	0	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	9	0	0
T43	20986	0	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	113	0	0
T22	0	5	0	0
T27	766	1	0	0
T28	12055	0	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	9	0	0
T43	20986	0	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	627	0	0
T22	0	15	0	0
T27	766	8	0	0
T28	12055	0	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	63	0	0
T43	20986	0	0	0
T44	0	11	0	0
T45	0	4	0	0
T46	0	11	0	0
T47	0	13	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	5	0	0
T118	0	3	0	0
T140	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6775	0	0
T1	25831	7	0	0
T2	1099	3	0	0
T5	4417	11	0	0
T6	651	2	0	0
T13	5067	8	0	0
T14	427	2	0	0
T15	508	6	0	0
T16	502	5	0	0
T17	5367	27	0	0
T18	502	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	112	0	0
T22	0	5	0	0
T27	766	1	0	0
T28	12055	0	0	0
T31	470	0	0	0
T32	13036	0	0	0
T37	15555	0	0	0
T41	0	9	0	0
T43	20986	0	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T52	422	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T140	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T22
1	0	Covered	T1,T5,T6
1	1	Covered	T2,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T22
0	1	Covered	T114,T115,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T22
0	1	Unreachable
1	0	Covered	T2,T4,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T22
DetectSt	168	Covered	T2,T4,T22
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T22
DebounceSt->IdleSt	163	Covered	T41,T80,T108
DetectSt->IdleSt	186	Covered	T114,T115,T91
DetectSt->StableSt	191	Covered	T2,T4,T22
IdleSt->DebounceSt	148	Covered	T2,T4,T22
StableSt->IdleSt	206	Covered	T2,T4,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T22
0	1	Covered	T2,T4,T22
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T22
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T80,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T114,T115,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T22
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	172	0	0
CntIncr_A	7903577	94479	0	0
CntNoWrap_A	7903577	7250915	0	0
DetectStDropOut_A	7903577	15	0	0
DetectedOut_A	7903577	565149	0	0
DetectedPulseOut_A	7903577	53	0	0
DisabledIdleSt_A	7903577	6269595	0	0
DisabledNoDetection_A	7903577	6271875	0	0
EnterDebounceSt_A	7903577	105	0	0
EnterDetectSt_A	7903577	68	0	0
EnterStableSt_A	7903577	53	0	0
PulseIsPulse_A	7903577	53	0	0
StayInStableSt	7903577	565096	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6775	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_sticky_sva.StableStDropOut_A	7903577	124435	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	172	0	0
T2	1099	2	0	0
T3	596	0	0	0
T4	0	2	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	8	0	0
T41	0	5	0	0
T48	504	0	0	0
T61	0	2	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	6	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	94479	0	0
T2	1099	88	0	0
T3	596	0	0	0
T4	0	81	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	30902	0	0
T41	0	235	0	0
T48	504	0	0	0
T61	0	64	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	33	0	0
T78	0	22	0	0
T79	0	13	0	0
T80	0	88	0	0
T81	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250915	0	0
T1	25831	25363	0	0
T2	1099	696	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	15	0	0
T91	0	2	0	0
T114	719	2	0	0
T115	0	2	0	0
T145	0	1	0	0
T146	0	7	0	0
T147	0	1	0	0
T148	4041	0	0	0
T149	404	0	0	0
T150	14339	0	0	0
T151	818	0	0	0
T152	2574	0	0	0
T153	429	0	0	0
T154	675	0	0	0
T155	522	0	0	0
T156	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	565149	0	0
T2	1099	260	0	0
T3	596	0	0	0
T4	0	398	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	108818	0	0
T48	504	0	0	0
T61	0	161	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	69	0	0
T78	0	144	0	0
T79	0	27	0	0
T81	0	412	0	0
T120	0	183	0	0
T142	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	53	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	4	0	0
T48	504	0	0	0
T61	0	1	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6269595	0	0
T1	25831	25363	0	0
T2	1099	244	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6271875	0	0
T1	25831	25373	0	0
T2	1099	245	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	105	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	4	0	0
T41	0	5	0	0
T48	504	0	0	0
T61	0	1	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	4	0	0
T81	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	68	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	4	0	0
T48	504	0	0	0
T61	0	1	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	53	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	4	0	0
T48	504	0	0	0
T61	0	1	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	53	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	4	0	0
T48	504	0	0	0
T61	0	1	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	565096	0	0
T2	1099	259	0	0
T3	596	0	0	0
T4	0	397	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	108814	0	0
T48	504	0	0	0
T61	0	160	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	66	0	0
T78	0	143	0	0
T79	0	26	0	0
T81	0	411	0	0
T120	0	182	0	0
T142	0	97	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6775	0	0
T1	25831	7	0	0
T2	1099	3	0	0
T5	4417	11	0	0
T6	651	2	0	0
T13	5067	8	0	0
T14	427	2	0	0
T15	508	6	0	0
T16	502	5	0	0
T17	5367	27	0	0
T18	502	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	124435	0	0
T2	1099	88	0	0
T3	596	0	0	0
T4	0	114	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	465	0	0
T48	504	0	0	0
T61	0	167	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	547	0	0
T78	0	286	0	0
T79	0	129	0	0
T81	0	90	0	0
T120	0	113	0	0
T142	0	128	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T5,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T22,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T22
1	0	Covered	T5,T6,T2
1	1	Covered	T2,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T22,T61
0	1	Covered	T22,T78,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T22,T61
0	1	Unreachable
1	0	Covered	T4,T22,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T22
DetectSt	168	Covered	T4,T22,T61
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T22,T61

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T22,T61
DebounceSt->IdleSt	163	Covered	T2,T22,T78
DetectSt->IdleSt	186	Covered	T22,T78,T81
DetectSt->StableSt	191	Covered	T4,T22,T61
IdleSt->DebounceSt	148	Covered	T2,T4,T22
StableSt->IdleSt	206	Covered	T4,T22,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T22
0	1	Covered	T2,T4,T22
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T22,T61
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T22,T61
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T22,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T78,T81
DetectSt	-	-	-	-	0	1	-	Covered	T4,T22,T61
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T22,T61
StableSt	-	-	-	-	-	-	0	Covered	T4,T22,T61
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	160	0	0
CntIncr_A	7903577	62142	0	0
CntNoWrap_A	7903577	7250927	0	0
DetectStDropOut_A	7903577	11	0	0
DetectedOut_A	7903577	69154	0	0
DetectedPulseOut_A	7903577	50	0	0
DisabledIdleSt_A	7903577	6269595	0	0
DisabledNoDetection_A	7903577	6271875	0	0
EnterDebounceSt_A	7903577	100	0	0
EnterDetectSt_A	7903577	61	0	0
EnterStableSt_A	7903577	50	0	0
PulseIsPulse_A	7903577	50	0	0
StayInStableSt	7903577	69104	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_sticky_sva.StableStDropOut_A	7903577	7541	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	160	0	0
T2	1099	2	0	0
T3	596	0	0	0
T4	0	2	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	11	0	0
T41	0	2	0	0
T48	504	0	0	0
T61	0	2	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	6	0	0
T78	0	7	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	62142	0	0
T2	1099	114	0	0
T3	596	0	0	0
T4	0	13	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	324	0	0
T41	0	50	0	0
T48	504	0	0	0
T61	0	10	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	174	0	0
T78	0	350	0	0
T79	0	44	0	0
T80	0	70	0	0
T81	0	192	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250927	0	0
T1	25831	25363	0	0
T2	1099	696	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	11	0	0
T22	166215	3	0	0
T42	15471	0	0	0
T61	3451	0	0	0
T78	0	1	0	0
T81	0	2	0	0
T107	32359	0	0	0
T134	529	0	0	0
T135	507	0	0	0
T142	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	430	0	0	0
T161	616	0	0	0
T162	521	0	0	0
T163	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	69154	0	0
T4	1937	87	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	468	0	0
T41	0	218	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	44	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	354	0	0
T78	0	1	0	0
T79	0	93	0	0
T80	0	446	0	0
T81	0	67	0	0
T140	0	430	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	50	0	0
T4	1937	1	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	2	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	1	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6269595	0	0
T1	25831	25363	0	0
T2	1099	244	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6271875	0	0
T1	25831	25373	0	0
T2	1099	245	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	100	0	0
T2	1099	2	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	6	0	0
T41	0	1	0	0
T48	504	0	0	0
T61	0	1	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	3	0	0
T78	0	5	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	61	0	0
T4	1937	1	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	5	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	1	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T142	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	50	0	0
T4	1937	1	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	2	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	1	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	50	0	0
T4	1937	1	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	2	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	1	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	69104	0	0
T4	1937	86	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	466	0	0
T41	0	217	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	43	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	351	0	0
T79	0	92	0	0
T80	0	445	0	0
T81	0	66	0	0
T140	0	429	0	0
T143	0	71	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7541	0	0
T4	1937	498	0	0
T7	850	0	0	0
T8	602	0	0	0
T22	0	162	0	0
T41	0	358	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T59	1557	0	0	0
T60	1418	0	0	0
T61	0	334	0	0
T71	502	0	0	0
T73	440	0	0	0
T77	0	138	0	0
T78	0	28	0	0
T79	0	38	0	0
T80	0	168	0	0
T81	0	162	0	0
T140	0	88	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T22
1	0	Covered	T1,T5,T6
1	1	Covered	T2,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T22
0	1	Covered	T22,T77,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T22
0	1	Unreachable
1	0	Covered	T2,T4,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T22
DetectSt	168	Covered	T2,T4,T22
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T22
DebounceSt->IdleSt	163	Covered	T22,T61,T80
DetectSt->IdleSt	186	Covered	T22,T77,T79
DetectSt->StableSt	191	Covered	T2,T4,T22
IdleSt->DebounceSt	148	Covered	T2,T4,T22
StableSt->IdleSt	206	Covered	T2,T4,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T22
0	1	Covered	T2,T4,T22
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T22
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T61,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T77,T79
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T22
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	180	0	0
CntIncr_A	7903577	49836	0	0
CntNoWrap_A	7903577	7250907	0	0
DetectStDropOut_A	7903577	22	0	0
DetectedOut_A	7903577	155986	0	0
DetectedPulseOut_A	7903577	44	0	0
DisabledIdleSt_A	7903577	6269595	0	0
DisabledNoDetection_A	7903577	6271875	0	0
EnterDebounceSt_A	7903577	115	0	0
EnterDetectSt_A	7903577	66	0	0
EnterStableSt_A	7903577	44	0	0
PulseIsPulse_A	7903577	44	0	0
StayInStableSt	7903577	155942	0	0
gen_high_event_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_sticky_sva.StableStDropOut_A	7903577	449968	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	180	0	0
T2	1099	2	0	0
T3	596	0	0	0
T4	0	2	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	8	0	0
T41	0	2	0	0
T48	504	0	0	0
T61	0	3	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	8	0	0
T78	0	2	0	0
T79	0	4	0	0
T80	0	4	0	0
T81	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	49836	0	0
T2	1099	35	0	0
T3	596	0	0	0
T4	0	84	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	282	0	0
T41	0	96	0	0
T48	504	0	0	0
T61	0	168	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	352	0	0
T78	0	41	0	0
T79	0	28	0	0
T80	0	368	0	0
T81	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250907	0	0
T1	25831	25363	0	0
T2	1099	696	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	22	0	0
T22	166215	1	0	0
T42	15471	0	0	0
T61	3451	0	0	0
T77	0	2	0	0
T79	0	1	0	0
T107	32359	0	0	0
T134	529	0	0	0
T135	507	0	0	0
T144	0	2	0	0
T146	0	4	0	0
T158	0	1	0	0
T160	430	0	0	0
T161	616	0	0	0
T162	521	0	0	0
T163	425	0	0	0
T164	0	2	0	0
T165	0	3	0	0
T166	0	2	0	0
T167	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	155986	0	0
T2	1099	75	0	0
T3	596	0	0	0
T4	0	468	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	557	0	0
T41	0	410	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	180	0	0
T78	0	314	0	0
T79	0	1	0	0
T140	0	312	0	0
T142	0	150	0	0
T143	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	44	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	2	0	0
T41	0	1	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6269595	0	0
T1	25831	25363	0	0
T2	1099	244	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6271875	0	0
T1	25831	25373	0	0
T2	1099	245	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	115	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	5	0	0
T41	0	1	0	0
T48	504	0	0	0
T61	0	3	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	4	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	66	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	3	0	0
T41	0	1	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	4	0	0
T78	0	1	0	0
T79	0	2	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	44	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	2	0	0
T41	0	1	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	44	0	0
T2	1099	1	0	0
T3	596	0	0	0
T4	0	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	2	0	0
T41	0	1	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	155942	0	0
T2	1099	74	0	0
T3	596	0	0	0
T4	0	467	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	555	0	0
T41	0	409	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	178	0	0
T78	0	313	0	0
T114	0	133	0	0
T140	0	311	0	0
T142	0	149	0	0
T143	0	114	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	449968	0	0
T2	1099	337	0	0
T3	596	0	0	0
T4	0	50	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	139360	0	0
T41	0	134	0	0
T48	504	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T77	0	108	0	0
T78	0	116	0	0
T79	0	89	0	0
T140	0	250	0	0
T142	0	41	0	0
T143	0	83	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T40,T25,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T40,T25,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T40,T25,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T25,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T40,T25,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T25,T38
0	1	Covered	T113
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T25,T38
0	1	Covered	T40,T38,T41
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T25,T38
1	-	Covered	T40,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T25,T38
DetectSt	168	Covered	T40,T25,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T40,T25,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T25,T38
DebounceSt->IdleSt	163	Covered	T108
DetectSt->IdleSt	186	Covered	T113
DetectSt->StableSt	191	Covered	T40,T25,T38
IdleSt->DebounceSt	148	Covered	T40,T25,T38
StableSt->IdleSt	206	Covered	T40,T25,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T25,T38
0	1	Covered	T40,T25,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T25,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T25,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T25,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T25,T38
DetectSt	-	-	-	-	1	-	-	Covered	T113
DetectSt	-	-	-	-	0	1	-	Covered	T40,T25,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T38,T41
StableSt	-	-	-	-	-	-	0	Covered	T40,T25,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	95	0	0
CntIncr_A	7903577	177971	0	0
CntNoWrap_A	7903577	7250992	0	0
DetectStDropOut_A	7903577	1	0	0
DetectedOut_A	7903577	160162	0	0
DetectedPulseOut_A	7903577	46	0	0
DisabledIdleSt_A	7903577	6695992	0	0
DisabledNoDetection_A	7903577	6698223	0	0
EnterDebounceSt_A	7903577	48	0	0
EnterDetectSt_A	7903577	47	0	0
EnterStableSt_A	7903577	46	0	0
PulseIsPulse_A	7903577	46	0	0
StayInStableSt	7903577	160092	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	95	0	0
T22	166215	0	0	0
T25	13294	2	0	0
T38	0	2	0	0
T39	8763	0	0	0
T40	850	2	0	0
T41	0	2	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	2	0	0
T140	0	4	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	6	0	0
T169	0	2	0	0
T170	0	2	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	177971	0	0
T22	166215	0	0	0
T25	13294	79	0	0
T38	0	54	0	0
T39	8763	0	0	0
T40	850	73	0	0
T41	0	100	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	49	0	0
T140	0	32	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	132504	0	0
T169	0	79	0	0
T170	0	18	0	0
T171	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250992	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1	0	0
T113	2948	1	0	0
T164	1297	0	0	0
T172	16800	0	0	0
T173	2203	0	0	0
T174	538	0	0	0
T175	402	0	0	0
T176	709	0	0	0
T177	522	0	0	0
T178	552	0	0	0
T179	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	160162	0	0
T22	166215	0	0	0
T25	13294	186	0	0
T38	0	17	0	0
T39	8763	0	0	0
T40	850	43	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	38	0	0
T140	0	94	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	125	0	0
T169	0	43	0	0
T170	0	44	0	0
T171	0	129	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	46	0	0
T22	166215	0	0	0
T25	13294	1	0	0
T38	0	1	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	1	0	0
T140	0	2	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6695992	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6698223	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	48	0	0
T22	166215	0	0	0
T25	13294	1	0	0
T38	0	1	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	1	0	0
T140	0	2	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	47	0	0
T22	166215	0	0	0
T25	13294	1	0	0
T38	0	1	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	1	0	0
T140	0	2	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	46	0	0
T22	166215	0	0	0
T25	13294	1	0	0
T38	0	1	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	1	0	0
T140	0	2	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	46	0	0
T22	166215	0	0	0
T25	13294	1	0	0
T38	0	1	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	1	0	0
T140	0	2	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	160092	0	0
T22	166215	0	0	0
T25	13294	184	0	0
T38	0	16	0	0
T39	8763	0	0	0
T40	850	42	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T111	0	36	0	0
T140	0	91	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	121	0	0
T169	0	42	0	0
T170	0	42	0	0
T171	0	127	0	0
T180	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	21	0	0
T22	166215	0	0	0
T25	13294	0	0	0
T38	0	1	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T126	0	1	0	0
T140	0	1	0	0
T160	430	0	0	0
T161	616	0	0	0
T168	0	2	0	0
T169	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T25,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T25,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T25,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T39
1	0	Covered	T1,T5,T14
1	1	Covered	T3,T25,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T39
0	1	Covered	T111,T183,T184
1	0	Covered	T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T39
0	1	Covered	T25,T39,T22
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T25,T39
1	-	Covered	T25,T39,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T25,T39
DetectSt	168	Covered	T3,T25,T39
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T25,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T25,T39
DebounceSt->IdleSt	163	Covered	T39,T168,T81
DetectSt->IdleSt	186	Covered	T111,T53,T183
DetectSt->StableSt	191	Covered	T3,T25,T39
IdleSt->DebounceSt	148	Covered	T3,T25,T39
StableSt->IdleSt	206	Covered	T25,T39,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T25,T39
0	1	Covered	T3,T25,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T39
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T25,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T25,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T168,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T25,T39
DetectSt	-	-	-	-	1	-	-	Covered	T111,T53,T183
DetectSt	-	-	-	-	0	1	-	Covered	T3,T25,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T39,T22
StableSt	-	-	-	-	-	-	0	Covered	T3,T25,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	153	0	0
CntIncr_A	7903577	242490	0	0
CntNoWrap_A	7903577	7250934	0	0
DetectStDropOut_A	7903577	5	0	0
DetectedOut_A	7903577	66867	0	0
DetectedPulseOut_A	7903577	64	0	0
DisabledIdleSt_A	7903577	6447291	0	0
DisabledNoDetection_A	7903577	6449512	0	0
EnterDebounceSt_A	7903577	83	0	0
EnterDetectSt_A	7903577	70	0	0
EnterStableSt_A	7903577	64	0	0
PulseIsPulse_A	7903577	64	0	0
StayInStableSt	7903577	66779	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	2553	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	153	0	0
T3	596	2	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	4	0	0
T25	0	6	0	0
T38	0	4	0	0
T39	0	3	0	0
T41	0	6	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T81	0	1	0	0
T111	0	2	0	0
T168	0	4	0	0
T169	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	242490	0	0
T3	596	23	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	92	0	0
T25	0	113	0	0
T38	0	108	0	0
T39	0	124	0	0
T41	0	259	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T81	0	16	0	0
T111	0	49	0	0
T168	0	132504	0	0
T169	0	158	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250934	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	5	0	0
T41	263390	0	0	0
T111	547	1	0	0
T139	11128	0	0	0
T141	32603	0	0	0
T183	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	406	0	0	0
T187	411	0	0	0
T188	422	0	0	0
T189	29382	0	0	0
T190	22091	0	0	0
T191	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	66867	0	0
T3	596	139	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	347	0	0
T25	0	246	0	0
T38	0	87	0	0
T39	0	5	0	0
T41	0	494	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T140	0	15	0	0
T168	0	11316	0	0
T169	0	191	0	0
T171	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	64	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	2	0	0
T25	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T140	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6447291	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6449512	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	83	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	2	0	0
T25	0	3	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T81	0	1	0	0
T111	0	1	0	0
T168	0	3	0	0
T169	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	70	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	2	0	0
T25	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T111	0	1	0	0
T140	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	64	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	2	0	0
T25	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T140	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	64	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	2	0	0
T25	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T140	0	2	0	0
T168	0	1	0	0
T169	0	2	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	66779	0	0
T3	596	137	0	0
T4	1937	0	0	0
T7	850	0	0	0
T22	0	344	0	0
T25	0	243	0	0
T38	0	84	0	0
T39	0	4	0	0
T41	0	489	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T140	0	13	0	0
T168	0	11315	0	0
T169	0	188	0	0
T171	0	140	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	2553	0	0
T2	1099	0	0	0
T3	0	1	0	0
T5	4417	12	0	0
T6	651	0	0	0
T7	0	1	0	0
T13	5067	0	0	0
T14	427	3	0	0
T15	508	6	0	0
T16	502	5	0	0
T17	5367	0	0	0
T18	502	6	0	0
T48	504	3	0	0
T70	0	4	0	0
T73	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	40	0	0
T22	166215	1	0	0
T25	13294	3	0	0
T38	0	1	0	0
T39	8763	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T140	0	2	0	0
T160	430	0	0	0
T161	616	0	0	0
T162	521	0	0	0
T163	425	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T171	0	1	0	0
T192	0	1	0	0